| Patent application number | Description | Published |
| 20090079916 | LIQUID CRYSTAL DISPLAY AND METHOD FOR MANUFACTURING THE SAME - A liquid crystal display (LCD) device and a method for manufacturing the same are discussed. According to an embodiment, the liquid crystal display device includes a first substrate and a second substrate facing each other, wherein each of the first and second substrates includes pixel regions to form a matrix, a black matrix layer arranged in a region other than the pixel regions gate lines and data lines arranged in a portion corresponding to the black matrix layer spacers arranged in predetermined portions provided on the black matrix layer wherein each spacer includes one or more balls, and a solid to adhere the balls to the first or second substrate, and a liquid crystal layer filled between the first substrate and the second substrate. | 03-26-2009 |
| 20090086136 | Liquid crystal display and method for manufacturing the same - A liquid crystal display device includes a first substrate and a second substrate facing each other, a gate line and a common line arranged adjacent and parallel to each other on the first substrate, a data line crossing the gate line, a spacer comprising a plurality of balls, formed on the first or second substrate in a lower-height and flat region provided between the gate line and the common line, and a liquid crystal layer filled between the first substrate and the second substrate. | 04-02-2009 |
| 20090091677 | LIQUID CRYSTAL DISPLAY AND METHOD FOR MANUFACTURING THE SAME - Disclosed herein are a liquid crystal display (LCD) device and a method for manufacturing the same, capable of preventing problems (i.e., movement of balls, damage to the surfaces that face spacers upon application of predetermined pressure, and variation in cell gap) associated with the use of the ball spacers. The liquid crystal display device includes a first substrate and a second substrate facing each other, a spacer formed on the first substrate, wherein the spacer includes a plurality of balls and a solid to aggregate the balls together and adhere the balls to the first substrate, a hard coating layer formed on the second substrate facing the spacer, and a liquid crystal layer filled between the first substrate and the second substrate. | 04-09-2009 |
| 20090091702 | Liquid crystal display and method for manufacturing the same - Disclosed is a liquid crystal display (LCD) device and a method for manufacturing the same, capable of maintaining a cell gap and preventing press defects caused by application of a predetermined external pressure via the use of ball spacers. | 04-09-2009 |
| 20110171766 | LIQUID CRYSTAL DISPLAY AND METHOD FOR MANUFACTURING THE SAME - Disclosed is a liquid crystal display (LCD) device and a method for manufacturing the same, capable of maintaining a cell gap and preventing press defects caused by application of a predetermined external pressure via the use of ball spacers. | 07-14-2011 |
| 20120008084 | LIQUID CRYSTAL DISPLAY AND METHOD FOR MANUFACTURING THE SAME - A liquid crystal display (LCD) device and a method for manufacturing the same are discussed. According to an embodiment, the liquid crystal display device includes a first substrate and a second substrate facing each other, wherein each of the first and second substrates includes pixel regions to form a matrix, a black matrix layer arranged in a region other than the pixel regions gate lines and data lines arranged in a portion corresponding to the black matrix layer spacers arranged in predetermined portions provided on the black matrix layer wherein each of the plurality of spacers includes one or more balls, and a solid to adhere the one or more balls to the first or second substrate, and a liquid crystal layer filled between the first substrate and the second substrate. | 01-12-2012 |
| Patent application number | Description | Published |
| 20090090294 | METHOD AND APPARATUS FOR MANUFACTURING AN ULTRA LOW DEFECT SEMICONDUCTOR SINGLE CRYSTALLINE INGOT - The present invention relates to a method for manufacturing an ultra low defect semiconductor single crystalline ingot, which uses a Czochralski process for growing a semiconductor single crystalline ingot through a solid-liquid interface by dipping a seed into a semiconductor melt received in a quartz crucible and slowly pulling up the seed while rotating the seed, wherein a defect-free margin is controlled by increasing or decreasing a heat space on a surface of the semiconductor melt according to change in length of the single crystalline ingot as progress of the single crystalline ingot growth process. | 04-09-2009 |
| 20090114147 | SEMICONDUCTOR SINGLE CRYSTAL GROWTH METHOD HAVING IMPROVEMENT IN OXYGEN CONCENTRATION CHARACTERISTICS - The present invention relates to a semiconductor single crystal growth method, which uses a Czochralski process for growing a semiconductor single crystal through a solid-liquid interface by dipping a seed into a semiconductor melt received in a quartz crucible and pulling up the seed while rotating the quartz crucible and applying a strong horizontal magnetic field, wherein the seed is pulled up while the quartz crucible is rotated with a rate between 0.6 rpm and 1.5 rpm. | 05-07-2009 |
| 20090183670 | APPARATUS FOR MANUFACTURING HIGH-QUALITY SEMICONDUCTOR SINGLE CRYSTAL INGOT AND METHOD USING THE SAME - The present invention relates to an apparatus for manufacturing a high-quality semiconductor single crystal ingot and a method using the same. The apparatus of the present invention includes a quartz crucible, a heater installed around a side wall of the quartz crucible, a single crystal pulling means for pulling a single crystal from the semiconductor melt received in the quartz crucible, and a magnetic field applying means for forming a Maximum Gauss Plane (MGP) at a location of ML-1000 mm to ML-350 mm based on a Melt Level (ML) of the melt surface, and applying a strong magnetic field of 3000 to 5500 Gauss to an intersection between the MGP and the side wall of the quartz crucible and a weak magnetic field of 1500 to 3000 Gauss below a solid-liquid interface. | 07-23-2009 |
| 20090272948 | High Quality Single Crystal and Method of Growing the Same - Disclosed is a method of growing a single crystal from a melt contained in a crucible. The method includes the step of making the temperature of a melt increase gradually to a maximum point and then decrease gradually along the axis parallel to the lengthwise direction of the single crystal from the interface of the single crystal and the melt to the bottom of the crucible. The increasing temperature of the melt is kept to preferably have a greater temperature gradient than the decreasing temperature thereof. Preferably, the axis is set to pass through the center of the single crystal. Preferably, the convection of the inner region of the melt is made smaller than that of the outer region thereof. | 11-05-2009 |
| 20110197809 | SINGLE CRYSTAL COOLER AND SINGLE CRYSTAL GROWER INCLUDING THE SAME - Provided are a single crystal cooler and a single crystal grower including the same. The single crystal cooler includes a cooling main body and a passage. The passage is formed on an inner wall and an outer wall of the cooling main body. The passage allows cooling materials to move therethrough. The single crystal cooler has a cylindrical shape. A first inner diameter R | 08-18-2011 |
| Patent application number | Description | Published |
| 20090159895 | Array substrate for liquid crystal display device and fabricating method of the same - A method of manufacturing an array substrate for a liquid crystal display device includes forming a gate line, a gate pad, a gate electrode, and a data pad on a substrate through a first mask process, forming a gate insulating layer on a substantial part of an entire surface of the substrate including the gate line, the gate pad, the gate electrode, and the data pad, forming a data line, a source-drain pattern and an active layer on the gate insulating layer and forming a gate pad contact hole and a data pad contact hole in the gate insulating layer through a second mask process, and forming a pixel electrode, a gate pad terminal, a data pad terminal, a source electrode, a drain electrode, and an ohmic contact layer through a third mask process. | 06-25-2009 |
| 20100001278 | THIN FILM TRANSISTOR (TFT) ARRAY SUBSTRATE AND FABRICATING METHOD THEREOF THAT PROTECT THE TFT AND A PIXEL ELECTRODE WITHOUT A PROTECTIVE FILM - A thin film transistor array substrate and a fabricating method thereof are disclosed. The thin film transistor array substrate protects a thin film transistor without a protective film and accordingly reduces the manufacturing cost. In the thin film transistor array substrate, a gate electrode is connected to a gate line. A source electrode is connected to a data line crossing the gate line to define a pixel area. A drain electrode is opposed to the source electrode with a channel therebetween. A semiconductor layer is in the channel. A pixel electrode in the pixel area contacts the drain electrode over substantially the entire overlapping area between the two. A channel protective film is provided on the semiconductor layer corresponding to the channel to protect the semiconductor layer. | 01-07-2010 |
| 20100075472 | TFT array substrate and the fabrication method thereof - A TFT array substrate includes: a gate electrode connected to a gate line; a source electrode connected to a data line crossing the gate line to define a pixel region; a drain electrode which is opposite to the source electrode with a channel in between; a semiconductor layer defining the channel between the source electrode and the drain electrode; a pixel electrode in the pixel region and connected to the drain electrode; a channel passivation layer on the channel of the semiconductor layer; a gate pad extending from the gate line, where a semiconductor pattern and a transparent conductive pattern are formed; a data pad connected to the data line, where the transparent conductive pattern is formed; and a gate insulating layer formed under the semiconductor layer, the gate line and the gate pad, and the data line and the data pad. | 03-25-2010 |
| 20100289023 | Array substrate for dislay device and method of fabricating the same - A method of fabricating an array substrate for a display device includes: forming a buffer layer on a substrate having a pixel region; sequentially forming a gate electrode of impurity-doped polycrystalline silicon, a gate insulating layer and an active layer of intrinsic polycrystalline silicon on the buffer layer in the pixel region; forming an interlayer insulating layer of an inorganic insulating material on the active layer; sequentially forming a source barrier pattern, a source ohmic contact layer and a source electrode on the interlayer insulating layer, sequentially forming a drain barrier pattern, a drain ohmic contact layer and a drain electrode on the interlayer insulating layer, and sequentially forming a first dummy pattern, a second dummy pattern and a data line on the interlayer insulating layer; forming a first passivation layer on a surface of the interlayer insulating layer including the source electrode, the drain electrode and the data line formed thereon; forming a gate line on the first passivation layer; forming a second passivation layer on a surface of the first passivation layer including the gate line formed thereon; and forming a pixel electrode on the second passivation layer. | 11-18-2010 |
| 20100315584 | ARRAY SUBSTRATE FOR IPS-MODE LCD DEVICE AND METHOD OF FABRICATING THE SAME - Provided is an array substrate for an IPS-mode LCD device and method of fabricating the same that prevents a problem referred to as wavy noise. The IPS-mode LCD device and method have a shorter processing time and low error rate without an increase in fabrication and production costs. | 12-16-2010 |
| 20100323482 | TFT ARRAY SUBSTRATE AND THE FABRICATION METHOD THEREOF - A TFT array substrate is provided. The TFT array substrate includes: a gate electrode connected to a gate line; a source electrode connected to a data line that crosses the gate line and defines a pixel region; a drain electrode facing the source electrode with a channel between; a semiconductor layer forming the channel in between the source electrode and the drain electrode; a pixel electrode in the pixel region and contacting the drain electrode; a channel passivation layer formed on the semiconductor layer; a gate pad with a gate pad lower electrode that extends from the gate line; and a data pad having a data pad lower electrode separated from the data line. | 12-23-2010 |
| 20120104405 | ARRAY SUBSTRATE FOR ORGANIC ELECTROLUMINESCENT DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating an array substrate for an organic electroluminescent device includes forming a semiconductor layer of polysilicon in an element region, and a semiconductor pattern of polysilicon in a storage region on a substrate; forming a multiple-layered gate electrode corresponding to a center portion of the semiconductor layer and a first storage electrode corresponding to the semiconductor pattern; performing an impurity-doping to make a portion of the semiconductor layer not covered by the gate electrode into an ohmic contact layer and make the semiconductor pattern into a second storage electrode; forming source and drain electrodes and a third storage electrode corresponding to the first storage electrode; forming a first electrode contacting the drain electrode and a fourth storage electrode corresponding to the third storage electrode. | 05-03-2012 |