Cho, CA
Aesop Cho, Foster City, CA US
Patent application number | Description | Published |
---|---|---|
20100310512 | ANTIVIRAL COMPOUNDS - The invention is related to anti-viral compounds, compositions containing such compounds, and therapeutic methods that include the administration of such compounds, as well as to processes and intermediates useful for preparing such compounds. | 12-09-2010 |
20120157404 | ANTIVIRAL COMPOUNDS - The invention is related to anti-viral compounds, compositions containing such compounds, and therapeutic methods that include the administration of such compounds, as well as to processes and intermediates useful for preparing such compounds. | 06-21-2012 |
20120264711 | ANTIVIRAL COMPOUNDS - The invention is related to anti-viral compounds, compositions containing such compounds, and therapeutic methods that include the administration of such compounds, as well as to processes and intermediates useful for preparing such compounds. | 10-18-2012 |
20130137877 | ANTIVIRAL COMPOUNDS - The invention is related to anti-viral compounds, compositions containing such compounds, and therapeutic methods that include the administration of such compounds, as well as to processes and intermediates useful for preparing such compounds. | 05-30-2013 |
Alvin Aram Cho, San Diego, CA US
Patent application number | Description | Published |
---|---|---|
20120220021 | HERBICIDE RESISTANT ORGANISMS - Disclosed herein are transformed non-vascular photosynthetic organisms that are herbicide resistant, nucleotides and vectors useful in conducting such transformations, and transformed strains produced by such transformations. | 08-30-2012 |
20120288918 | SALT TOLERANT ORGANISMS - Disclosed herein are transformed non-vascular photosynthetic organisms that are salt tolerant, nucleotides and vectors useful in conducting such transformations, and transformed strains produced by such transformations. | 11-15-2012 |
Brian Cho, Berkeley, CA US
Patent application number | Description | Published |
---|---|---|
20090298104 | REFERENCE ELECTRODES HAVING AN EXTENDED LIFETIME FOR USE IN LONG TERM AMPEROMETRIC SENSORS - The present application provides Ag/AgCl based reference electrodes having an extended lifetime that are suitable for use in long term amperometric sensors. Electrochemical sensors equipped with reference electrodes described herein demonstrate considerable stability and extended lifetime in a variety of conditions. | 12-03-2009 |
20100270180 | SERVICE-DETECTABLE ANALYTE SENSORS AND METHODS OF USING AND MAKING SAME - Generally, embodiments of the invention relate to analyte determining devices (e.g., electrochemical analyte monitoring systems) that include an indicator element that provides information relating to service history of the analyte determining devices, including, for example, previous use of the analyte determining devices. Also provided are systems and methods of using the, for example electrochemical, analyte determining devices in analyte monitoring. | 10-28-2010 |
20110046466 | Analyte Sensors Including Nanomaterials and Methods of Using Same - Generally, embodiments of the invention relate to analyte determining methods and devices (e.g., electrochemical analyte monitoring systems) that have improved uniformity of distribution of one or more components, improved stability, and improved response time of the sensor by inclusion of a nanomaterial, such as inert inorganic nanomaterials, where the components are disposed proximate to a working electrode of in vivo and/or in vitro analyte sensors, e.g., continuous and/or automatic in vivo monitoring using analyte sensors and/or test strips. Also provided are systems and methods of using the, for example electrochemical, analyte sensors in analyte monitoring. | 02-24-2011 |
20130053667 | Reference Electrodes Having an Extended Lifetime for use in Long Term Amperometric Sensors - The present application provides Ag/AgCl based reference electrodes having an extended lifetime that are suitable for use in long term amperometric sensors. Electrochemical sensors equipped with reference electrodes described herein demonstrate considerable stability and extended lifetime in a variety of conditions. | 02-28-2013 |
20130184546 | Service-Detectable Analyte Sensors and Methods of Using and Making Same - Generally, embodiments of the invention relate to analyte determining devices (e.g., electrochemical analyte monitoring systems) that include an indicator element that provides information relating to service history of the analyte determining devices, including, for example, previous use of the analyte determining devices. Also provided are systems and methods of using the, for example electrochemical, analyte determining devices in analyte monitoring. | 07-18-2013 |
Catherine M. Cho, Redwood City, CA US
Patent application number | Description | Published |
---|---|---|
20110294170 | Pentose Fermentation By a Recombinant Microorganism - The present invention provides recombinant nucleic acid constructs comprising a xylose isomerase polynucleotide, a recombinant fungal host cell comprising a recombinant xylose isomerase polynucleotide, and related methods. | 12-01-2011 |
20130004998 | PENTOSE FERMENTATION BY A RECOMBINANT MICROORGANISM - The present invention provides recombinant nucleic acid constructs comprising a xylose isomerase polynucleotide, a recombinant fungal host cell comprising a recombinant xylose isomerase polynucleotide, and related methods. | 01-03-2013 |
20130095530 | BETA-GLUCOSIDASE VARIANT ENZYMES AND RELATED POLYNUCLEOTIDES - The invention provides variants of the | 04-18-2013 |
20140004586 | BETA-GLUCOSIDASE VARIANT ENZYMES AND RELATED POLYNUCLEOTIDES | 01-02-2014 |
20140017765 | PENTOSE FERMENTATION BY A RECOMBINANT MICROORGANISM - The present invention provides recombinant nucleic acid constructs comprising a xylose isomerase polynucleotide, a recombinant fungal host cell comprising a recombinant xylose isomerase polynucleotide, and related methods. | 01-16-2014 |
20140242674 | PENTOSE FERMENTATION BY A RECOMBINANT MICROORGANISM - The present invention provides recombinant nucleic acid constructs comprising a xylose isomerase polynucleotide, a recombinant fungal host cell comprising a recombinant xylose isomerase polynucleotide, and related methods. | 08-28-2014 |
20150050658 | GENE SHUFFLING METHODS - Disclosed methods pertain to nucleic acid shuffling techniques that employ repeated short extension cycles. In each such cycle, strand extension along a template fragment is limited such that the strand extends only for a relatively short length (e.g., a few base pairs). Repeated short extension cycles cause many template switches during shuffling and thereby produce chimeric products with many crossovers. The methods may employ a pre-shuffling truncation or excision operation in which one or more parent nucleic acids has a portion of its full-length sequence truncated or excised. Shuffling with truncated parent nucleic acids introduces crossovers at the location of the truncation. Apparatus for implementing the disclosed methods may include appropriately configured thermocycling tools. | 02-19-2015 |
Charles Cho, San Diego, CA US
Patent application number | Description | Published |
---|---|---|
20090156523 | METHODS AND COMPOSITIONS FOR MODULATING FOXO1 ACTIVITY AND INSULIN SIGNALING - The invention provides methods for modulating insulin signaling pathway and methods for treating insulin resistance. The methods employ agents which modulate FOXO1 subcellular localization. The invention also provides methods of screening for compounds that modulate insulin signaling related activities such as gluconeogenesis and cell proliferation. | 06-18-2009 |
Charles Y. Cho, San Diego, CA US
Patent application number | Description | Published |
---|---|---|
20110243923 | ORGANIC COMPOUNDS - The present invention relates to modulators of the interaction between Epstein-Barr Virus induced receptor-2 (EBi2) and cholest-5-ene-3b,7b,25-triol (7, 25-dihydroxycholesterol) (“7,25DHC”) and/or cholest-5-ene-3b, 7b-diol (7-hydroxycholesterol) (“7HC”). The modulator maybe a small chemical molecule, antibody or other therapeutic protein. Methods of medical treatment and methods of identifying modulators are also described. | 10-06-2011 |
Ching-Fai Cho, La Canada, CA US
Patent application number | Description | Published |
---|---|---|
20090091402 | Compact stripline low frequency band reject filter - A low frequency reject filter element is formed on a printed circuit board that utilizes the fact that power transmission in a waveguide is cut-off below a certain frequency. A quasi waveguide cavity is formed in printed circuit board using the top and bottom ground plane of the stripline circuit and using conductive via holes to form the side walls of the cavity. Waveguide cavity mode is launched from the input and output striplines by shorting them to ground. Transformers and matching via hole elements may be used to improve matching. The resulting filter is compact and is highly effective in suppressing low frequency transmissions. | 04-09-2009 |
Christine Cho, Cupertino, CA US
Patent application number | Description | Published |
---|---|---|
20100332283 | SOCIAL NETWORKING IN SHOPPING ENVIRONMENTS - This is directed to a system and method for providing social networking services using a portable electronic device. In some embodiments, a user may identify one or more articles of interest and transmit identifying information for the articles to mobile or other devices of the user's friends. The user's friends can review the identified articles, and provide comments for the user. For example, the user's friends can give a thumbs up/down, a star rating, a comment (e.g., text, audio or video), or any other type of comment. In some embodiments, the user can request the assistance of a salesperson using the social networking application device, for example to request recommended articles based on a particular event or need. In some embodiments, the social networking application can provide information to or from a kiosk. | 12-30-2010 |
Christine Kim Cho, Cupertino, CA US
Patent application number | Description | Published |
---|---|---|
20100191578 | SYSTEMS AND METHODS FOR PROVIDING ENHANCED ACCESS TO HIGH FASHION USING A PORTABLE ELECTRONIC DEVICE - This is directed to systems and methods for enhancing a user's experience when shopping for high fashion items. In some embodiments, an integrated application available on an electronic device can provide information for promotional and invitation-only events, allow a user to browse and search through fashion items, recommend fashion items to purchase based on outfits desired by the user, check for the availability of particular fashion items, and view or providing ratings or reviews for stores or fashion items. | 07-29-2010 |
20100191770 | SYSTEMS AND METHODS FOR PROVIDING A VIRTUAL FASHION CLOSET - This is directed to systems and methods for providing a virtual fashion closet. Fashion items can be added to the Virtual Closet. Outfits may then be created by combining two or more of the fashion items. In some embodiments, the Virtual Closet system can create recommended outfits based on weather, season, or the user's calendar. The Virtual Closet system can allow a vendor to send recommended fashion items that may complete an outfit to a user for potential purchasing. In some embodiments, a social networking Virtual Closet can be provided. The social networking Virtual Closet can allow friends to see each other's Virtual Closets, recommend outfits to one another, recommend fashion items to buy, recommend fashion items to get rid of, recommend outfits to wear at a particular event, share and borrow each other's fashion items, or can otherwise suitably provide a social networking environment through the Virtual Closet. | 07-29-2010 |
20100198626 | SYSTEMS AND METHODS FOR ACCESSING SHOPPING CENTER SERVICES USING A PORTABLE ELECTRONIC DEVICE - This is directed to systems and methods for enhancing a user's experience at a shopping center. In some embodiments, an integrated application available on an electronic device can provide information for promotional and available sales of goods and services, allow a user to browse and search through available content providers of the shopping center, such as parking, restaurants, and clothing stores, to purchase content based on the personal needs of a user. In some embodiments, an application available on an electronic device can check for the availability of particular items and show ratings or reviews for stores carrying the items. In some embodiments, In particular, the integrated application can provide a “heat map” to indicate popular areas of or items in a mall. | 08-05-2010 |
Eung San Cho, Torrance, CA US
Patent application number | Description | Published |
---|---|---|
20110049690 | Direct contract leadless package for high current devices - Some exemplary embodiments of a direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached to a top side of the paddle portion and is enclosed by said mold compound, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations. | 03-03-2011 |
20110057300 | Direct contact leadless flip chip package for high current devices - Some exemplary embodiments of an advanced direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a mold compound enclosing a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached on top of the lead frame portions as a flip chip, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations. | 03-10-2011 |
20110278710 | Direct Contact Leadless Package - Some exemplary embodiments of a direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached to a top side of the paddle portion and is enclosed by said mold compound, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations. | 11-17-2011 |
20110278711 | Leadless Package for High Current Devices - Some exemplary embodiments of a direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached to a top side of the paddle portion and is enclosed by said mold compound, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations. | 11-17-2011 |
20120104586 | Direct Contact Flip Chip Package with Power Transistors - Some exemplary embodiments of an advanced direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a mold compound enclosing a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached on top of the lead frame portions as a flip chip, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations. | 05-03-2012 |
20120104587 | Direct Contact Semiconductor Package with Power Transistor - Some exemplary embodiments of an advanced direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a mold compound enclosing a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached on top of the lead frame portions as a flip chip, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations. | 05-03-2012 |
20120168922 | High Power Semiconductor Package with Conductive Clip - One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor, a sync transistor, a driver integrated circuit (IC) for driving the control and sync transistors, and a conductive clip electrically coupling a sync drain of the sync transistor to a first leadframe pad of the package, wherein the first leadframe pad of the package is electrically coupled to a control source of the control transistor using a wirebond. The conductive clip provides an efficient connection between the control source and the sync drain by direct mechanical connection and large surface area conduction. A sync source is electrically and mechanically coupled to a second leadframe pad providing a high current carrying capability, and high reliability. The resulting package has significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections. | 07-05-2012 |
20120168923 | High Power Semiconductor Package with Conductive Clip on Multiple Transistors - One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor, a sync transistor, a driver integrated circuit (IC) for driving the control and sync transistors, and a conductive clip extending from a sync drain on a top surface of the sync transistor to a control source on a top surface of the control transistor. The conductive clip may also connect to substrate pads such as a leadframe pad for current input and output. In this manner, the conductive clip provides an efficient connection between the control source and the sync drain by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections. | 07-05-2012 |
20120168924 | High Power Semiconductor Package with Multiple Conductive Clips - One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadframe and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections. | 07-05-2012 |
20120168925 | High Power Semiconductor Package with Conductive Clips and Flip Chip Driver IC - One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a leadframe, a flip chip driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. The source of the control transistor is electrically coupled to the drain of the sync transistor using the leadframe and one of the transistor conductive clips. In this manner, the leadframe and the conductive clips provide efficient current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections. | 07-05-2012 |
20120168926 | High Power Semiconductor Package with Conductive Clip and Flip Chip Driver IC with Integrated Control Transistor - One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a sync transistor with a top surface having a drain, a flip chip driver integrated circuit (IC) having an integrated control transistor, the flip chip driver IC driving the sync and control transistors, and a conductive clip electrically coupling the drain of the sync transistor to a common portion of the leadframe shared with a control source of the control transistor. In this manner, the leadframe and the conductive clip provide efficient current conduction by direct mechanical connection and large surface area conduction, significantly reducing package electrical resistance, form factor, complexity, and cost compared to conventional packages. Moreover, by integrating only the control transistor rather than both the control and sync transistor within the flip chip driver IC, the sync transistor may remain separate, simplifying manufacture and providing greater total surface area for thermal dissipation. | 07-05-2012 |
20120181624 | Stacked Half-Bridge Package with a Common Conductive Clip - According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to a common conductive clip, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the common conductive clip, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of the common conductive clip with the common conductive clip electrically and mechanically coupling the control source with the sync drain, where the common conductive clip has a conductive leg for providing electrical and mechanical connection to an output terminal leadframe. | 07-19-2012 |
20120181674 | Stacked Half-Bridge Package with a Common Conductive Leadframe - According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of a common conductive leadframe with the common conductive leadframe electrically and mechanically coupling the control source with the sync drain. The common conductive leadframe thereby serves as the output terminal. | 07-19-2012 |
20120181681 | Stacked Half-Bridge Package with a Current Carrying Layer - According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. A current carrying layer is situated on the sync drain; the control transistor and the sync transistor being stacked on one another, where the current carrying layer provides a high current connection between the sync drain and the control source. | 07-19-2012 |
20120292752 | Thermally Enhanced Semiconductor Package with Exposed Parallel Conductive Clip - One exemplary disclosed embodiment comprises a semiconductor package including an inside pad, a transistor, and a conductive clip coupled to the inside pad and a terminal of the transistor. A top surface of the conductive clip is substantially exposed at the top of the package, and a side surface of the conductive clip is exposed at a side of the package. By supporting the semiconductor package on an outside pad during the fabrication process and by removing the outside pad during singulation, the conductive clip may be kept substantially parallel and in alignment with the package substrate while optimizing the package form factor compared to conventional packages. The exposed top surface of the conductive clip may be further attached to a heat sink for enhanced thermal dissipation. | 11-22-2012 |
20120292753 | MULTI-TRANSISTOR EXPOSED CONDUCTIVE CLIP FOR HIGH POWER SEMICONDUCTOR PACKAGES - One exemplary disclosed embodiment comprises a semiconductor package including multiple transistors coupled to an exposed conductive clip. A driver integrated circuit (IC) may control the transistors to implement a buck converter. By exposing a top surface of the exposed conductive clip outside of a mold compound of the package, enhanced thermal performance is provided. Additionally, the conductive clip provides a short distance, high current carrying route between transistors of the package, providing higher electrical performance and reduced form factor compared to conventional designs with individually packaged transistors. | 11-22-2012 |
20120292754 | Common Drain Exposed Conductive Clip for High Power Semiconductor Packages - One exemplary disclosed embodiment comprises a semiconductor package including multiple transistors having a common drain coupled to an exposed conductive clip. A driver integrated circuit (IC) may control the transistors for various power applications. By exposing a top surface of the exposed conductive clip outside of a mold compound of the package, enhanced thermal performance is provided. Additionally, the conductive clip provides a short distance, high current carrying route between transistors of the package, providing higher electrical performance and reduced form factor compared to conventional designs with individually packaged transistors. | 11-22-2012 |
20130134524 | Multi-Transistor Exposed Conductive Clip for Semiconductor Packages - One exemplary disclosed embodiment comprises a semiconductor package including multiple transistors coupled to an exposed conductive clip. A driver integrated circuit (IC) may control the transistors to implement a buck converter. By exposing a top surface of the exposed conductive clip outside of a mold compound of the package, enhanced thermal performance is provided. Additionally, the conductive clip provides a short distance, high current carrying route between transistors of the package, providing higher electrical performance and reduced form factor compared to conventional designs with individually packaged transistors. | 05-30-2013 |
20130228794 | Stacked Half-Bridge Package with a Common Leadframe - According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package further includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of a common conductive leadframe with the common conductive leadframe electrically and mechanically coupling the control source with the sync drain. The common conductive leadframe thereby serves as the output terminal. | 09-05-2013 |
20130249072 | Direct Contact Package for Power Transistors - Some exemplary embodiments of a direct contact leadless package and related structure and method, especially suitable for packaging high current semiconductor devices, have been disclosed. One exemplary structure comprises a first contact lead frame portion, a paddle portion, and an extended contact lead frame portion held together by a mold compound. A first semiconductor device is attached to a top side of the paddle portion and is enclosed by said mold compound, while a second semiconductor device is attached to a bottom side of said paddle portion and is in electrical contact with said the first semiconductor device. The extended contact lead frame portion is in direct electrical contact with the second semiconductor device without using a bond wire. Alternative exemplary embodiments may include additional extended lead frame portions, paddle portions, and semiconductor devices in various configurations. | 09-26-2013 |
20130256807 | Integrated Dual Power Converter Package Having Internal Driver IC - An integrated dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control FET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a driver integrated circuit (IC) paddle configured to support a driver IC for controlling each of the control FETs and each of the sync FETs. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control FET and the second sync FET via a second clip, respectively. | 10-03-2013 |
20130256859 | Dual Power Converter Package Using External Driver IC - A dual power converter package is disclosed. The package includes a leadframe having a first control FET paddle configured to support a drain of a first control FET, and a second control FET paddle configured to support a drain of a second control PET. The leadframe further includes a sync FET paddle configured to support a source of a first sync FET and a source of a second sync FET, and a first plurality of contacts configured to receive control signals for each of the control PETS and each of the sync FETs from a driver integrated circuit (IC) external to the leadframe. The leadframe may additionally include first and second switched nodes, configured for electrical connection to the first control FET and the first sync FET via a first clip, and to the second control PET and the second sync PET via a second clip, respectively. | 10-03-2013 |
20130256905 | Monolithic Power Converter Package with Through Substrate Vias - According to an exemplary embodiment, a monolithic power converter package includes a monolithic die over a substrate, the monolithic die integrating a driver integrated circuit (IC) with a control power transistor and a sync power transistor connected in a half-bridge. The high side power input and a power output of the half-bridge each are disposed on a top surface of the monolithic die. The high side power input is electrically coupled to the substrate through a high side power connection. The power output is electrically coupled to the substrate through a power output connection. The low side power input of the half-bridge comprises a plurality of through substrate vias that extend through the monolithic die to electrically connect a low side power pad to the monolithic die. | 10-03-2013 |
20130257524 | Monolithic Power Converter Package - According to an exemplary embodiment, a monolithic power converter package includes a monolithic die over a substrate, the monolithic die integrating a driver integrated circuit (IC) with a control power transistor and a sync power transistor connected in a half-bridge. A high side power input, a low side power input, and a power output of the half-bridge are each disposed on a top surface of the monolithic die. The high side power input is electrically and mechanically coupled to the substrate by a high side power strip. Also, the low side power input is electrically and mechanically coupled to the substrate by a low side power strip. Furthermore, the power output is electrically and mechanically coupled to the substrate by a power output strip. | 10-03-2013 |
20130337611 | Thermally Enhanced Semiconductor Package with Conductive Clip - One exemplary disclosed embodiment comprises a semiconductor package including an inside pad, a transistor, and a conductive clip coupled to the inside pad and a terminal of the transistor. A top surface of the conductive clip is substantially exposed at the top of the package, and a side surface of the conductive clip is exposed at a side of the package. By supporting the semiconductor package on an outside pad during the fabrication process and by removing the outside pad during singulation, the conductive clip may be kept substantially parallel and in alignment with the package substrate while optimizing the package form factor compared to conventional packages. The exposed top surface of the conductive clip may be further attached to a heat sink for enhanced thermal dissipation. | 12-19-2013 |
20140001614 | Thermally Enhanced Semiconductor Package | 01-02-2014 |
20140110776 | Semiconductor Package Including Conductive Carrier Coupled Power Switches - In one implementation, a semiconductor package including conductive carrier coupled power switches includes a first vertical FET in a first active die having a first source and a first gate on a source side of the first active die and a first drain on a drain side of the first active die. The semiconductor package also includes a second vertical FET in a second active die having a second source and a second gate on a source side of the second active die and a second drain on a drain side of the second active die. The semiconductor package includes a conductive carrier attached to the source side of the first active die and to the drain side of the second active die, the conductive carrier coupling the first source to the second drain. | 04-24-2014 |
20140110788 | Power Converter Package Including Top-Drain Configured Power FET - In one implementation, a semiconductor package includes a top-drain vertical FET in a first active die, a source of the top-drain vertical FET situated on a source side of the first active die and a drain and a gate of the top-drain vertical FET situated on a drain side of the first active die. The semiconductor package also includes a bottom-drain vertical FET in a second active die, a source and a gate of the bottom-drain vertical FET situated on a source side of the second active die and a drain of the bottom-drain vertical FET situated on a drain side of the second active die. The semiconductor package includes a conductive carrier attached to the source side of the first active die and to the drain side of the second active die, the conductive carrier coupling the source of the top-drain vertical FET to the drain of the bottom-drain vertical FET. | 04-24-2014 |
20140110796 | Semiconductor Package with Conductive Carrier Integrated Heat Spreader - In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage having a control drain attached to the die side of the control conductive carrier. The control conductive carrier is configured to sink heat produced by the control FET into the mounting surface. The semiconductor package includes a sync conductive carrier having another die side and another opposite I/O side connecting the semiconductor package to the mounting surface, and a sync FET of the power converter switching stage having a sync source attached to the die side of the sync conductive carrier. | 04-24-2014 |
20140110863 | Power Converter Package Including Vertically Stacked Driver IC - In one implementation, a semiconductor package includes a control conductive carrier having a die side and an opposite input/output (I/O) side connecting the semiconductor package to a mounting surface. The semiconductor package also includes a control FET of a power converter switching stage attached to the die side of the control conductive carrier, and a driver integrated circuit (IC) for driving the control FET. The driver IC is situated above the control FET and is electrically coupled to the control FET by at least one conductive buildup layer formed over the control conductive carrier. | 04-24-2014 |
20140175630 | Semiconductor Package with Multiple Conductive Clips - One exemplary disclosed embodiment comprises a high power semiconductor package configured as a buck converter having a control transistor and a sync transistor disposed on a common leadframe pad, a driver integrated circuit (IC) for driving the control and sync transistors, and conductive clips electrically coupling the top surfaces of the transistors to substrate pads such as leadframe pads. In this manner, the leadframe and the conductive clips provide efficient grounding or current conduction by direct mechanical connection and large surface area conduction, thereby enabling a package with significantly reduced electrical resistance, form factor, complexity, and cost when compared to conventional packaging methods using wirebonds for transistor interconnections. | 06-26-2014 |
20140191337 | Stacked Half-Bridge Package - According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to an output terminal, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the output terminal, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. A current carrying layer is situated on the sync drain; the control transistor and the sync transistor being stacked on one another, where the current carrying layer provides a high current connection between the sync drain and the control source. | 07-10-2014 |
20140203419 | Half-Bridge Package with a Conductive Clip - According to an exemplary embodiment, a stacked half-bridge package includes a control transistor having a control drain for connection to a high voltage input, a control source coupled to a common conductive clip, and a control gate for being driven by a driver IC. The stacked half-bridge package also includes a sync transistor having a sync drain for connection to the common conductive clip, a sync source coupled to a low voltage input, and a sync gate for being driven by the driver IC. The control and sync transistors are stacked on opposite sides of the common conductive clip with the common conductive clip electrically and mechanically coupling the control source with the sync drain, where the common conductive clip has a conductive leg for providing electrical and mechanical connection to an output terminal leadframe. | 07-24-2014 |
Hanbum Cho, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20110225096 | Method And System For Providing Diagnostic Feedback Based On Diagnostic Data - A system and method for providing diagnostic feedback based on vehicle diagnostic data is disclosed. According to one embodiment, vehicle data is received from a communication device connected to a motor vehicle. The vehicle data comprises a vehicle identifier and diagnostic data. The diagnostic data is analyzed based on the vehicle identifier. A list of diagnoses is generated based on the analysis. Diagnostic feedback corresponding to the list of diagnoses is transmitted to the communication device. According to one embodiment, the diagnostic feedback is service pricing comprising a list of parts and estimated labor corresponding to the list of diagnoses. | 09-15-2011 |
Hanna Cho, San Francisco, CA US
Patent application number | Description | Published |
---|---|---|
20120122860 | SOLID FORMS OF SULFONAMIDES AND AMINO ACIDS - Solid forms of phenyl sulfonamide compounds of formula (I) active on protein kinases, including Raf protein kinases, are described, as well as methods of using such solid forms to treat diseases and conditions associated with activity of protein kinases, e.g. Raf protein kinases, including pain, polycystic kidney disease, melanoma and colorectal cancer. | 05-17-2012 |
20120165329 | COMPOUNDS AND METHODS FOR KINASE MODULATION, AND INDICATIONS THEREFOR - Compounds and salts thereof, formulations thereof, conjugates thereof, derivatives thereof, forms thereof and uses thereof are described. In certain aspects and embodiments, the described compounds or salts thereof, formulations thereof, conjugates thereof, derivatives thereof, forms thereof are active on at least one of Fms protein kinase or Kit protein kinase. Also described are methods of use thereof to treat diseases and conditions, including diseases and conditions associated with activity of Fms protein kinases and/or Kit protein kinases, including rheumatoid arthritis, osteoarthritis, osteoporosis, peri-prosthetic osteolysis, systemic sclerosis, demyelinating disorders, multiple sclerosis, Charcot Marie Tooth syndrome, amyotrophic lateral sclerosis, Alzheimer's disease, Parkinson's disease, ulcerative colitis, Crohn's disease, immune thrombocytopenic purpura, myelopreparation for autologous transplantation, transplant rejection, nephritis, nephropathy, type I diabetes, acute pain, inflammatory pain, neuropathic pain, breast cancer, prostate cancer, pancreatic cancer, lung cancer, ovarian cancer, gliomas, glioblastomas, neurofibromatosis, osteolytic bone metastases, and giant cell tumors. | 06-28-2012 |
20120245174 | COMPOUNDS AND METHODS FOR KINASE MODULATION, AND INDICATIONS THEREFOR - Compounds and salts thereof, formulations thereof, conjugates thereof, derivatives thereof, forms thereof and uses thereof are described. In certain aspects and embodiments, the described compounds or salts thereof, formulations thereof, conjugates thereof, derivatives thereof, and forms thereof are active on each of BRaf and c-Raf-1 protein kinase, and may also be active on either or both of A-Raf and B-Raf V600E protein kinase. Also described are methods of use thereof to treat diseases and conditions, including melanoma, colorectal cancer, thyroid cancer, ovarian cancer, and biliary tract cancer. | 09-27-2012 |
Hansang Cho, Albany, CA US
Patent application number | Description | Published |
---|---|---|
20100105053 | APTAMER BASED SENSORS AND RELATED METHODS AND SYSTEMS - An aptamer based-sensor comprising: a target binding aptamer attaching a Raman probe and a metal coated surface; and related methods and systems | 04-29-2010 |
20100136551 | MICROFLUIDIC PLATFORM AND RELATED METHODS AND SYSTEMS - A microfluidic platform comprising one or more chambers connectable through microfluidic channels, and comprising a substrate presenting aptamer sensors detectable through Raman active molecules, and related methods and systems. | 06-03-2010 |
Hans S. Cho, Oakland, CA US
Patent application number | Description | Published |
---|---|---|
20130043056 | THREE-DIMENSIONAL CROSSBAR ARRAY - A three-dimensional crossbar array may include a metal layer, and an insulator layer disposed adjacent the metal layer. A trench may be formed in the metal layer to create sections in the metal layer, and a portion of the trench may include an insulator. A hole may be formed in the trench and contact a section of the metal layer. The hole may define a via. A contact region between the via and the section of the metal layer may define a crossbar array. | 02-21-2013 |
20150076438 | NON-VOLATILE RESISTIVE MEMORY CELLS - Examples of the present disclosure include non-volatile resistive memory cells and methods of forming the same. An example of a non-volatile resistive memory cell includes a first portion of the non-volatile resistive memory cell formed as a vertically-extending structure on a first electrode, where the first portion comprises at least one memristive material across a width of the vertically-extending structure. The non-volatile resistive memory cell also includes a second portion formed as a vertically-extending memristive material structure on at least one sidewall of the first portion. | 03-19-2015 |
Helen Kim Cho, San Diego, CA US
Patent application number | Description | Published |
---|---|---|
20130078270 | HER-2 PEPTIDES AND VACCINES - The present invention provides (a) isolated immunogenic HER-2 peptides capable of inducing immune responses against human HER-2 receptor; (b) isolated nucleic acid molecules encoding an isolated immunogenic HER-2 peptide; (c) plasmid constructs comprising a nucleic acid molecule encoding an isolated immunogenic HER-2 peptide; (d) vaccine compositions comprising an isolated immunogenic HER-2 peptide (e) vaccine compositions comprising an isolated nucleic acid molecule encoding an isolated immunogenic HER-2 peptide; and (f) methods of treating or preventing cancer, inhibiting abnormal cell proliferation, or eliciting an immune response against HER-2 protein in a mammal using (1) an isolated immunogenic HER-2 peptide, (2) nucleic acid molecule encoding an isolated immunogenic HER-2 peptide, or (3) a composition comprising an isolated immunogenic HER-2 peptide, or composition comprising a nucleic acid molecule encoding an isolated immunogenic HER-2 peptide. | 03-28-2013 |
20130295110 | PROSTATE-ASSOCIATED ANTIGENS AND VACCINE-BASED IMMUNOTHERAPY REGIMENS - The present disclosure provides (a) isolated immunogenic PAA polypeptides; (b) isolated nucleic acid molecules encoding immunogenic PAA polypeptides; (c) vaccine compositions comprising an immunogenic PAA polypeptide or an isolated nucleic acid molecule encoding an immunogenic PAA polypeptide; (d) methods relating to uses of the polypeptides, nucleic acid molecules, and compositions; and (e) vaccine-based immunotherapy regimens which involve co-administration of a vaccine in combination with an immune-suppressive-cell inhibitor and an immune-effector-cell enhancer. | 11-07-2013 |
Hoon Cho, Santa Clara, CA US
Patent application number | Description | Published |
---|---|---|
20120137048 | METHOD AND APPARATUS FOR IMPROVING ENDURANCE OF FLASH MEMORIES - A method and apparatus for improving the endurance of flash memories. In one embodiment of the invention, a high electric field is provided to the control gate of a flash memory module. The high electric field applied to the flash memory module removes trapped charges between a control gate and an active area of the flash memory module. In one embodiment of the invention, the high electric field is applied to the control gate of the flash memory module prior to an erase operation of the flash memory module. By applying a high electric field to the control gate of the flash memory module, embodiments of the invention improve the Program/Erase cycling degradation of the single-level or multi-level cells of the flash memory module. | 05-31-2012 |
Hyungmin Cho, Stanford, CA US
Patent application number | Description | Published |
---|---|---|
20120131389 | CROSS-LAYER SYSTEM ARCHITECTURE DESIGN - Methods and systems for cross-layer forgiveness exploitation include executing one or more applications using a processing platform that includes a first reliable processing core and at least one additional processing core having a lower reliability than the first processing core, modifying application execution according to one or more best-effort techniques to improve performance, and controlling parameters associated with the processing platform and the best-effort layer that control performance and error rate such that performance is maximized in a region of low hardware-software interference. | 05-24-2012 |
Hyun Jin Cho, Cupertino, CA US
Patent application number | Description | Published |
---|---|---|
20110307631 | SYSTEM AND METHOD FOR PROVIDING ASYNCHRONOUS DATA COMMUNICATION IN A NETWORKED ENVIRONMENT - A method and system for providing asynchronous data communication between a plurality of devices in a networked environment is disclosed. A user using a first device views view media content received from a first content provider of a plurality of service providers. At a request of the user, a message including a data link to the media content is generated and asynchronously sent to a second device via a network. The data link contained in the received message on the second device is used to retrieve the media content from a second content provider. Various action commands contained in the message are used to control the operation of the media content on the second device. | 12-15-2011 |
James Cho, Santa Clara, CA US
Patent application number | Description | Published |
---|---|---|
20090175383 | Wireless Communication Using Beam Forming And Diversity - A method and apparatus for wirelessly transmitting real-time data streams is described. To ensure continuous data flow, fast diversity and slow diversity can be used. Fast diversity chooses a receive antenna based on received signal parameters, such as signal strength, during the transmission header and prior to information transfer. Slow diversity stores received signal parameters from previous packets, associates the parameters with a selected antenna, and uses the parameter history to denote a “default” antenna. Additionally, receive and/or transmit beam forming can be used to maintain continuous communication between stations. Beam forming, which combines antenna signals to maximize performance, is possible when at least two transmit/receive signal processing chains are available. | 07-09-2009 |
James Cho, Mountain View, CA US
Patent application number | Description | Published |
---|---|---|
20120069804 | Selecting Frequency Bands For Transmitting Data Packets - A first combination of frequency bands is selected for transmitting a first data packet, and a second, different combination of frequency bands is selected for transmitting a second data packet. A data stream is divided into a first set of data and a second set of data. The first set of data is allocated to the first combination of frequency bands, and the second set of data is allocated to the second combination of frequency bands. | 03-22-2012 |
20120170685 | Wireless Communication Using Beam Forming And Diversity - A method and apparatus for wirelessly transmitting real-time data streams is described. To ensure continuous data flow, fast diversity and slow diversity can be used. Fast diversity chooses a receive antenna based on received signal parameters, such as signal strength, during the transmission header and prior to information transfer. Slow diversity stores received signal parameters from previous packets, associates the parameters with a selected antenna, and uses the parameter history to denote a “default” antenna. Additionally, receive and/or transmit beam forming can be used to maintain continuous communication between stations. Beam forming, which combines antenna signals to maximize performance, is possible when at least two transmit/receive signal processing chains are available. | 07-05-2012 |
20120269170 | Synchronization-Free Station Locator In Wireless Network - A method of providing synchronization-free station locating in a wireless network is provided. In this method, an AP having a known location sends a unicast packet to the station and notes its time of departure TOD(D). The station receives the unicast packet, notes its time of arrival TOA(D), sends an acknowledgement packet to the AP, and notes its time of departure TOD(D_ACK). The AP receives the acknowledgment packet and notes its time of arrival TOA(D_ACK). Notably, a distance between the AP and the station can be accurately determined using a first difference between the TOA(D_ACK) and the TOD(D) and a second difference between the TOD(D_ACK) and the TOA(D). A plurality of such computed distances between a plurality of APs and the station can be used to determine an accurate location of the station. | 10-25-2012 |
Jenn Cho, San Francisco, CA US
Patent application number | Description | Published |
---|---|---|
20100309134 | COMPUTER HAVING INTERLOCKING L-SHAPE COMPONENTS - A computer has a display, keyboard and two main component parts. The components each have an L-shape and are linked together to enable sliding movement in substantially one plane in a first direction. The linkage also enables movement orthogonally with respect to the first direction in another plane, such that the components transition from a closed position of the computer in which the components interfit together to form a first right rectangular prism and in which the display is exposed, to an open position having a second right rectangular prism shape in which the keyboard is exposed adjacent to and in the same plane as the display. | 12-09-2010 |
Jennifer Cho, Redwood City, CA US
Patent application number | Description | Published |
---|---|---|
20100228600 | System and method for sponsorship recognition - A method and apparatus for providing recognition to individuals and corporations (sponsors) that sponsor electronic content and other products and services, including, for example: video games, CDs, DVDs, movie rentals, game rentals, downloadable content, virtual gaming accessories and other merchandise. Sponsors may associate an icon with sponsored content so that users, such as gamers, who may not be viewing the sponsored content, may see the sponsor's icon and a description of the sponsored content when other gamers are using the sponsored content. Thus, the sponsor may receive recognition for their participation in providing the goods and/or services. | 09-09-2010 |
20100250385 | METHOD AND SYSTEM FOR A COMBINATION VOUCHER - A voucher system for redeeming vouchers via a network. The voucher has an associated voucher code that permits access to one or more first items and/or one or more second items. A redemption module accepts a voucher code such that a user, upon validation of the voucher code, selects one or more of the first items and/or selects one or more of the second items. Upon redeeming the voucher, the user receives the selected first items at a designated user account and receives the selected second items at a designated user account. | 09-30-2010 |
20100261520 | SYSTEM AND METHOD FOR WAGERING BADGES - A method for wagering badges. The method includes establishing badges representing an associated event, such as a window of time that the badge was available. A predetermined criteria for the badges are established, such as an activity required for a gamer to obtain a particular badge, and a determination is made that a gamer is entitled to the badge, based on the predetermined criteria. Similarly, other gamers can also obtain badges by meeting the criteria for the badge. Each gamer, is associated with their badges and a wager or trade between gamers can be established whereby the gamers wager or trade chosen badges. Ownership of the wagered badges is then transferred based on the outcome of the wager or trade. | 10-14-2010 |
Jennifer Cho, San Francisco, CA US
Patent application number | Description | Published |
---|---|---|
20100302719 | Mechanical Mechanism for Revealing Keyboard in L-shaped, 2-part system - A computer has two main parts that are of an L-shape which interfit with one another in open and closed positions. | 12-02-2010 |
Jennifer Moonyoung Cho, Redwoody City, CA US
Patent application number | Description | Published |
---|---|---|
20110015976 | METHOD AND SYSTEM FOR A CUSTOMIZED VOUCHER - This invention relates to a voucher system and method for generating and redeeming vouchers. The voucher system includes a generation module adapted to generate a voucher code upon a request of a purchaser and a redemption module adapted to utilize the voucher code such that a recipient, upon validation of the voucher code, accesses the associated items. The voucher code is associated with at least two items selected by the purchaser. The generation module allows the purchaser to select an item to be associated with the voucher code from a wish-list of the purchaser or the recipient. Upon redeeming the voucher, the recipient receives the associated items at a designated user account. | 01-20-2011 |
Jonathan Cho, San Francisco, CA US
Patent application number | Description | Published |
---|---|---|
20100159967 | METHOD AND APPARATUS FOR A FAMILY CENTER - A family center system and method is provided that allows receiving from a registered family member a family message intended for other registered family members and determines, based on a set of rules, to which of other registered family members to push the family message, mode of transport by which to push the family message, and the schedule according to which to push the family message. A technique involving a tile is provided that allows displaying a unified view of information onto a plurality of registered devices, regardless of device platform and/or communications network. The system and method provides a variety of services to registered family members and allows third party application plug-in for offering third party services. The system and method receives a SMS message and stores such message as a family message for subsequent access or family message treatment. | 06-24-2010 |
Joshua Cho, Irvine, CA US
Patent application number | Description | Published |
---|---|---|
20080265854 | Low Drop Out Voltage Regulator Circuit Assembly - An integrated circuit assembly includes a voltage level generator, a level shifter, a bandgap reference generator and a voltage regulator. The voltage level generator generates output voltage level signals in response to a supply voltage. The level shifter receives the output voltage level signals from the voltage level generator and generates first and second sets of control signals. The bandgap reference generator receives a reference voltage input and generates a bandgap reference signal. The voltage regulator receives a supply voltage, the bandgap reference signal the first and second sets of control signals from the level shifter and generates a constant output voltage under varying circuit conditions. | 10-30-2008 |
20090231024 | Low Drop Out Voltage Regulator Circuit Assembly - An integrated circuit assembly includes a voltage level generator, a level shifter, a bandgap reference generator and a voltage regulator. The voltage level generator generates output voltage level signals in response to a supply voltage. The level shifter receives the output voltage level signals from the voltage level generator and generates first and second sets of control signals. The bandgap reference generator receives a reference voltage input and generates a bandgap reference signal. The voltage regulator receives a supply voltage, the bandgap reference signal the first and second sets of control signals from the level shifter and generates a constant output voltage under varying circuit conditions. | 09-17-2009 |
Junghwa Jenn Cho, San Francisco, CA US
Patent application number | Description | Published |
---|---|---|
20080269869 | Intraluminal Stent, Delivery System, and Method of Treating a Vascular Condition - An intraluminal stent, an intraluminal stent delivery system, and a method of treating a vascular condition. The stent includes a stent body with a plurality of struts. The stent body is expandable from a compressed configuration to a deployed configuration. The struts include at least one sliding assembly for locking the stent body in the deployed configuration. The at least one sliding assembly allows sliding of adjacent struts one to another while the stent body is expanding. The system further includes a catheter and the stent disposed on a portion of the catheter. The method includes positioning an intraluminal stent with a catheter within a vessel. The stent includes minimized overlap of adjacent struts while in a compressed configuration. The stent is expanded from the compressed configuration to an deployed configuration where it is locked. Adjacent struts slide relative one to another while the stent is expanding. | 10-30-2008 |
20090306756 | Hybrid Biodegradable/Non-Biodegradable Stent, Delivery System and Method of Treating a Vascular Condition - An intraluminal stent, an intraluminal stent delivery system, and a method of treating a vascular condition. The stent includes a framework composed of a biodegradable material. At least one strut is composed of a non-biodegradable material. The framework is operably attached to the at least one strut. The delivery system includes a catheter and a stent disposed on a portion of the catheter. The stent includes a framework composed of a biodegradable material. The stent further includes at least one strut composed of a non-biodegradable material. The framework is operably attached to the at least one strut. The method includes positioning an intraluminal stent via a catheter within a vessel. The stent includes at least one strut that is composed of a non-biodegradable material and is operably attached to a framework. The framework expands during deployment of the intraluminal stent. The framework is allowed to biodegrade within the vessel. | 12-10-2009 |
20100168833 | Stent With Reduced Profile, Delivery System, and Method of Manufacture - An intraluminal stent, an intraluminal stent delivery system, and a method of manufacturing a stent. The stent ( | 07-01-2010 |
Jung Wook Cho, Cupertino, CA US
Patent application number | Description | Published |
---|---|---|
20110252251 | Hardware Automatic Performance State Transitions in System on Processor Sleep and Wake Events - In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state. | 10-13-2011 |
20120081577 | IMAGE SENSOR DATA FORMATS AND MEMORY ADDRESSING TECHNIQUES FOR IMAGE SIGNAL PROCESSING - Certain embodiments of the present disclosure provide a flexible memory input/output controller that is configured to the storing and reading of multiple types of pixels and pixel memory formats. For instance, the memory I/O controller may support the storing and reading of raw image pixels at various bits of precision, such as 8-bit, 10-bit, 12-bit, 14-bit, and 16-bit. Pixel formats that are unaligned with memory bytes (e.g., not being a multiple of 8-bits) may be stored in a packed manner. The memory I/O controller may also support various formats of RGB pixel sets and YCC pixel sets. | 04-05-2012 |
20120317427 | Hardware Automatic Performance State Transitions in System on Processor Sleep and Wake Events - In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state. | 12-13-2012 |
20130042135 | CONTROLLER CORE TIME BASE SYNCHRONIZATION - A system and method for efficiently synchronizing multiple processing cores on a system-on-a-chip (SOC). A SOC includes an interrupt controller and multiple processing cores. The interrupt controller includes a main time base counter. The SOC includes multiple local time base counters, each coupled to a respective one of the processing cores. Synchronization logic blocks are used to update the local counters. These blocks receive a subset of bits from the interrupt controller. The subset of bits represents a number of least significant bits of the main counter less than a total number of bits for the main counter. The logic blocks update an associated local counter according to changes to the received subset of bits. A difference may exist between values of the main counter in the interrupt controller and the local counter in the processing core. However, this difference may be a constant value. | 02-14-2013 |
20130043917 | HARDWARE CONTROLLED PLL SWITCHING - A system and method for efficiently managing multiple PLLs on a system on a chip (SOC). A SOC includes a hardware phase lock loop (PLL) switching control block coupled to a software interface. The hardware PLL switching (HPS) control block receives PLL switch requests from software. The request identifies a given core clock received by a given processing core of multiple processor cores on the SOC and indicates the identified core clock is not to be provided anymore by a current PLL. The request indicates a given search method including search conditions. The HPS control block searches for a target PLL that satisfies these search conditions. In response to finding the target PLL, the HPS control block changes clock network connections and parameters across the die of the SOC. These changes across the die disconnect the identified core clock from the current PLL and connects the identified core clock to the target PLL. | 02-21-2013 |
20130076381 | Threshold-Based Temperature-Dependent Power/Thermal Management with Temperature Sensor Calibration - A method and apparatus for temperature sensor calibration is disclosed. In one embodiment, an integrated circuit (IC) is tested at a first known temperature corresponding to a first temperature threshold. During the test, a first temperature reading is obtained from a temperature sensor. A first offset is calculated by determining the difference between the first known temperature and the first temperature reading. The first offset is recorded in a storage unit for later use during operation of the IC. During operation, the first offset may be added to temperature readings obtained from a temperature sensing unit to produce an adjusted temperature value. The adjusted temperature value may be compared to one or more temperature thresholds. Based on the comparisons, a power management unit may perform power control actions. | 03-28-2013 |
20130111191 | PROCESSOR INSTRUCTION ISSUE THROTTLING | 05-02-2013 |
20130232364 | Hardware Automatic Performance State Transitions in System on Processor Sleep and Wake Events - In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state. | 09-05-2013 |
20140122908 | Hardware Automatic Performance State Transitions in System on Processor Sleep and Wake Events - In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state. | 05-01-2014 |
20140380066 | CONTROL SCHEME TO TEMPORARILY RAISE SUPPLY VOLTAGE IN RESPONSE TO SUDDEN CHANGE IN CURRENT DEMAND - A system for managing changes in current demand, including one or more processors, a memory coupled to at least one of the processors, a clock generation circuit coupled to the memory and configured to output a clock, one or more functional blocks, a power supply, configured to output a plurality of voltage levels, and a power management unit. The power management unit may be configured to set the power supply output to a first voltage level and then detect indications of an impending change in current demand within the SoC. If an indication of an impending change in current demand is detected, then the power management unit may be configured to adjust the power supply output to a second voltage level. After determining the impending change in current demand has occurred, the power management unit may be configured to adjust the power supply output back to the first voltage level. | 12-25-2014 |
Kiho Cho, Davis, CA US
Patent application number | Description | Published |
---|---|---|
20110280466 | SYSTEMS AND METHODS FOR GENETIC IMAGING - Sequence data, e.g., genetic sequence data such as nucleic acid or amino acid sequences, can be represented in Genetic Images, as defined herein, that provide a compact, portable image that can be analyzed electronically (e.g., by computer) or optically, e.g., visually or by optical scanning devices. New methods and systems are described by which sequence data is first converted into a numeric data set, which is, in turn, encoded to form a Genetic Image. The Genetic Image can be traced backwards to determine the original sequence data. | 11-17-2011 |
20120040938 | GLUCOCORTICOID RECEPTOR ALLELES AND USES THEREOF - Provided here in are, inter alia, methods of determining whether a patient is resistant or sensitive to glucocorticoid therapy. | 02-16-2012 |
20120149668 | GLUCOCORTICOID RECEPTOR ALLELES AND USES THEREOF - Provided here in are, inter alia, methods of determining whether a patient is resistant or sensitive to glucocorticoid therapy. | 06-14-2012 |
20140213474 | GLUCOCORTICOID RECEPTOR ALLELES AND USES THEREOF - Provided here in are, inter alia, methods of determining whether a patient is resistant or sensitive to glucocorticoid therapy. | 07-31-2014 |
Kwang-Bo Cho, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20120188422 | IMAGING SYSTEM WITH AN ARRAY OF IMAGE SENSORS - An integrated circuit may have rows and columns of imaging pixel arrays. Row driver circuitry and column readout circuitry may be shared between the imaging pixel arrays. Control circuit blocks may bypass inactive pixel arrays and may shift signals between different signal paths on the integrated circuit. The control circuit blocks may include synchronizing circuitry for deskewing control signals and buffer circuitry for regenerating weak signals as they are distributed across the integrated circuit. An array of lenses may be associated with the integrated circuit. The spacing between imaging pixel arrays may differ at different parts of the integrated circuit. Images from multiple image sensor pixel arrays may be combined to form a single digital image. Image sensors may be provided with unique lenses, different color responses, different image pixels, different image pixel patterns, and other differences. Reference pixels may be interposed in the gaps between image sensor arrays. | 07-26-2012 |
Kwang-Bo (austin) Cho, Valencia, CA US
Patent application number | Description | Published |
---|---|---|
20090073297 | TWISTED INPUT PAIR OF FIRST GAIN STAGE FOR HIGH SIGNAL INTEGRITY IN CMOS IMAGE SENSOR - Methods for forming conductors and global bus configurations for reducing an interference signal from electromagnetic interference (EMI) source are provided. First and second conductor lines are formed on an integrated circuit in a twisted pair configuration. A differential amplifier is formed on the integrated circuit and coupled to each of the first and second conductor lines. The first and second signals are respectively transmitted through the first and second conductor lines and are modified by the interference signal. The modified first and second signals are differentially amplified by the differential amplifier so that the interference signal is substantially cancelled. | 03-19-2009 |
Kwang Han Cho, Northridge, CA US
Patent application number | Description | Published |
---|---|---|
20090062026 | Ball returning tent net - A ball returning tent net includes a frame that is supported on the ground on three or four contact points, and a ball-catch enclosure that is supported by the frame. The ball-catch enclosure includes an aperture that is adapted to pass a ball through, and a rear wall that is adapted to catch the ball and a bottom net. The frame includes a front frame member that supports the aperture and a rear frame member that supports the rear wall. The bottom net is inclined downward toward the front frame member. The ball-catch enclosure further includes an anti-sagging device that prevents sagging of the bottom net. | 03-05-2009 |
20090176590 | PUTTING MAT - An aspect of the invention provides a putting mat including a mat portion, a ball returning net portion, and a pair of bumps. The mat portion is configured for a ball to travel along. The ball returning net portion includes an entrance, a confining net portion, and a slope portion configured to guide the ball in the confining net portion toward and beyond the entrance. The pair of bumps along the two side portions of the mat portion are configured to limit the ball on the central path portion of the mat portion. The mat portion is tilted downward from the first end portion to the second end portion such that the ball is fallen off the entrance of the ball returning net and rolls toward the second end portion of the mat portion. | 07-09-2009 |
20090197707 | SCREEN NET - A screen net includes a front member with an opening, a base member, a catch member and a wall member. The base member is placed on the ground. The catch member is adapted to catch a ball that passes through the opening of the front member. The wall member is positioned above the opening of the front member. The wall member comprises a wall fabric member and a wall pole member. The wall fabric member comprises a sleeve through which the wall pole member passes. The wall fabric member is attached to the front member. The ends of the wall pole member are supported by the base member. The screen net further comprises straps that connect the front member and the base member. The straps are under tension provided by the elastic pole segments. | 08-06-2009 |
20110070979 | HALF MOON TYPE NET - Disclosed is a half moon type net for catching balls or flexibly stopping the flight of balls, comprising a half-moon-shaped or arch-shaped loop and a fabric retainer to better support the net structure, maintain a bigger net in shape, and reduce the chance of missing balls. More specifically, the net comprises: a main member forming a substantially half-moon-shaped closed loop; a base member forming a closed loop, wherein the straight front section of the base member is connected to the straight bottom section of the main member; a fabric retainer comprising two bottom sections formed adjacent to each of the two corners of the main member and an arch section along the top section of the main member so as to maintain the main member in shape; a fabric member covering the loop of the main member to flexibly stop the flight of projectiles; and a supporting member to sustain the main member against the base member while maintaining a substantial angle between the main and base members. | 03-24-2011 |
20120088593 | BALL NET OF BOX TYPE WITH RAISED FRONT TOP - A ball net of box type comprises a front loop, a rear loop, and first and second side loops. The enclosing net portion are for covering a top hole formed by top portions of the loops, two side holes formed by the side loops, and a rear hole formed by the rear loop, so as to enclose the box-type space from four sides. The vertical side straight portions of neighboring loops are hold together by fabric holder portions. The top curved portion of the front loop protrudes above the top straight portions of the other loops, such that a front opening defined by the front loop provides a receiving area larger than the other holes defined by the other loops especially in a upper portion of the receiving area. The front loop has a larger area than the other loops in a lower portion of the receiving area. | 04-12-2012 |
20120088594 | SINGLE LOOP NET WITH PEGS - A single loop net includes a loop member, triangular holders, side straight edge portions, two propping poles, two holding straps, a first opening, a catching net, net deploying straps, and a second opening. The triangular holders are for holding two neighboring straight portions. The side straight edge portions are fixed to one of the side straight portions. Each of the propping poles extends from two side straight portions of the loop member. Each of the holding straps extends from a lower portion of the loop member. The first opening is enclosed and defined by the triangular holders and the side straight edge portions. The catching net covers the first opening and configured to catch balls flying into the first opening from a frontal direction. The second opening is disposed in a bottom one of the side straight edge portions. The second opening is disposed so as to return balls. | 04-12-2012 |
20120149503 | Ball Net with Basket - An aspect of the present invention provides a ball net with a basket. The ball net comprises a target opening portion, a decelerating catcher, and a collecting pocket. The target opening portion is configured for hulling a ball therein. The decelerating catcher is provided inside the target opening for reducing speed of, stopping, and dropping the ball. The collecting pocket is disposed below the decelerating catcher for receiving the ball dropped from the decelerating catcher and keeping inside. The target opening portion comprises a coilable loop and an edge portion extending from the coilable loop and defining a flying-in opening. | 06-14-2012 |
20130045815 | Ball Net with Sack - A ball net is provided, which includes two poles, a top net, a tilting bottom net, a decelerating catcher, and a collecting sack. Each of the two poles are bent and crossed at a zenith point forming four side openings, one of which provides a target opening portion configured for hulling a ball. The tilting bottom net is provided at a low portion of the space surrounded by the zenith point and the four ends of the two poles, and the tilting bottom net is tilted toward a front of the ball net. The decelerating catcher is provided inside the target opening for reducing speed of, stopping, and dropping the ball. The collecting sack is disposed at a front portion of the tilting bottom net for receiving the ball rolling down on the tilting bottom net and keeping inside. | 02-21-2013 |
20150087445 | Ball Stopping Net - A ball stopping net is provided, which includes a loop, propping poles, fold-butting poles, hexagonal-shaped holding fabrics, and a net. Each of the two propping poles comprises an upper end and a lower end, and the upper end is curved and engaged rotatably with a mid point of a corresponding side portion of the loop. Each of the two fold-butting poles comprises a first arm and a second arm engaging each other with a hinge, and the first arm is connected to a lower point of the loop rotatably and the second arm is connected to a lower point of a corresponding propping pole rotatably. Each of the two hexagonal-shaped holding fabrics has three queuing sides and three plain sides alternatively, and are queued through the queuing side of the hexagonal-shaped holding fabric. | 03-26-2015 |
Kwang Myung Cho, Los Angeles, CA US
Patent application number | Description | Published |
---|---|---|
20130029386 | COMPOSITIONS AND METHODS FOR THE PRODUCTION OF L-HOMOALANINE - Healthcare costs are a significant worldwide, with many patients being denied medications because of their high prices. One approach to addressing this problem involves the biosynthesis of chiral drug intermediates, an environmentally friendly solution that can be used to generate pharmaceuticals at much lower costs than conventional techniques. In this context, embodiments of the invention comprise methods and materials designed to allow microorganisms to biosynthesize the nonnatural amino acid L-homoalanine. As is known in the art, L-homoalanine is a chiral precursor of a variety of pharmaceutically valuable compounds including the anticonvulsant medications levetiracetam (sold under the trade name Keppra®) and brivaracetam, as well as ethambutol, a bacteriostatic antimycobacterial drug used to treat tuberculosis. Consequently, embodiments of the invention can be used in low cost, environmentally friendly processes to generate these and other valuable compounds. | 01-31-2013 |
20140322774 | MICROBIAL PRODUCTION OF N-BUTYRALDEHYDE - Microorganisms and methods of producing n-butyraldehyde with enhanced yields are presented in which a microorganism is engineered to enhance the conversion of a carbon source into n-butyraldehyde. The n-butyraldehyde is recovered by way of a gas stripping process that occurs during the conversion process, providing significantly greater product yield than post-fermentation recovery of n-butyraldehyde alone. | 10-30-2014 |
Kyu Hwang Cho, Fairfield, CA US
Patent application number | Description | Published |
---|---|---|
20080208680 | DriveOn Pay(TM) as WiMAX-compatible Menu-Driven Dashtop Mobile Payment Platform - DriveOn Pay™ is a location-based Privacy-friendly dashtop mobile payment platform (DMPP), based on mobile WiMAX IEEE 802-16e-2005. It is an all-in-one solution geared to integrate all other dashtop gadgets in view of the growing necessity of the real-time bridge syncing cyberworld and real world, which is central to mobile broadband technology. The VIN-based Menu-Driven Fail-safe 5-mile-range DMPP envisions a BS and a Touchscreen On-Vehicle CPE named VIMO™, powered by the vehicle battery. It works as an Unmanned Booth-free Toll-Collection Maximizer at any vehicle speed; Transportation Hub Security Enforcer for non-linear surveillance of passengers plus non-passengers, both indoors and outdoors; ‘JIT e-Commerce on the Go’ (JITeCGO) Creator; Ticket-free Biometrics-free Remote Check-In & Admission Optimizer for ballparks, expos, parking garages, and transportation hubs. After all, it is to provide an optimal solution to metropolitan traffic surges, wherever they may happen, utilizing the Disposable Ephemeral Digital ID (DEDID) and the vehicle-to-vehicle mobile P2P. | 08-28-2008 |
20110122244 | Real-Time Remote-Viewing Digital Compass - Vehicle-mounted video cameras, if and when wirelessly connected via a hybrid transceiver of satellite and terrestrial links and either through a randomly-formed vehicle-to-vehicle network, or via mobile web links, may enable motorists behind the wheel to remotely see either on a navigator screen, or on a screen of mobile equipment, inclusive of handsets and tablet PCs, any real-time video images of traffic and/or street scenes, far beyond physical limits of human eyesight. In pursuing the said peer-to-peer advantages, the real-time street views targeted in any directions can be picked at the discretion of motorists, by transmitting the location-based inquiry to the targeted on-vehicle cameras, by tapping on an in-vehicle touchscreen or a mobile device screen and also by activating voice commands, if necessary. The viewable range and directions are only affected or limited by the signal strength based on the density of moving vehicles in between and the availability of interconnected roadside stationary surveillance fixtures as well as the availability of target vehicles equipped with video cameras. | 05-26-2011 |
20140327775 | Mirrorless Driving of Automotive Vehicle Using Digital Image Sensors and Touchscreen - Automotive mirrors may be replaced by a multi-lens-equipped touchscreen to enable mirrorless driving that may help open a new avenue for identifying energy-saving and environment-friendly solutions to enhance driving safety by harnessing vehicle traffic to incentivize a mixed reality. The mirrorless driving may eventually encompass not just vehicular black boxes and rearview backup cameras but also ADAS (Advanced Driver Assistance System). | 11-06-2014 |
Kyunghee Cho, Ventura, CA US
Patent application number | Description | Published |
---|---|---|
20110286912 | CATHODE ACTIVE MATERIAL (HIGHER OXIDES OF SILVER) - The present invention provides novel cathodes having a reduced resistivity and electrochemical cells using these cathodes. Furthermore, this invention also presents methods of manufacturing novel electrochemical cells and novel cathodes. | 11-24-2011 |
Myeong-Je Cho, Alameda, CA US
Patent application number | Description | Published |
---|---|---|
20100192253 | METHODS FOR IMPROVING MONOCOT TRANSFORMATION - The invention provides improved plant transformation methods. In particular the method provides increased transformation frequency, especially in recalcitrant plants. The method includes various transformation protocols for monocots, such as maize and sorghum, using a combination of media and light conditions to achieve increased efficiency of monocot transformation and increased callus initiation frequencies. | 07-29-2010 |
20110165561 | DIRECT AND CONTINUOUS ROOT ALONE OR ROOT/SHOOT PRODUCTION FROM TRANSGENIC EVENTS DERIVED FROM GREEN REGENERATIVE TISSUES AND ITS APPLICATIONS - The present invention provides assays and methods for efficiently testing a polynucleotide of interest for a phenotype in a root. In some embodiments, the assays and methods include regenerating green tissue that is transgenic for at least one polynucleotide of interest into one or more transgenic plantlets that have at least one transgenic root. Further provided are methods of making a root assay by contacting green tissue with a first rooting medium to produce a plantlet and a plurality of roots. Additionally provided are methods of assaying for insecticidal activity on a live root. Accordingly provided herein is a substantially contamination-free, root bioassay. Further provided are methods of identifying a promoter having activity in a root. | 07-07-2011 |
20140173775 | METHODS AND COMPOSITIONS FOR PRODUCING AND SELECTING TRANSGENIC PLANTS - Compositions and methods are provided for the production and selection of transgenic plants and plant parts, for increasing the transformation frequency of a plant or plant part, and for regulating the expression of a transgene, such as a herbicide tolerance polynucleotide. The methods and compositions allow for the delay in the expression of herbicide tolerance polynucleotides until a point in development during which herbicide selection is more efficient. Compositions comprise polynucleotide constructs comprising an excision cassette that separates a transgene, such as a herbicide tolerance polynucleotide, from its promoter and host cells comprising the same. The excision cassette comprises a polynucleotide encoding a site-specific recombinase operably linked to an inducible promoter and expression of the recombinase leads to excision of the excision cassette and expression of the transgene. | 06-19-2014 |
20140173781 | METHODS AND COMPOSITIONS FOR PRODUCING AND SELECTING TRANSGENIC WHEAT PLANTS - Compositions and methods are provided for the production and selection of transgenic plants and plant parts, for increasing the transformation frequency of a plant or plant part, and for regulating the expression of a transgene, such as a herbicide tolerance polynucleotide. The methods and compositions allow for the delay in the expression of herbicide tolerance polynucleotides until a point in development during which herbicide selection is more efficient. Compositions comprise polynucleotide constructs comprising an excision cassette that separates a transgene, such as a herbicide tolerance polynucleotide, from its promoter and host cells comprising the same. The excision cassette comprises a polynucleotide encoding a site-specific recombinase operably linked to an inducible promoter and expression of the recombinase leads to excision of the excision cassette and expression of the transgene. | 06-19-2014 |
Myeong-Je Cho, Santa Clara, CA US
Patent application number | Description | Published |
---|---|---|
20130055472 | Methods for tissue culture and transformation of sugarcane - Compositions and methods for the efficient transformation and regeneration of monocot plants are provided. The methods of transformation involve infection with | 02-28-2013 |
20150037807 | Direct and Continuous Root Alone or Root/Shoot Production from Transgenic Events Derived from Green Regenerative Tissues and Its Applications - The present invention provides assays and methods for efficiently testing a polynucleotide of interest for a phenotype in a root. In some embodiments, the assays and methods include regenerating green tissue that is transgenic for at least one polynucleotide of interest into one or more transgenic plantlets that have at least one transgenic root. Further provided are methods of making a root assay by contacting green tissue with a first rooting medium to produce a plantlet and a plurality of roots. Additionally provided are methods of assaying for insecticidal activity on a live root. Accordingly provided herein is a substantially contamination-free, root bioassay. Further provided are methods of identifying a promoter having activity in a root. | 02-05-2015 |
Myoeng-Je Cho, Alameda, CA US
Patent application number | Description | Published |
---|---|---|
20110160087 | METHOD FOR INCREASING EFFICIENCY OF GERMPLASM SCREENING IN PLANT TRANSFORMATION - A method for increasing efficiency of germplasm screening for transformability may include providing a plurality of lines of plant target tissue to be transformed, characterizing each of the lines to provide characterization data, the characterization data comprises DNA or nucleic acid delivery technique response data and tissue culture response data, eliminating one or more of the plurality of lines based on the characterization data without performing transformation of the plurality of lines, such that a subset of the plurality of lines remains, and performing transformation experiments on the subset of the plurality of lines. The method may also include selecting a DNA or nucleic acid delivery technique protocol and a tissue culture protocol prior to the characterization. | 06-30-2011 |
20130145500 | METHOD FOR INCREASING EFFICIENCY OF GERMPLASM SCREENING IN PLANT TRANSFORMATION - A method for increasing efficiency of germplasm screening for transformability may include providing a plurality of lines of plant target tissue to be transformed, characterizing each of the lines to provide characterization data, the characterization data comprises DNA or nucleic acid delivery technique response data and tissue culture response data, eliminating one or more of the plurality of lines based on the characterization data without performing transformation of the plurality of lines, such that a subset of the plurality of lines remains, and performing transformation experiments on the subset of the plurality of lines. The method may also include selecting a DNA or nucleic acid delivery technique protocol and a tissue culture protocol prior to the characterization. | 06-06-2013 |
20140007300 | METHOD FOR INCREASING EFFICIENCY OF GERMPLASM SCREENING IN PLANT TRANSFORMATION | 01-02-2014 |
Myung-Sam Cho, Pinole, CA US
Patent application number | Description | Published |
---|---|---|
20090036358 | Methods of preparing pharmaceutical compositions for treatment of factor Vlll associated disorders and methods of use - The invention concerns glycosylated proteins having human factor VIII activity. In a preferred embodiment, the protein is glycosylated with oligosaccharides that include an alpha-(2,6)-linked sialic acid and a bisecting GlcNAc linked to a core beta-mannose. | 02-05-2009 |
20110144025 | Methods of Reducing Hemorrhage Due to Surgical Procedure - The invention concerns glycosylated proteins having human factor VIII activity. In a preferred embodiment, the protein is glycosylated with oligosaccharides that include an alpha-(2,6)-linked sialic acid and a bisecting GlcNAc linked to a core beta-mannose. | 06-16-2011 |
20130143818 | Factor VIII Glycoforms - The invention concerns glycosylated proteins having human factor VIII activity. In a preferred embodiment, the protein is glycosylated with oligosaccharides that include an alpha-(2,6)-linked sialic acid and a bisecting GlcNAc linked to a core beta-mannose. | 06-06-2013 |
20130267468 | FACTOR VIII GLYCOFORMS - The invention concerns glycosylated proteins having human factor VIII activity. In a preferred embodiment, the protein is glycosylated with oligosaccharides that include an alpha-(2,6)-linked sialic acid and a bisecting GlcNAc linked to a core beta-mannose. | 10-10-2013 |
Paula Marie Cho, Los Altos, CA US
Patent application number | Description | Published |
---|---|---|
20080301005 | Collective gift system - An Internet business model comprises a website that allows an Organizer to log-in and initiate a collective gift from many Contributors that are then presented to the Recipient in the form of a Gift Card. Each contributor provides credit card information and an authorization only is obtained. The actual charge is put through only after the gift is fully subscribed and the collection period has ended. Then the gift card is funded and issued. Fees for the collective gift service may be paid in full by the Organizer, a Sponsor, partitioned amongst the Contributors, or covered as an advertizing or merchandizing expense by the gift card issuer. | 12-04-2008 |
Peter Cho, San Francisco, CA US
Patent application number | Description | Published |
---|---|---|
20120102395 | METHODS FOR SEQUENCING ELECTRONIC MEDIA CONTENT - A method for use with an electronic reading device comprising automatically fetching electronic media content and automatically and dynamically sequencing portions of the electronic media content for display on an electronic reading device. Optionally, the electronic media content can be automatically and dynamically divided into the portions that are then sequenced. Optionally, the electronic media content can be re-sequenced to reflect user preferences and needs. Various methods for recognizing and altering the display of the electronic reading device quickly and efficiently are disclosed. | 04-26-2012 |
Pyong Yun Cho, Fremont, CA US
Patent application number | Description | Published |
---|---|---|
20120061764 | MODIFIED DESIGN RULES TO IMPROVE DEVICE PERFORMANCE - The layouts, device structures, and methods described above utilize dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures to the dummy device. Such extension of diffusion regions resolves or reduces LOD and edge effect issues. In addition, treating the gate structure of a dummy device next to an edge device also allows only one dummy structure to be added next to the dummy device and saves the real estate on the semiconductor chip. The dummy devices are deactivated and their performance is not important. Therefore, utilizing dummy devices to extend the diffusion regions of edge structures and/or non-allowed structures according to design rules allows the resolution or reduction or LOD and edge effect issues without the penalty of yield reduction or increase in layout areas. | 03-15-2012 |
20130311964 | MODIFIED DESIGN RULES TO IMPROVE DEVICE PERFORMANCE - A method of designing a layout of devices includes designing a layout of gate structures and diffusion regions of a plurality of devices. The method further includes identifying an edge device of the plurality of devices. The method further includes adding a dummy device next to the edge device and a dummy gate structure next to the dummy device, wherein the dummy device shares a diffusion region with the edge device, and wherein a gate structure of the dummy device is considered to be one of two dummy gate structures added next to the edge device. | 11-21-2013 |
Richard Cho, Sunnyvale, CA US
Patent application number | Description | Published |
---|---|---|
20120252543 | PHONE AND TABLET STAND - The present invention is a phone and tablet stand that includes a rotatable mounting head that attaches a tablet to the phone and tablet stand, attachment magnets that are evenly disposed on a rotatable mounting head to magnetically attach a tablet to the phone and tablet stand and an adjustable stand that includes a stem and a pair of adjustment knobs. The phone and tablet stand also includes a base that provides stability to the phone and tablet stand and a gel attachment interface that is in direct contact with a contact surface where the phone and tablet stand is removably secured. The phone and tablet stand can also include a protective casing that is placed around the back of a tablet and is magnetically attached to the phone and tablet stand and includes a metal disc disposed and centered on the front facing of the protective casing. | 10-04-2012 |
Sang J. Cho, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20120009847 | CLOSED-LOOP CONTROL OF CMP SLURRY FLOW - Embodiments of the present invention generally relate to methods for chemical mechanical polishing a substrate. The methods generally include measuring the thickness of a polishing pad having grooves or other slurry transport features on a polishing surface. Once the depth of the grooves on the polishing surface is determined, a flow rate of a polishing slurry is adjusted in response to the determined groove depth. A predetermined number of substrates are polished on the polishing surface. The method can then optionally be repeated. | 01-12-2012 |
20130122783 | PAD CONDITIONING FORCE MODELING TO ACHIEVE CONSTANT REMOVAL RATE - A method and apparatus for conditioning a polishing pad in a CMP system is provided. In one embodiment, a method for conditioning a polishing pad includes applying a down force to the conditioning disk that urges the conditioning disk against the polishing pad, measuring a torque required to sweep the conditioning disk across the polishing pad, determining a change in down force by comparing the measured torque to a model force profile (MFP), and adjusting the down force that the conditioning disk applies against the polishing pad in response to the determined change. | 05-16-2013 |
Sangjun Cho, Pleasanton, CA US
Patent application number | Description | Published |
---|---|---|
20080293249 | In-situ photoresist strip during plasma etching of active hard mask - A method for etching features in a silicon layer is provided. A hard mask layer is formed over the silicon layer. A photoresist layer is formed over the hard mask layer. The hard mask layer is opened. The photoresist layer is stripped by providing a stripping gas; forming a plasma with the stripping gas by providing a high frequency RF power and a low frequency RF power, wherein the low frequency RF power has a power less than 50 watts; and stopping the stripping gas when the photoresist layer is stripped. The opening the hard mask layer and the stripping the photoresist layer are performed in a same chamber. | 11-27-2008 |
20080314733 | Methods of and apparatus for reducing amounts of particles on a wafer during wafer de-chucking - Particles are trapped away from a wafer transport zone in a chamber. A first electrode is on one side of the zone. A second electrode is on an opposite side of the zone. A power supply connected across the electrodes establishes an electrostatic field between the electrodes. The field traps particles at the electrodes, away from the zone. For transporting the wafer from the chamber, the second electrode mounts the wafer for processing, and the first electrode is opposite to the second electrode defining a process space. The zone is in the space with a separate part of the space separating the zone from each electrode. Particles are urged away from the wafer by simultaneously terminating plasma processing of the wafer, connecting the second electrode to ground, applying a positive DC potential to the first electrode, and de-chucking the wafer from the second electrode into the zone. | 12-25-2008 |
20130001754 | IN-SITU PHOTORESIST STRIP DURING PLASMA ETCHING OF ACTIVE HARD MASK - A method for etching features in a silicon layer is provided. A hard mask layer is formed over the silicon layer. A photoresist layer is formed over the hard mask layer. The hard mask layer is opened. The photoresist layer is stripped by providing a stripping gas; forming a plasma with the stripping gas by providing a high frequency RF power and a low frequency RF power, wherein the low frequency RF power has a power less than 50 watts; and stopping the stripping gas when the photoresist layer is stripped. The opening the hard mask layer and the stripping the photoresist layer are performed in a same chamber. | 01-03-2013 |
Seon-Mee Cho, Santa Clara, CA US
Patent application number | Description | Published |
---|---|---|
20080286982 | PLASMA IMMERSION ION IMPLANTATION WITH HIGHLY UNIFORM CHAMBER SEASONING PROCESS FOR A TOROIDAL SOURCE REACTOR - A method is provided for performing plasma immersion ion implantation with a highly uniform seasoning film on the interior of a reactor chamber having a ceiling and a cylindrical side wall and a wafer support pedestal facing the ceiling. The method includes providing a gas distribution ring with plural gas injection orifices on a periphery of a wafer support pedestal, the orifices facing radially outwardly from the wafer support pedestal. Silicon-containing gas is introduced through the gas distribution orifices of the ring to establish a radially outward flow pattern of the silicon-containing gas. The reactor includes pairs of conduit ports in the ceiling adjacent the side wall at opposing sides thereof and respective external conduits generally spanning the diameter of the chamber and coupled to respective pairs of the ports. The method further includes injecting oxygen gas through the conduit ports into the chamber to establish an axially downward flow pattern of oxygen gas in the chamber. RF power is coupled into the interior of each of the conduits to generate a toroidal plasma current of Si | 11-20-2008 |
20090195777 | DOSIMETRY USING OPTICAL EMISSION SPECTROSCOPY/RESIDUAL GAS ANALYZER IN CONJUNCTION WITH ION CURRENT - The present invention generally provides methods and apparatus for controlling ion dosage in real time during plasma processes. In one embodiment, ion dosages may be controlled using in-situ measurement of the plasma from a mass distribution sensor combined with in-situ measurement from an RF probe. | 08-06-2009 |
20090197401 | Plasma immersion ion implantation method using a pure or nearly pure silicon seasoning layer on the chamber interior surfaces - Plasma immersion ion implantation employing a very high RF bias voltage on an electrostatic chuck to attain a requisite implant depth profile is carried out by first depositing a partially conductive silicon-containing seasoning layer over the interior chamber surfaces prior to wafer introduction. | 08-06-2009 |
20090203197 | NOVEL METHOD FOR CONFORMAL PLASMA IMMERSED ION IMPLANTATION ASSISTED BY ATOMIC LAYER DEPOSITION - Embodiments of the invention provide a novel apparatus and methods for forming a conformal doped layer on the surface of a substrate. A substrate is provided to a process chamber, and a layer of dopant source material is deposited by plasma deposition, atomic layer deposition, or plasma-assisted atomic layer deposition. The substrate is then subjected to thermal processing to activate and diffuse dopants into the substrate surface. | 08-13-2009 |
20110159673 | NOVEL METHOD FOR CONFORMAL PLASMA IMMERSED ION IMPLANTATION ASSISTED BY ATOMIC LAYER DEPOSITION - Embodiments of the invention provide a novel apparatus and methods for forming a conformal doped layer on the surface of a substrate. A substrate is provided to a process chamber, and a layer of dopant source material is deposited by plasma deposition, atomic layer deposition, or plasma-assisted atomic layer deposition. The substrate is then subjected to thermal processing to activate and diffuse dopants into the substrate surface. | 06-30-2011 |
20110207307 | PLASMA IMMERSION ION IMPLANTATION METHOD USING A PURE OR NEARLY PURE SILICON SEASONING LAYER ON THE CHAMBER INTERIOR SURFACES - Plasma immersion ion implantation employing a very high RF bias voltage on an electrostatic chuck to attain a requisite implant depth profile is carried out by first depositing a partially conductive silicon-containing seasoning layer over the interior chamber surfaces prior to wafer introduction. | 08-25-2011 |
20120171391 | THIN FILM DEPOSITION USING MICROWAVE PLASMA - Embodiments of the present invention generally provide deposition processes for a silicon-containing dielectric layer using an improved microwave-assisted CVD chamber. In one embodiment, a method of processing a substrate in a processing chamber is provided. The method generally includes applying a microwave power to an antenna coupled to a microwave source disposed within the processing chamber, wherein the microwave source is disposed relatively above a gas feeding source configured to provide a gas distribution coverage covering substantially an entire surface of the substrate, and exposing the substrate to a microwave plasma generated from a processing gas provided by the gas feeding source to deposit a silicon-containing layer on the substrate at a temperature lower than about 200 degrees Celsius, the microwave plasma using a microwave power of about 500 milliWatts/cm | 07-05-2012 |
20120326592 | Transmission Line RF Applicator for Plasma Chamber - A transmission line RF applicator apparatus and method for coupling RF power to a plasma in a plasma chamber. The apparatus comprises an inner conductor and one or two outer conductors. The main portion of each of the one or two outer conductors includes a plurality of apertures that extend between an inner surface and an outer surface of the outer conductor. | 12-27-2012 |
20130068161 | GAS DELIVERY AND DISTRIBUTION FOR UNIFORM PROCESS IN LINEAR-TYPE LARGE-AREA PLASMA REACTOR - An apparatus for introducing gas into a processing chamber comprising one or more gas distribution tubes having gas-injection holes which may be larger in size, greater in number, and/or spaced closer together at sections of the gas introduction tubes where greater gas conductance through the gas-injection holes is desired. An outside tube having larger gas-injection holes may surround each gas distribution tube. The gas distribution tubes may be fluidically connected to a vacuum foreline to facilitate removal of gas from the gas distribution tube at the end of a process cycle. | 03-21-2013 |
20130087783 | METHODS FOR DEPOSITING A SILICON CONTAINING LAYER WITH ARGON GAS DILUTION - Embodiments of the disclosure generally provide methods of forming a silicon containing layers in TFT devices. The silicon can be used to form the active channel in a LTPS TFT or be utilized as an element in a gate dielectric layer, a passivation layer or even an etch stop layer. The silicon containing layer is deposited by a vapor deposition process whereby an inert gas, such as argon, is introduced along with the silicon precursor. The inert gas functions to drive out weak, dangling silicon-hydrogen bonds or silicon-silicon bonds so that strong silicon-silicon or silicon-oxygen bonds remain to form a substantially hydrogen free silicon containing layer. | 04-11-2013 |
20130221833 | Transmission line RF applicator for plasma chamber - A transmission line RF applicator apparatus and method for coupling RF power to a plasma in a plasma chamber. The apparatus comprises an inner conductor and one or two outer conductors. The main portion of each of the one or two outer conductors includes a plurality of apertures that extend between an inner surface and an outer surface of the outer conductor. | 08-29-2013 |
20130302999 | SIOX PROCESS CHEMISTRY DEVELOPMENT USING MICROWAVE PLASMA CVD - Methods for processing a substrate are described herein. Methods can include positioning a substrate in a processing chamber, maintaining the processing chamber at a temperature below 400° C., flowing a reactant gas comprising either a silicon hydride or a silicon halide and an oxidizing precursor into the process chamber, applying a microwave power to create a microwave plasma from the reactant gas, and depositing a silicon oxide layer on at least a portion of the exposed surface of a substrate. | 11-14-2013 |
20140273312 | PIN HOLE EVALUATION METHOD OF DIELECTRIC FILMS FOR METAL OXIDE SEMICONDUCTOR TFT - The present invention generally relates to methods measuring pinhole determination. In one aspect, a method of measuring pinholes in a stack, such as a TFT stack, is provided. The method can include forming an active layer on a deposition surface of a substrate, forming a dielectric layer over the active layer, delivering an etchant to at least the dielectric layer, to etch both the dielectric layer and any pinholes formed therein and optically measuring the pinhole density of the etched dielectric layer using the active layer. | 09-18-2014 |
Shinuk Cho, Santa Barbara, CA US
Patent application number | Description | Published |
---|---|---|
20110175064 | Light emitting device and method of fabricating the same - A light emitting device may include a first electrode on a substrate, a first emission layer on the first electrode, a buffer layer on the first emission layer, a middle electrode on the buffer layer, a second emission layer on the middle electrode, and a second electrode on the second emission layer. The buffer layer may include a material selected from the group consisting of a metal oxide, a polyelectrolyte, and a combination thereof. The first emission layer, buffer layer, middle electrode, and second emission layer may be fabricated using a wet process. | 07-21-2011 |
20130234116 | ORGANIC MICROELECTRONIC DEVICE AND FABRICATION METHOD THEREFOR - An organic electronic device includes an active region polarity definition layer, and a bulk heterojunction active layer formed on the active region polarity definition layer. The bulk heterojunction active layer includes an upper region and a lower region having respective majority carriers localized therein of different polarities. | 09-12-2013 |
Soogyung Cho, Corona Del Mar, CA US
Patent application number | Description | Published |
---|---|---|
20090240609 | SYSTEM AND METHOD FOR TRACKING AND ANALYZING LOANS INVOLVED IN ASSET-BACKED SECURITIES - Embodiments of the disclosure are directed to providing unique loan identifiers to track loans involved in Asset-Backed Securities (ABS) throughout the life-cycle of the individual loans. In one embodiment, a unique loan identifier, for example, a loan number, may be appended to loan data at initiation of each loan, for example, at the application stage, to and/or beyond the retirement of the loan. The unique loan identifiers may allow disparate financial data sources such as the credit histories of the borrowers to be associated with the individual loans, even as the loans are repackaged and resold as ABS in the secondary markets. Thus, market participants such as loan servicers and investors can access current and historical data associated with the loans. Other embodiments are directed to analyzing the data associated with the underlying loans and providing the analysis to the market participants including servicers, investors, and underwriters. | 09-24-2009 |
Sung Hwan Cho, La Jolla, CA US
Patent application number | Description | Published |
---|---|---|
20120078531 | FLUIDIC FLOW CYTOMETRY DEVICES AND PARTICLE SENSING BASED ON SIGNAL-ENCODING - Microfluidic devices, systems and techniques in connection with particle sorting in liquid, including cytometry devices and techniques and applications in chemical or biological testing and diagnostic measurements. | 03-29-2012 |
20130083315 | FLUIDIC FLOW CYTOMETRY DEVICES AND METHODS - Devices, systems and methods facilitate analyzing, identifying and sorting particles in fluids, including cytometry devices and techniques. The described techniques can be used in a variety of applications such as in chemical or biological testing and diagnostic measurements. One exemplary flow cytometry device includes a channel that is capable of conducting a fluid containing at least one particle and also capable of allowing light be transmitted to and from the channel. The flow cytometry device also includes a lens that is positioned between the channel and a color filter. The lens directs at least a portion of light transmitted from the channel to the color filter. The color filter includes a plurality of zones, where each zone is adapted to allow transmission of only a particular spectral range of light. The flow cytometry device further includes a detector configured to receive the light that is transmitted through the color filter. | 04-04-2013 |
Sung Il Cho, San Diego, CA US
Patent application number | Description | Published |
---|---|---|
20110110174 | System and Method of Operating a Memory Device - A system and method of operating a memory device is disclosed. In a particular embodiment, an apparatus is disclosed that includes a bit cell coupled to a first bit line and to a second bit line. The apparatus also includes a sense amplifier coupled to the first bit line and to the second bit line. The apparatus includes a loop circuit configured to provide a sense amplifier enable signal to the sense amplifier in response to receiving a first signal. The apparatus also includes a wordline enable circuit configured to provide a wordline enable signal to a wordline driver in response to receiving a second signal. The loop circuit receives the first signal before the wordline enable circuit receives the second signal. | 05-12-2011 |
Thomas B. Cho, Fremont, CA US
Patent application number | Description | Published |
---|---|---|
20110116399 | ANALOG BIAS CONTROL FOR PACKET COMMUNICATION SYSTEMS - Apparatus having corresponding methods and non-transitory computer-readable media comprise an amplifier configured to amplify signals according to a bias current, wherein the signals represent packets of data; a packet module configured to recover the packets of data from the signals amplified by the amplifier; and a control module configured to control the bias current according to one or more characteristics of the packets of data. | 05-19-2011 |
20110204724 | Dual Output Direct Current (DC)-DC Regulator - An apparatus includes a first switch coupled to a first voltage reference and a second switch coupled to a second voltage reference. A third switch is coupled to a first terminal of a first capacitor and a first terminal of a second capacitor. A fourth switch is coupled to a second terminal of the first capacitor and the first terminal of the second capacitor. A fifth switch is coupled to the second terminal of the first capacitor and a first terminal of a third capacitor. A sixth switch is coupled to the first terminal of the first capacitor and the first terminal of the third capacitor. The first switch, the second switch, the third switch, the fourth switch, the fifth switch, and the sixth switch are controlled to maintain a first voltage level at a first output and a second voltage level at a second output. | 08-25-2011 |
20140071721 | VOLTAGE REGULATOR AND METHOD FOR REGULATING DUAL OUTPUT VOLTAGES BY SELECTIVE CONNECTION BETWEEN A VOLTAGE SUPPLY AND MULTIPLE CAPACITANCES - A voltage regulator including a first, second, and third capacitances, first switches, and second switches. A first terminal of the first capacitance is connected to a first output. The first output is at a first output voltage. A first terminal of the second capacitance is connected to a second output. The second output is at a second output voltage. The first switches connect a first terminal of the third capacitance to a voltage supply, the first output, or the second output. The second switches connect a second terminal of the third capacitance to a reference terminal, the first output, or the second output. The first and second switches are controlled, based on the first output voltage and the second output voltage, to: adjust voltages across the first, second, and third capacitances; maintain the first output at a first predetermined voltage; and maintain the second output at a second predetermined voltage. | 03-13-2014 |
Tom K. Cho, Los Altos Hills, CA US
Patent application number | Description | Published |
---|---|---|
20100285240 | APPARATUS AND METHOD FOR EXPOSING A SUBSTRATE TO A ROTATING IRRADIANCE PATTERN OF UV RADIATION - Embodiments of the invention relate generally to an ultraviolet (UV) cure chamber for curing a dielectric material disposed on a substrate and to methods of curing dielectric materials using UV radiation. A substrate processing tool according to one embodiment comprises a body defining a substrate processing region; a substrate support adapted to support a substrate within the substrate processing region; an ultraviolet radiation lamp spaced apart from the substrate support, the lamp configured to transmit ultraviolet radiation to a substrate positioned on the substrate support; and a motor operatively coupled to rotate at least one of the ultraviolet radiation lamp or substrate support at least 180 degrees relative to each other. The substrate processing tool may further comprise one or more reflectors adapted to generate a flood pattern of ultraviolet radiation over the substrate that has complementary high and low intensity areas which combine to generate a substantially uniform irradiance pattern if rotated. Other embodiments are also disclosed. | 11-11-2010 |
20110164955 | PROCESSING CHAMBER WITH TRANSLATING WEAR PLATE FOR LIFT PIN - Embodiments of a method and apparatus for processing large area substrates including a translational wear plate and/or bushing assembly are provided for reducing the stress on a lift pin used to space substrates from a substrate support in a processing or other type of chamber. In another embodiment, an apparatus for processing substrates includes processing chamber comprising a substrate support disposed in a chamber body. A bushing assembly is disposed in the substrate support. A lift pin is disposed through the bushing assembly. A wear plate is provided that is coupled to the chamber body and aligned with the lift pin. The wear plate is movable laterally relative to a centerline of the chamber body to accommodate lateral motion of the lift pin when contacting the wear plate. | 07-07-2011 |
Yonah Cho, Sunnyvale, CA US
Patent application number | Description | Published |
---|---|---|
20100248435 | METHOD OF SELECTIVE NITRIDATION - Methods of forming semiconductor devices are provided herein. In some embodiments, a method of forming a semiconductor device may include providing a substrate having an oxide surface and a silicon surface; forming a nitrogen-containing layer on exposed portions of both the oxide and silicon surfaces; and oxidizing the nitrogen-containing layer to selectively remove the nitrogen-containing layer from atop the oxide surface. In some embodiments, an oxide layer is formed atop a remaining portion of the nitrogen-containing layer formed on the silicon feature. In some embodiments, the oxide surface is an exposed surface of a shallow trench isolate region (STI) disposed adjacent to one or more floating gates of a semiconductor device. In some embodiments, the silicon surface is an exposed surface of a silicon or polysilicon floating gate of a semiconductor device. | 09-30-2010 |
20100264470 | NMOS TRANSISTOR DEVICES AND METHODS FOR FABRICATING SAME - NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, a method for forming an NMOS transistor may include providing a substrate having a p-type silicon region and a gate stack disposed thereon, the gate stack partially defining a source and a drain region; depositing an undoped first silicon layer having a lattice adjusting element atop the p-type silicon region and within the source and the drain regions; and depositing a second silicon layer having a lattice adjusting element and an n-type dopant atop the undoped first silicon layer. | 10-21-2010 |
20100317186 | ENHANCING NAND FLASH FLOATING GATE PERFORMANCE - Embodiments described herein generally relate to flash memory devices and methods for manufacturing flash memory devices. In one embodiment, a method for selective removal of nitrogen from the nitrided areas of a substrate is provided. The method comprises positioning a substrate comprising a material layer disposed adjacent to an oxide containing layer in a processing chamber, exposing the substrate to a nitridation process to incorporate nitrogen onto the material layer and the exposed areas of the oxide containing layer, and exposing the nitrided material layer and the nitrided areas of the oxide containing layer to a gas mixture comprising a quantity of a hydrogen containing gas and a quantity of an oxygen containing gas to selectively remove nitrogen from the nitrided areas of the oxide containing layer relative to the nitrided material layer using a radical oxidation process. | 12-16-2010 |
20100330814 | METHODS OF FORMING OXIDE LAYERS ON SUBSTRATES - Methods for processing substrates are provided herein. In some embodiments, a method for processing a substrate includes providing a substrate having an oxide layer disposed thereon, the oxide layer including one or more defects; and exposing the oxide layer to a plasma formed from a process gas comprising an oxygen-containing gas to repair the one or more defects. In some embodiments, the oxide layer may be formed on the substrate. In some embodiments, forming the oxide layer further comprises depositing the oxide layer atop the substrate. In some embodiments, forming the oxide layer further comprises thermally oxidizing the surface of the substrate to form the oxide layer. In some embodiments, a processing temperature is maintained at about 700 degrees Celsius or below during the thermal oxidation of the surface. | 12-30-2010 |
20110278651 | NMOS TRANSISTOR DEVICES AND METHODS FOR FABRICATING SAME - NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, an NMOS transistor may include a transistor stack comprising a gate dielectric and a gate electrode formed atop a p-type silicon region; and a source/drain region disposed on both sides of the transistor stack and defining a channel region therebetween and beneath the transistor stack, the source drain region including a first silicon layer having a lattice adjusting element and one or more second silicon layers having a lattice adjusting element and an n-type dopant disposed atop the first silicon layer. | 11-17-2011 |
Yong Eun Cho, Cambell, CA US
Patent application number | Description | Published |
---|---|---|
20100325377 | SYSTEM AND METHOD FOR RESTORING DATA ON DEMAND FOR INSTANT VOLUME RESTORATION - A technique is disclosed for restoring data of sparse volumes, where one or more block pointers within the file system structure are marked as ABSENT, and fetching the appropriate data from an alternate location on demand. Client data access requests to the local storage system initiate a restoration of the data from a backing store as required. A demand generator can also be used to restore the data as a background process by walking through the sparse volume and restoring the data of absent blocks. A pump module is also disclosed to regulate the access of the demand generator. Once all the data has been restored, the volume contains all data locally, and is no longer a sparse volume. | 12-23-2010 |
Yong Moon Cho, Hacienda Heights, CA US
Patent application number | Description | Published |
---|---|---|
20090325454 | Pinata expandable to a plurality of positions - Expandable piñata is a decorative container constructed from sheet materials connected at the edges, which can be shipped and stored flat. An internal expandable brace is activated by pulling external cords that draw brace into the expanded position, causing piñata body to flex into a three-dimensional body with fillable chamber. Score lines optionally direct flexing into a faceted shape. Lock mechanism holds brace in the erect configuration, with adjustable degree of expansion. Piñata body is resilient and compresses brace, to engage lock automatically and maintain expanded configuration. | 12-31-2009 |
Young Geun Cho, Palo Alto, CA US
Patent application number | Description | Published |
---|---|---|
20110254714 | METHOD AND APPARATUS FOR SOFT SYMBOL DETERMINATION - A method for wireless communication is disclosed that includes selecting a plurality of probabilities for a symbol based on a bit-to-symbol mapping; calculating a conditional mean of the symbol based on the plurality of probabilities; and, generating a signal representative of the symbol based on the conditional mean of the symbol. An apparatus for performing the method is also disclosed. | 10-20-2011 |
20120142276 | METHOD AND APPARATUS FOR DATA AIDED CHANNEL QUALITY ESTIMATION - Methods and apparatuses for data aided channel quality estimation using both pilot and data information are disclosed herein. In one exemplary aspect, a method for estimating channel quality in a wireless communication system is disclosed. The method comprises estimating a pilot noise variance based on a pilot signal received from a base station on a downlink and estimating a data noise variance based on a data signal received from the base station on the downlink. The method also comprises combining the pilot noise variance and the data noise variance to obtain a combined noise variance, and estimating the channel quality based on the combined noise variance. | 06-07-2012 |
20120249346 | METHOD AND APPARATUS FOR SOFT SYMBOL DETERMINATION - A method for wireless communication is disclosed that includes selecting a plurality of probabilities for a symbol based on a bit-to-symbol mapping; calculating a conditional mean of the symbol based on the plurality of probabilities; and, generating a signal representative of the symbol based on the conditional mean of the symbol. An apparatus for performing the method is also disclosed. | 10-04-2012 |
Young Kyu Cho, San Jose, CA US
Patent application number | Description | Published |
---|---|---|
20120138139 | DRY ETCHING METHOD OF SURFACE TEXTURE FORMATION ON SILICON WAFER - Systems and methods for improving surface reflectance of silicon wafers are disclosed. The systems and methods improve surface reflectance by forming a textured surface on the silicon wafer by performing surface oxidation and dry etching processes. The surface oxidation maybe performed using a dry oxygen plasma process. A dry etch process is performed to remove the oxide layer formed by the surface oxidation step and etch the Silicon layer with oxide masking. Dry etching enables black silicon formation, which minimizes or eliminates light reflection or scattering, eventually leading to higher energy conversion efficiency. | 06-07-2012 |
20120138230 | SYSTEMS AND METHODS FOR MOVING WEB ETCH, CVD, AND ION IMPLANT - Systems and methods for moving substrates through process chambers for photovoltaic (PV) or solar cell applications are disclosed. In particular, systems and methods for moving substrates through process chambers using a conveyor belt are disclosed. The conveyor belt can be used to move the substrates through etch chambers, chemical vapor deposition (CVD) chambers, and/or ion implant chambers, and the like. | 06-07-2012 |
20120291955 | LARGE AREA ICP SOURCE FOR PLASMA APPLICATION - An arrangement for coupling RF energy for inductively coupled plasma chamber. The RF coil or radiator is embedded within a groove made in the ceiling of the chamber and an insulating filler covers the coil within the groove. The ceiling may be made of two plates: an upper plate made of conductive material and a bottom plate made of dielectric material. The two plates are in physical contact. A magnetic shield may be provided over the coil to control the spread of the magnetic field from the coil. Fluid channels may be made in the conductive plate to provide thermal control. Also, fluid conduits may be provided to allow injecting gas into the pace between the metal and dielectric plates. | 11-22-2012 |
20120295394 | METHOD FOR REAR POINT CONTACT FABRICATION FOR SOLAR CELLS - A method for forming holes in the backside dielectric layer of solar cells for fabrication of rear point contact. The backside dielectric layer is coated with a layer of carbon. A shadow mask is placed over the carbon layer and reactive ion etch (RIE) is used to transfer the holes in the shadow mask to the carbon layer, to thereby form a carbon mask. The shadow mask is then removed and RIE is used to transfer the holes from the carbon mask to the dielectric layer. The carbon mask is then removed by, e.g., ashing. | 11-22-2012 |
20130087531 | INDUCTIVE/CAPACITIVE HYBRID PLASMA SOURCE AND SYSTEM WITH SUCH CHAMBER - A plasma processing chamber having capacitive and inductive coupling of RF power. An RF power source is connected to an inductive coil and to a top electrode via a variable capacitor to control the ratio of power applied to the coil and electrode. The bottom electrode, which is part of the chuck holding the substrates, is floating, but has parasitive capacitance coupling to ground. No RF bias is applied to the chuck and/or the substrate, but the substrate is chucked using DC power. In a system utilizing the chamber, the chuck is movable and is loaded with substrates outside the chamber, enter the chamber from one side for processing, exit the chamber from an opposite side after the processing, and is unloaded in an unloading chamber. The chuck is then transported back to the loading chamber. Substrates are delivered to and removed from the system using conveyor belts. | 04-11-2013 |
20130105087 | SOLAR WAFER ELECTROSTATIC CHUCK | 05-02-2013 |
20130109189 | SYSTEM ARCHITECTURE FOR PLASMA PROCESSING SOLAR WAFERS | 05-02-2013 |
Young Sang Cho, El Cajon, CA US
Patent application number | Description | Published |
---|---|---|
20100122220 | Method of and apparatus for dynamically generating a user presentation based on database stored rules - A method of dynamically generating a user presentation includes selecting and retrieving at least one of a plurality of rules stored in one or more databases in response to a request from an application program, executing the rule to retrieve data from the one or more databases, and generating presentation data based on the data. The presentation data may be for use in the user presentation of the application program. | 05-13-2010 |
Yushin Cho, Sunnyvale, CA US
Patent application number | Description | Published |
---|---|---|
20100104027 | ADAPTIVE PREPROCESSING METHOD USING FEATURE-EXTRACTED VIDEO MAPS - A method and apparatus for preprocessing a video signal prior to its being encoded. During preprocessing, features are extracted from the video signal into feature planes which are each adaptively filtered in response to estimations of feature activity. After feature extraction the signal which remains is referred to as a “remaining signal”, which is then noise filtered to remove a substantial portion of the noise. The feature planes and remaining signal are recombined into a preprocessed output signal configured for receipt and processing by a video encoder. A video encoder receiving the preprocessed video signal can generate higher quality and/or lower bit rate encoded video than one receiving the original source video. Preprocessing according to the invention is particularly well suited for use with encoders adapted to remove temporal and/or spatial redundancy, such as those implemented according to the MPEG2/4, or AVC/H.264 standards. | 04-29-2010 |
20110074967 | TARGET BIT RATE DECISION METHOD FOR WAVELET-BASED IMAGE COMPRESSION - A method of deciding a target bit rate for wavelet-based image encoding based on the wavelet coefficients is described. The target bit rate is used for maintaining a high quality image. A minimum target bit rate and a maximum target bit rate are determined. A pseudo code length corresponding to the minimum target bit rate is calculated. The pseudo code length is calculated as a function of the wavelet coefficients. The corresponding pseudo code length is calculated for the maximum target bit rate. A curve between the pseudo code length and target bit rate is derived. Slope of the curve depends on buffer fullness. Using the curve, for a given pseudo code length, an appropriate target bit rate is derived. The derived target bit rate depends on the image content, and computing resources are able to be optimally used to attain similar quality for each image block of an image. | 03-31-2011 |
20110074976 | METHOD OF DETECTING THE EXISTENCE OF VISUALLY SENSITIVE THIN LINES IN A DIGITAL IMAGE - A method of detecting existence of visually thin lines in images is described herein. The method includes profile generation, profile analysis and deciding the existence of thin lines. The profile generation includes generating a profile in each direction of the input image. Multiple projection lines are projected along the direction and all of the pixel values along the projection lines are added and averaged to obtain a profile. The profile analysis includes determining presence of thin lines in the input image and also noticing if the direction of the thin lines is similar to that of the projection lines. At the third step, according to the analysis made, existence of thin lines in the image is decided. | 03-31-2011 |