Patent application number | Description | Published |
20140149207 | SYSTEM AND METHOD FOR IMPLEMENTING ADVERTISEMENT PUSH AND MARKETING - A system and method for implementing advertisement push and marketing are provided. Target location information and location information are provided by a client. A driving path is planned by a server according to the target location information and the location information, so that an advertisement corresponding to the location information is queried. The queried advertisement is fed back and provided for users to click. Therefore, the technical efficacy of implementing advertisement push and marketing is achieved. | 05-29-2014 |
20140149220 | PLAY INFORMATION ESTABLISHING AND PLAYING SYSTEM, AND METHOD THEREOF - A play information establishing and playing system, and a method thereof are provided. When an information establishing client sends coordinate information and play information to a server to establish a play information in the server, and a information query client sends queried coordinate information to the server, the corresponding play information is queried according to the queried coordinate information, and is provided to the information query client to play the play information, so as to achieve the technical efficacy of providing a corresponding play information according to different coordinate information. | 05-29-2014 |
20140149495 | CLOUD-BASED ROUTE PLANNING SYSTEM AND METHOD THEREOF - A cloud-based route planning system and a method thereof are provided. A server provides a route plan message, continuously receives a positioning message of a first client, and displays the route plan message and the positioning message on the first client. After a second client logs in to the server, the server sets a right for the second client according to a user state of the second client and allows the second client to select and download a route plan message. When the user state is browsing, the server displays on the second client both the positioning message of the first client and the route plan message downloaded by the second client, and when the user state is feedback, the second client is allowed to upload a feedback message to modify the route plan message. | 05-29-2014 |
20140150062 | SYSTEM FOR PROVIDING LEARNING ACCORDING TO GLOBAL POSITIONING INFORMATION AND METHOD THEREOF - A system for providing learning according to global positioning information and a method thereof are provided. A server queries for a corresponding learning content according to global positioning information provided by a first client, so that a student can learn anytime and anywhere. The server records contents already learnt by the student. A corresponding test type and test content are provided for a second client, and selection is performed to generate a test paper, which is provided for the first client so that the student can take a test. Therefore, learning anytime and anywhere is enabled, thereby achieving the technical effect of optimal learning efficiency. | 05-29-2014 |
20140156184 | NAVIGATION MESSAGE PROVIDING SYSTEM AND METHOD THEREOF - A navigation message providing system and a method thereof are provided. A server searches, according to a planned moving path, for a location message corresponding to a target location, and when determining that a distance or a relative position of a position where the navigation terminal is currently located and the target location satisfies a predetermined condition or determining that preset time or a preset position is met, a navigation terminal displays the satisfied or met location message, so as to give a prompt to a user when close to the target location, and achieve the technical efficacy of proactively providing location message of the target location. | 06-05-2014 |
20140156342 | SYSTEM FOR SELECTING TARGET DATA ACCORDING TO ATTENTION TIME AND METHOD THEREOF - A system for selecting target data according to attention time and a method thereof are provided. After a user image is captured when target data is displayed, attention time in which a user gazes at the target data is determined according to the captured user image, and statistics are made on the attention time to use the attention time as a technical means for selecting target data in a next time. Responses of the user when the user watches displayed information may be collected, so as to assist a provider of the target data to know whether the user understands the provided target data and/or is interested in the provided target data, thereby achieving the technical efficacy of selecting target data suitable for the user. | 06-05-2014 |
20140156803 | TRANSACTION SYSTEM FOR EXCHANGING COMMODITY DATA VIA PORTABLE STORAGE DEVICE AND METHOD THEREOF - A transaction system for exchanging commodity data via a portable storage device and a method thereof are provided. Commodity content of a candidate commodity sold on a server is stored in the portable storage device, commodity identification data of the candidate commodity selected by a user is stored after the user uses an operating device to select the candidate commodity stored in the storage device, and the server generates transaction result information according to the commodity identification data stored in the storage device. By using the technical means, the transaction system and the method thereof can prevent a network transaction platform from affecting consumption due to management conditions, and achieve the technical efficacy of effectively providing a commodity to a specific group merely. | 06-05-2014 |
Patent application number | Description | Published |
20090107627 | Method of manufacturing a laminated paperboard with an opaque plastic film for printing a color label thereon - In one embodiment a method of manufacturing a laminated paperboard includes feeding a reel of opaque plastic (e.g., PP, PVC, PET, or PE) film to a multiple color gravure device; activating the color gravure device to print a color label on the top surface of the plastic film by applying ink thereon; feeding the plastic film to a pressing device and feeding a reel of paper member (e.g., paper or paperboard) under the plastic film to the pressing device; activating the pressing device to apply an adhesive on a joining surface of the passing paper member and the passing plastic film; activating a drying device to dry the adhesive to fasten the plastic film and the paper member together to form a laminated paperboard; and feeding the laminated paperboard to a cutter for cutting the laminated paperboard into a plurality of units of predetermined size. | 04-30-2009 |
20090308529 | METHOD OF MANUFACTURING A LAMINATED PAPERBOARD WITH AN OPAQUE PLASTIC FILM FOR PRINTING A COLOR LABEL THEREON - In one embodiment a method of manufacturing a laminated paperboard includes feeding a reel of opaque plastic (e.g., PP, PVC, PET, or PE) film to a first pressing device and feeding a reel of paper member (e.g., paper or paperboard) under the plastic film to the first pressing device; activating the first pressing device to apply a first adhesive on a joining surface of the passing paper member and the passing plastic film; activating a drying device to dry the first adhesive to fasten the plastic film and the paper member together to form a laminated paperboard; feeding the laminated paperboard to a color gravure device; activating the color gravure device to print a color label on the top surface of the laminated paperboard by applying ink thereon; and feeding the laminated paperboard to a cutter for cutting the laminated paperboard into a plurality of units of predetermined size. | 12-17-2009 |
20110120643 | Process of manufacturing paperboard with textile surface - A process of manufacturing paperboard includes mixing a predetermined weight percentage of polypropylene and a predetermined weight percentage of polyethylene in a tank; heating the tank to a predetermined temperature for forming an adhesive of the polypropylene and the polyethylene; flowing the adhesive out of the tank to coat on an outer surface of an endless, continuous paperboard member moving thereunder; and moving an endless, continuous textile to place on the adhesive at a joining line of a pair of opposite rotating rolls so that the rolls press the textile, the adhesive, and the paperboard member to cause the adhesive to adhere the textile and the paperboard member together to produce the finished paperboard having a textile surface. | 05-26-2011 |
20110120644 | Process of manufacturing heavy paper pulp based board - A process of manufacturing heavy paper pulp based board comprising flowing liquefied starch based adhesive onto a plurality of endless, continuous, stacked paperboards; conveying the paperboards coated with the starch based adhesive to a joining line of a pair of opposite drive rolls; and conveying an endless, continuous linerboard to the joining line of the drive rolls so that the drive rolls press the linerboard, the starch based adhesive, and the paperboards from top to bottom to produce the finished heavy paper pulp based board. The heavy paper pulp based board can be further cut into desired units. | 05-26-2011 |
20110120827 | Foldable paper wheeled luggage - A wheeled luggage includes a folding main body formed of heavy paper pulp based board and comprising a folding a top panel and a folding handle panel, the handle panel being opposite the top panel and including at least one opening; and a wheel assembly disposed at a bottom edge of the main body. The wheel assembly is made of heavy paper pulp based board. The number of the at least one opening is two. The handle panel further comprises an elastic strap. | 05-26-2011 |
20110123781 | Corrugated fiberboard for bullet-resistant vest - A corrugated fiberboard includes a top linerboard comprising an upper layer of PE and a lower layer of paper; a corrugated sheet comprising a plurality of layers of corrugation trough support, each of the layers of corrugation trough support having a crush resistance in a range of 90 g/m | 05-26-2011 |
Patent application number | Description | Published |
20110133875 | Stack inductor with different metal thickness and metal width - A stacked inductor with different metal thickness and metal width is represented in this invention, this structure comprise: top and bottom metal trace, which is aligned with each other. The thickness and width of top and bottom metal trace are different. The top and bottom metal trace are connected at the end of metal trace with via holes. The inductance is increased with the use of the mutual inductance between top and bottom metal layers, and the parasitic resistor is reduced by means of different top and bottom metal width. This stacked inductor possesses larger inductance than single layer spiral inductor with relatively higher Q factor. | 06-09-2011 |
20110133876 | Manufacture method for IC process with TOP and TOP-1 metal layers thickened and stacked inductor manufactured by this method - A manufacture method for IC process with top and top-1 metal layers thickened and stacked inductor manufactured by this method is represented in this invention. This method includes: with multi metal layers, and the thickness of top and top-1 metal layers are more than 2.8 um. Thickened top and top-1 metal layers can reduce the resistance of top and top-1 metal layers, so can increase the Q factor of inductor. | 06-09-2011 |
20110133877 | Stacked inductor with multi paths for current compensation - A multi-path stacked inductor for current compensation is represented in this invention. This structure includes top and bottom metal trace, which are aligned with each other. Each metal trace consists of multi paths. The inner path in top metal flips over to the outer path in the bottom metal, while the outer path in top metal flips over to the inner path in the bottom metal. These paths join together at the end of the metal trace with via holes. Skin effect and current crowding effect are reduced by means of this method. This stacked inductor possesses larger inductance than single layer spiral inductor, with relatively higher Q factor. | 06-09-2011 |
20110133879 | STACKED INDUCTOR - A stacked inductor with combined metal layers is represented in this invention. The stacked inductor includes: a top layer metal coil, and at least two lower layer metal coils, the metal coils being aligned with each other; adjacent metal coils being connected at the corresponding ends through a via; wherein, each of the lower layer metal coils is consisted of plural layers of metal lines which are interconnected. With the same chip area, the stacked inductor of the present invention can achieve higher inductance and Q factor because of the mutual inductance generated from the plural layers of metal lines and the reduced parasitic resistance. | 06-09-2011 |
20110140239 | High Voltage Bipolar Transistor with Pseudo Buried Layers - A high voltage bipolar transistor with shallow trench isolation (STI) comprises the areas of a collector formed by implanting first electric type impurities into active area and connected with pseudo buried layers at two sides; Pseudo buried layers which are formed by implanting high dose first type impurity through the bottoms of STI at two sides if active area, and do not touch directly; deep contact through field oxide to contact pseudo buried layers and pick up the collectors; a base deposited on the collector by epitaxial growth and in-situ doped by second electric type impurity, in which the intrinsic base touches local collector and extrinsic base is used for base pick-up; a emitter which is a polysilicon layer deposited on the intrinsic base and doped with first electric type impurities. This invention makes the depletion region of collector/base junction from 1D (vertical) distribution to 2D (vertical and lateral) distribution. The bipolar transistor's breakdown voltages are increased by only enlarge active critical dimension (CD). This is low-cost process. | 06-16-2011 |
20110147793 | SiGe HETEROJUNCTION BIPOLAR TRANSISTOR MULTI-FINGER STRUCTURE - The present invention provides a multi-finger structure of a SiGe heterojunction bipolar transistor (HBT). It is consisted of plural SiGe HBT single cells. The multi-finger structure is in a form of C/BEBC/BEBC/.../C, wherein, C, B, E respectively stands for collector, base and emitter; CBEBC stands for a SiGe HBT single cell. The collector region is consisted of an n type ion implanted layer inside the active region. The bottom of the implanted layer is connected to two n type pseudo buried layers. The two pseudo buried layers are formed through implantation to the bottom of the shallow trenches that surround the collector active region. Two collectors are picked up by deep trench contact through the field oxide above the two pseudo buried layers. The present invention can reduce junction capacitance, decrease collector electrode output resistance, and improve device frequency characteristics. | 06-23-2011 |
20110147892 | Bipolar Transistor with Pseudo Buried Layers - A structure and fabrication method for a bipolar transistor with shallow trench isolation (STI) comprises a collector formed by implanting first electric type impurity in active area; pseudo buried layers at the bottom of STI at both sides of active area by implanting heavy dose of first electric type impurity; deep contacts through field oxide to connect to pseudo buried layers and to pick up the collector; a base, a thin film deposited on the collector and doped with second electric type impurity; an emitter, a polysilicon film doped by heavy dose implant of first electric type impurity. This transistor has smaller device area, less parasitic effect, less photo layers and lower process cost. | 06-23-2011 |
20110156143 | Parasitic Vertical PNP Bipolar Transistor And Its Fabrication Method In Bicmos Process - This invention published a parasitic vertical PNP bipolar transistor in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process; the bipolar transistor comprises a collector, a base and an emitter. Collector is formed by active region with p-type ion implanting layer. It connects a p-type buried layer which formed in the bottom region of STI (Shallow Trench Isolation). The collector terminal connection is through the p-type buried layer and the adjacent active region. The base is formed by active region with n type ion implanting which is on the collector. Its connection is through the original p-type epitaxy layer after converting to n-type. The emitter is formed by the p-type epitaxy layer on the base region with heavy p-type doped. This invention also comprises the fabrication method of this parasitic vertical PNP bipolar in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process. And this PNP bipolar transistor can be used as the IO (Input/Output) device in high speed, high current and power gain BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) circuits. It also provides a device option with low cost. | 06-30-2011 |
20110156151 | Electrode Pick Up Structure In Shallow Trench Isolation Process - This invention disclosed a kind of electrode pick up structure in shallow trench isolation process. The active region is isolated by shallow trench. A pseudo-buried layer under the bottom of shallow trench is formed. The pseudo-buried layer extends into active region and connects to doping region one which needs to be picked up by an electrode. The pick up is realized by deep trench contacts which etch through STI and get in touch with pseudo buried layer. This invention can reduce the device size, pick up electrode resistance, collector parasitic capacitance, and increase device cut off frequency. | 06-30-2011 |
20110156163 | Structure of electrode pick up in LOCOS - This invention disclosed a kind of electrode picking up structure in LOCOS isolation process. The active region is isolated by local oxide of silicon (LOCOS). A pseudo buried layer under the bottom of LOCOS is formed. The pseudo-buried layer extends into active region and connects to doping region one which needs to be picked up by an electrode. This is achieved by deep trench contacts which etch through LOCOS and get in touch with pseudo buried layer. This invention can reduce the device size, pick up electrode resistance, collector parasitic capacitance, and increase device cut off frequency. | 06-30-2011 |
20110156202 | Parasitic Vertical PNP Bipolar Transistor in BICMOS Process - A parasitic vertical PNP device in one type of BiCMOS process with shallow trench isolation (STI) comprises a collector formed by a p type impurity ion implantation layer inside active area, the bottom of collector connects to a p type buried layer, the p type pseudo buried layer is formed in bottom of shallow trench at both sides of collector active region through ion implantation, deep contacts through field oxide to connect pseudo buried layers and to pick up the collector; a base, formed by n type impurity ion implantation layer which sits on top of above stated collector; an emitter, a p type epitaxy layer lies above base and is connected out directly by a metal contact. Part of the p type epitaxy layer is converted into n type, which serves as connection path of base. Present invented PNP can be used as output device of BiCMOS high frequency circuit. It has a small device area and conduction resistance. | 06-30-2011 |
20110159659 | Novel Manufacturing Approach for Collector and N Type Buried Layer Of Bipolar Transistor - This invention disclosed a novel manufacturing approach of collector and buried layer of a bipolar transistor. One aspect of the invention is that an oxide-nitride-oxide (ONO) sandwich structure is employed instead of oxide-nitride dual layer structure before trench etching. Another aspect is, through the formation of silicon oxide spacer in trench sidewall and silicon oxide remaining in trench bottom in the deposition and etch back process, the new structure hard mask can effectively protect active region from impurity implanted in ion implantation process. | 06-30-2011 |
20110159672 | Novel Manufacturing Approach for Collector and N Type Buried Layer Of Bipolar Transistor - This invention disclosed a manufacturing approach of collector and buried layer of a bipolar transistor. One aspect of the invention is that a pseudo buried layer, i.e, collector buried layer, is manufactured by ion implantation and thermal anneal. This pseudo buried layer has a small area, which makes deep trench isolation to divide pseudo buried layer unnecessary in subsequent process. Another aspect is, the doped area, i.e, collector, is formed by ion implantation instead of high cost epitaxy process. This invention simplified the manufacturing process, as a consequence, saved manufacturing cost. | 06-30-2011 |
20130020652 | METHOD FOR SUPPRESSING SHORT CHANNEL EFFECT OF CMOS DEVICE - A method for manufacturing a gate-last high-K CMOS structure comprising a first transistor and a second transistor, which is formed in a Si substrate includes: implanting acceptor impurity into a gate recess of the first transistor to form a first buried-layer heavily doping region under a channel of the first transistor; and implanting donor impurity into a gate recess of the second transistor to form a second buried-layer heavily doping region under a channel of the second transistor. | 01-24-2013 |
20130140604 | SILICON-GERMANIUM HETEROJUNCTION BIPOLAR TRANSISTOR AND MANUFACTURING METHOD THEREOF - A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) is disclosed, including: a substrate; two field oxide regions formed in the substrate; two pseudo buried layers, each being formed under a corresponding one of the field oxide regions; a collector region formed between the field oxide regions, the collector region laterally extending under a corresponding one of the field oxide regions and each side of the collector region being connected with a corresponding one of the pseudo buried layers; a matching layer formed under both the pseudo buried layers and the collector region; and two deep hole electrodes, each being formed in a corresponding one of the field oxide regions, the deep hole electrodes being connected to the corresponding ones of the pseudo buried layers for picking up the collector region. A manufacturing method of the SiGe HBT is also disclosed. | 06-06-2013 |
Patent application number | Description | Published |
20080252868 | MASK-LESS METHOD AND STRUCTURE FOR PATTERNING PHOTOSENSITIVE MATERIAL USING OPTICAL FIBERS - A method for patterning objects, e.g., semiconductor wafer, glass plate, composite, etc. The method includes providing an object, which has an overlying layer of photosensitive material. The method includes selectively applying light through one or more fiber cores from a plurality of fiber cores. Each of the fiber cores has an input end and an output end. Each of the input ends is coupled to the optical source. The plurality of fiber cores is numbered from 1 through N, where N is an integer greater than 1. Each of the output ends is also numbered from 1 through N, which corresponds respectively to each of the plurality of fiber cores numbered from 1 through N. The method exposes the photosensitive material from light emitted selectively through the one or more fiber cores. The one or more fiber cores out(s) light respectively through one or more output ends of the fiber cores. Each of the output ends numbered from 1 through N is associated with a pixel numbered respectively from 1 through N. | 10-16-2008 |
20100001354 | SELF ALIGNED MOS STRUCTURE WITH POLYSILICON CONTACT - A method for fabricating a semiconductor integrated circuit and resulting structure. The method includes providing a semiconductor substrate with an overlying dielectric layer and forming a polysilicon gate layer and an overlying capping layer. The gate layer is overlying the dielectric layer. The method also includes patterning the polysilicon gate layer to form a gate structure and a local interconnect structure. The gate structure and the local interconnect structure include a contact region defined therebetween. The gate structure also includes the overlying capping layer. The method includes forming sidewall spacers on the gate structure and the local interconnect structure and removing the sidewall spacer on the local interconnect structure. The method also includes forming contact polysilicon on the contact region and implanting a dopant impurity into the contact polysilicon. The method diffuses the dopant impurity from the contact polysilicon into the contact region in the substrate to form a diffused junction region. The method selectively removes the capping layer overlying the gate structure. The method then forms a silicide layer overlying the gate structure and surface of the contact polysilicon, whereupon the sidewall spacers isolate the silicide layer on the gate structure from the silicide layer on the contact polysilicon. | 01-07-2010 |
20140048892 | SELF ALIGNED MOS STRUCTURE WITH POLYSILICON CONTACT - An integrated circuit structure has a substrate comprising a well region and a surface region, an isolation region within the well region, a gate insulating layer overlying the surface region, first and second source/drain regions within the well region of the substrate. The structure also has a channel region formed between the first and second source/drain regions and within a vicinity of the gate insulating layer, and a gate layer overlying the gate insulating layer and coupled to the channel region. The structure has sidewall spacers on edges of the gate layer to isolate the gate layer, a local interconnect layer overlying the surface region of the substrate and having an edge region extending within a vicinity of the first source/drain region. A contact layer on the first source/drain region in contact with the edge region and has a portion abutting a portion of the sidewall spacers. | 02-20-2014 |
20140103445 | SEMICONDUCTOR SRAM STRUCTURES AND FABRICATION METHODS - Various embodiments provide semiconductor structures and their fabrication methods. An SRAM memory cell can include at least one semiconductor structure, and an SRAM memory can include at least one SRAM memory cell. An exemplary semiconductor structure can include at least two adjacent transistors formed on a semiconductor substrate. An opening can be formed and surrounded by gates of the two adjacent transistors and a doped region formed between the gates of the two adjacent transistors. A conductive layer can be formed to at least partially cover a bottom and a sidewall of the opening to electrically connect a gate of one transistor with the doped region of the other transistor of the two adjacent transistors. | 04-17-2014 |
20160078970 | METHOD AND SYSTEM FOR THERMAL NUCLEAR FUSION - A method for nuclide bombardment includes providing a nuclide bombardment target, which includes a metallic single-crystalline layer having a hydrogen-absorbing metallic element. The single-crystalline layer includes lattice channels disposed therein. The target also includes first hydrogen isotopes, configured as interstitial elements in the lattice channels in the single-crystalline layer. The method further includes injecting second hydrogen isotopes into the target substantially along the direction of the lattice channels. | 03-17-2016 |
Patent application number | Description | Published |
20130237431 | SIZE-BASED ANALYSIS OF FETAL DNA FRACTION IN MATERNAL PLASMA - A fractional concentration of clinically-relevant DNA in a mixture of DNA from a biological sample is determined based on amounts of DNA fragments at multiple sizes. For example, the fractional concentration of fetal DNA in maternal plasma or tumor DNA in a patient's plasma can be determined. The size of DNA fragments in a sample is shown to be correlated with a proportion of fetal DNA and a proportion of tumor DNA, respectively. Calibration data points (e.g., as a calibration function) indicate a correspondence between values of a size parameter and the fractional concentration of the clinically-relevant DNA. For a given sample, a first value of a size parameter can be determined from the sizes of DNA fragments in a sample. A comparison of the first value to the calibration data points can provide the estimate of the fractional concentration of the clinically-relevant DNA. | 09-12-2013 |
20130245961 | METHODS FOR ANALYZING MASSIVELY PARALLEL SEQUENCING DATA FOR NONINVASIVE PRENATAL DIAGNOSIS - This invention provides several ways of managing GC bias that occurs during seequencing and analysis of genomic DNA. Maternal plasma can be used as a source of fetal DNA for analysis. DNA segments or tags obtained from the plasma can be aligned with a chromosomal region of interest and with an artificial reference chromosome assembled from regions of the genome having matching GC content. This technology can be used, for example, to detect and evaluate aneuploidy and other chromosomal abnormalities | 09-19-2013 |
20130253844 | IDENTIFYING A DE NOVO FETAL MUTATION FROM A MATERNAL BIOLOGICAL SAMPLE - Systems, methods, and apparatus for determining at least a portion of fetal genome are provided. DNA fragments from a maternal sample (maternal and fetal DNA) can be analyzed to identify alleles at certain loci. The amounts of DNA fragments of the respective alleles at these loci can be analyzed together to determine relative amounts of the haplotypes for these loci and determine which haplotypes have been inherited from the parental genomes. Loci where the parents are a specific combination of homozygous and heterozygous can be analyzed to determine regions of the fetal genome. Reference haplotypes common in the population can be used along with the analysis of the DNA fragments of the maternal sample to determine the maternal and paternal genomes. Determination of mutations, a fractional fetal DNA concentration in a maternal sample, and a proportion of coverage of a sequencing of the maternal sample can also be provided. | 09-26-2013 |
20130267425 | NONINVASIVE PRENATAL DIAGNOSIS OF FETAL TRISOMY BY ALLELIC RATIO ANALYSIS USING TARGETED MASSIVELY PARALLEL SEQUENCING - Whether a fetus has an aneuploidy associated with a first chromosome is detected using ratios of alleles detected in a maternal sample having a mixture of maternal and fetal DNA. DNA from the sample is enriched for target regions associated with polymorphic loci and then sequenced. Polymorphic loci (e.g., single nucleotide polymorphisms) in the target regions with fetal-specific alleles are identified on a first chromosome and on one or more reference chromosomes. A first ratio of the fetal-specific alleles and shared alleles is determined for the loci on the first chromosome. A second ratio of the fetal-specific alleles and shared alleles is determined for the loci on the reference chromosome(s). A third ratio of the first and second ratio can be compared to a cutoff to determine whether an aneuploidy is present, and whether the aneuploidy is maternally-derived or paternally-derived. | 10-10-2013 |
20130323731 | DETERMINATION OF THE DEPTH COVERAGE OF THE FETAL GENOME - Systems, methods, and apparatus for determining at least a portion of fetal genome are provided. DNA fragments from a maternal sample (maternal and fetal DNA) can be analyzed to identify alleles at certain loci. The amounts of DNA fragments of the respective alleles at these loci can be analyzed together to determine relative amounts of the haplotypes for these loci and determine which haplotypes have been inherited from the parental genomes. Loci where the parents are a specific combination of homozygous and heterozygous can be analyzed to determine regions of the fetal genome. Reference haplotypes common in the population can be used along with the analysis of the DNA fragments of the maternal sample to determine the maternal and paternal genomes. Determination of mutations, a fractional fetal DNA concentration in a maternal sample, and a proportion of coverage of a sequencing of the maternal sample can also be provided. | 12-05-2013 |
20140080720 | FETAL GENOMIC ANALYSIS THAT ACCOUNTS FOR GC BIAS - Systems, methods, and apparatuses for performing a prenatal diagnosis of a sequence imbalance are provided. A shift (e.g. to a smaller size distribution) can signify an imbalance in certain circumstances. For example, a size distribution of fragments of nucleic acids from an at-risk chromosome can be used to determine a fetal chromosomal aneuploidy. A size ranking of different chromosomes can be used to determine changes of a rank of an at-risk chromosome from an expected ranking. Also, a difference between a statistical size value for one chromosome can be compared to a statistical size value of another chromosome to identify a significant shift in size. A genotype and haplotype of the fetus may also be determined using a size distribution to determine whether a sequence imbalance occurs in a maternal sample relative to a genotypes or haplotype of the mother, thereby providing a genotype or haplotype of the fetus. | 03-20-2014 |
20140315200 | DETERMINING FETAL GENOMES FOR MULTIPLE FETUS PREGNANCIES - Techniques are provided for determining inheritance of maternal and paternal haplotypes in preganncies with multiple fetuses. Maternal inheritance can be determined at loci where the mother is heterozygous and the paternally inherited alleles are known (e.g., the father is homozygous). Two types of loci may be used, where one type has the paternal allele appear on a first maternal haplotype, and another type has the paternal allele appear on a second maternal haplotype. Paternal inheritance can be determined from loci where the father is heterozygous and the maother is homozygous. Amounts of different alleles at each locus can be measured. A comparison of the amounts (e.g., using a fractional concentration of each allele and cutoffs) can be used to determine the haplotype inheritance. A haplotype can be linked to a condition of interest. | 10-23-2014 |
Patent application number | Description | Published |
20090244429 | THIN FILM TRANSISTOR SUBSTRATE AND LIQUID CRYSTAL DISPLAY DEVICE USING THE SAME - The invention provides a thin film transistor (TFT) substrate comprises a plurality of gate lines, a plurality of data lines, gate terminals, data terminals and thin film transistors as well as a liquid crystal display (LCD) device having the TFT substrate. The gate terminal and/or data terminal contain a first portion and a second portion, and the first potion and the second portion are connected electrically with an end electrode made of a material which is anticorrosive in the air. The thin film transistor substrate of the invention prevents the spreading of the metal corrosion occurred at the gate leads to the display region of the LCD, and therefore the quality of the LCD device can be ensured. | 10-01-2009 |
20090262061 | Liquid Crystal Panel and Display Apparatus Including Liquid Crystal Panel - A liquid crystal panel includes a plurality of pixel units, each of which include gating lines, data lines, a pixel electrode and a thin film transistor (TFT). Common electrodes of first pixel units in a same row are electrically connected via a first common line, and common electrodes of second pixel units in the same row are electrically connected via a second common line. The first common line is connected with a first common voltage and the second common voltage is connected with a second common voltage. The first common voltage and the second common voltage are alternating current voltages and have opposite polarities in the same frame. The liquid crystal panel can decrease power consumption of a source driver and lower cost of the liquid crystal panel. | 10-22-2009 |
20100013789 | Touch control liquid crystal display array substrate and a liquid crystal display - A touch control liquid crystal display includes an array substrate which comprises scan lines, data lines perpendicular to the scan lines and further defining a pixel area, a pixel electrode formed in the pixel area, a storage capacitor electrode forming a first storage capacitor with the pixel electrode, a first switching element through which the data line inputs data signals to the pixel electrode, a signal detecting line, a touch control electrode forming a second storage capacitor with the storage capacitor line, a second switching element through which the signal detecting line inputs or outputs a voltage signal to the touch control electrode, a converter for controlling the output or input of the voltage signal on the signal detecting line. | 01-21-2010 |
Patent application number | Description | Published |
20090295694 | Liquid Crystal Display and Array Substrate Thereof - The present invention provides a liquid crystal display and an array substrate thereof The array substrate comprises scan lines, data lines and a plurality of pixel defined by a crosswise arrangement of the scan lines and the data lines. The pixel comprises a first sub-pixel electrode; a second sub-pixel electrode electrically isolated from the first sub-pixel electrode; a first switching element for controlling the first sub-pixel electrode; and a second switching element for controlling the second sub-pixel electrode. When the control of the first sub-pixel electrode by the first switching element cannot be carried out normally, the second switching element can control at least a part of the first sub-pixel electrode in place of the first switching element. | 12-03-2009 |
20090322660 | LIQUID CRYSTAL PANEL, LIQUID CRYSTAL DISPLAY, AND DRIVING METHOD THEREOF - A liquid crystal panel, a liquid crystal display, and a driving method thereof are disclosed. The liquid crystal panel comprises scanning lines, data lines, and a plurality of pixels, each of the plurality of pixels including a TFT, a pixel electrode, a first common electrode, and a second common electrode. The first common electrodes of first pixels of the plurality of pixels are electrically connected via a first common line, the first common electrodes of second pixels of the plurality of pixels are electrically connected via a second common line, and the second common electrodes of the plurality of pixels are electrically connected. | 12-31-2009 |
20090322977 | Array Substrate of Liquid Crystal Display - An array substrate of a liquid crystal display, comprising a first scan line and a second scan line, a first data line and a second data line arranged crossing with the first scan line and the second scan line to define a pixel region, and a pixel electrode in the pixel region, wherein the second data line comprises at least a first branch and a second branch that are electrically connected to each other. According to the invention, it is not necessary to provide the array substrate with additional space for disposing repair lines, and the non-display region is therefore not increased, resulting in an increased yield. Only a short length of repair lines is used in repair, and thus both electrical resistance of repair line and distortion of data signals can be reduced. | 12-31-2009 |
20100066383 | ARRAY SUBSTRATE AND DEFECT-DETECTING METHOD THEREOF - The present invention discloses an array substrate and a defect detecting method thereof. The array substrate comprises one or more shorting bars for applying signals to a plurality of data lines or a plurality of gate lines of the array substrate while testing. The array substrate further comprises a line detecting circuit for receiving signals on the plurality of data lines or the plurality of gate lines, and detecting and locating the line defects of the plurality of data lines or the plurality of gate lines. The array substrate and the defect detecting method thereof provided by the invention can locate the line defects of the array substrate accurately and quickly. | 03-18-2010 |