Chitnis, CA
Ashay Chitnis, Goleta, CA US
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20080284541 | Bulk acoustic device and method for fabricating - A method for fabricating a bulk acoustic wave (BAW) device comprising providing a growth substrate and growing an Group-III nitride epitaxial layer on the growth substrate. A first electrode is deposited on the epitaxial layer. A carrier substrate is provided and the growth substrate, epitaxial layer and first electrode combination is flip-chip mounted on the carrier substrate. The growth substrate is removed and a second electrode is deposited on the epitaxial layer with the epitaxial layer sandwiched between the first and second electrodes. A bulk acoustic wave (BAW) device comprises first and second metal electrodes and a Group-III nitride epitaxial layer sandwiched between the first and second electrodes. A carrier substrate is included, with the first and second electrodes and epitaxial layer on the carrier substrate. | 11-20-2008 |
20090050903 | Selective wet etching of gold-tin based solder - The present invention is directed to post-deposition, wet etch processes for patterning AuSn solder material and devices fabricated using such processes. The processes can be applied to uniform AuSn layers to generate submicron patterning of thin AuSn layers having a wide variety of features. The use of multiple etching steps that alternate between different mixes of chemicals enables the etch to proceed effectively, and the same or similar processes can be used to etch under bump metallization. The processes are simple, cost-effective, do not contaminate equipment or tools, and are compatible with standard cleanroom fabrication processes. | 02-26-2009 |
20090121241 | Wire bond free wafer level LED - A wire-bond free semiconductor device with two electrodes both of which are accessible from the bottom side of the device. The device is fabricated with two electrodes that are electrically connected to the oppositely doped epitaxial layers, each of these electrodes having leads with bottom-side access points. This structure allows the device to be biased with an external voltage/current source, obviating the need for wire-bonds or other such connection mechanisms that must be formed at the packaging level. Thus, features that are traditionally added to the device at the packaging level (e.g., phosphor layers or encapsulants) may be included in the wafer level fabrication process. Additionally, the bottom-side electrodes are thick enough to provide primary structural support to the device, eliminating the need to leave the growth substrate as part of the finished device. | 05-14-2009 |
20100224890 | Light emitting diode chip with electrical insulation element - A light emitting diode chip comprising a light emitting diode and a thermally conductive substrate. The light emitting diode is on the substrate with the substrate providing a thermal path from the light emitting diode through the substrate. A mounting pad is also on a substrate and an electrically insulating layer is integral to the substrate. The insulating layer electrically insulates the mounting pad from the light emitting diode. A method for fabricating a light emitting diode chip comprises providing a thermally conductive substrate, forming an electrical insulating layer integral to the substrate and forming a mounting pad on the substrate. A light emitting diode is fabricated and mounted to the substrate, with the light emitting diode electrically insulated from the mounting pad by the electrically insulating layer. | 09-09-2010 |
Ashay Chitnis, Santa Barbara, CA US
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20090065790 | LED chips having fluorescent substrates with microholes and methods for fabricating - Methods for fabricating semiconductor devices such as LED chips at the wafer level, and LED chips and LED chip wafers fabricated using the methods. An LED chip wafer according to the present invention comprises a plurality of LEDs on a wafer and a plurality of pedestals, each of which is on one of the LEDs. A fluorescent substrate or preform (“preform”) is provided covering at least some of the LEDs, the preform comprising holes with the pedestals arranged within the holes. During operation of the covered ones of said LEDs at least some light from the LEDs passes through the preform and is converted. LED chips are provided that are singulated from this LED chip wafer. One embodiment of a method for fabricating LED chips from a wafer comprises depositing LED epitaxial layers on an LED growth wafer to form a plurality of LEDs on the growth wafer. Pedestals are formed on the LEDs and a fluorescent preform is formed with holes. The fluorescent preform is bonded over at least some of the plurality of LEDs so that at least some light from the covered ones of said LEDs passes through the preform and is converted. The pedestals are arranged in the holes so that an electrical signal is applied to the LEDs through the pedestals. | 03-12-2009 |
20090261358 | EMISSION TUNING METHODS AND DEVICES FABRICATED UTILIZING METHODS - A method for fabricating light emitting diode (LED) chips comprising providing a plurality of LEDs, typically on a wafer, and coating the LEDs with a conversion material so that at least some light from the LEDs passes through the conversion material and is converted. The light emission from the LED chips comprises light from the conversion material, typically in combination with LED light. The emission characteristics of at least some of the LED chips is measured and at least some of the conversion material over the LEDs is removed to alter the emission characteristics of the LED chips. The invention is particularly applicable to fabricating LED chips on a wafer where the LED chips have light emission characteristics that are within a range of target emission characteristics. This target range can fall within an emission region on a CIE curve to reduce the need for binning of the LEDs from the wafer. The emission characteristics of the LED chips in the wafer can be tuned to the desired range by micro-machining the conversion material over the LEDs. | 10-22-2009 |
Devraj Chitnis, San Jose, CA US
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20120203891 | NETFLIX IN A BOX - One embodiment of the present invention sets forth a technique for testing a client for audio/video/subtitle playback capabilities. A computing device is configured to receive a virtual machine data file that includes an operating system, a web server, a content playback application, and a test program. The virtual machine data file is executed to cause the operating system and web server to initialize. The web server detects a communications connection to the client, transmits the content playback application to the client for execution, and transmits one or more tests included in the test program to test the audio/video playback capabilities of the client. The computing device is further configured to receive, from the client via the web server, test results associated with the one or more tests, and to store the test results in a memory. | 08-09-2012 |
Laukik Vilas Chitnis, Sunnyvale, CA US
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20150088648 | DETERMINING COMMERCIAL INTENT - Methods, systems, and apparatus, including computer programs encoded on a computer-readable storage medium, for providing content. A query is received that includes a plurality of terms or phrases. Entities associated with the plurality of terms or phrases are identified. For each identified entity, one or more collections of entities are determined. A determined collection of entities includes a respective identified entity as a member. A commercial intent of a user that submitted the query is determined, including evaluating the determined one or more collections of entities. Based on the determined commercial intent, a decision is made when to deliver additional content items along with search results that are responsive to the query. | 03-26-2015 |
Mandar Chitnis, Pleasanton, CA US
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20100318954 | MANAGING AND CONTROLLING THE USE OF HARDWARE RESOURCES ON INTEGRATED CIRCUITS - Disclosed herein are representative embodiments of methods and apparatus for managing and allocating hardware resources during RTL synthesis. For example, in one exemplary method disclosed herein, an RTL description of a circuit to be implemented in a target architecture is received. The target architecture of this embodiment comprises a fixed number of hardware resources in a class of hardware resources. One or more operator instances are determined from the RTL description received, where at least some of the operator instances are implementable by the hardware resources in the class of hardware resources. In this embodiment, and prior to initially synthesizing the RTL description into a gate-level netlist, assignment information indicative of how the operator instances are to be implemented using the hardware resources in the class of hardware resources is automatically determined. A graphical user interface is also provided that allows a user to view and modify the assignment information. | 12-16-2010 |
20140317583 | MANAGING AND CONTROLLING THE USE OF HARDWARE RESOURCES ON INTEGRATED CIRCUITS - Disclosed herein are representative embodiments of methods and apparatus for managing and allocating hardware resources during RTL synthesis. For example, in one exemplary method disclosed herein, an RTL description of a circuit to be implemented in a target architecture is received. The target architecture of this embodiment comprises a fixed number of hardware resources in a class of hardware resources. One or more operator instances are determined from the RTL description received, where at least some of the operator instances are implementable by the hardware resources in the class of hardware resources. In this embodiment, and prior to initially synthesizing the RTL description into a gate-level netlist, assignment information indicative of how the operator instances are to be implemented using the hardware resources in the class of hardware resources is automatically determined. A graphical user interface is also provided that allows a user to view and modify the assignment information. | 10-23-2014 |
Samir A. Chitnis, Santa Clara, CA US
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20150121041 | PROCESSOR AND METHODS FOR IMMEDIATE HANDLING AND FLAG HANDLING - Described herein are methods and processors for flag renaming in groups to eliminate dependencies of instructions. Decoder and execution units in the processor may be configured to rename flags into groups that allow each group to be treated separately as appropriate. This flag renaming eliminates flag dependencies with respect to instructions. This allows an instruction to write exactly the flags that the instruction wants without having to create merge dependencies. Methods and processors are provided for handling immediate values embedded in instructions. A 16 bit immediate bus and a 4 bit encoding/control bus are added at the interface between decode and execution units. For an 8 or 12 bit immediate, the upper 4 bits of the immediate bus contain the encoding bits. For a 16 bit immediate, the encoding/control bus contains the encoding bits. The encoding/control bus indicates when to look at the top four bits of the immediate bus. | 04-30-2015 |
Siddharth D. Chitnis, San Diego, CA US
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20130094471 | SYSTEM AND METHOD FOR MINIMIZING LOSS OF IP CONTEXT DURING IRAT HANDOVER - A method for maintaining IP context during an inter RAT handover of a UE between an eHRPD network and an LTE network may include delaying a transfer of an Internet Protocol context for at least one active packet data network until an IP address for an attach (PDN) Packet Data Network has been assigned and in the case where the Internet Protocol address for the Attach Packet Data Network is not assigned, initiating a detach operation from the LTE network without the user equipment losing the Internet Protocol context of the at least one active Packet Data Network. | 04-18-2013 |
Sidharth D. Chitnis, San Diego, CA US
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20120320733 | REDUCING EVOLVED PACKET CORE INTERNET PROTOCOL SERVICE DISCONNECTS DURING INTER-RADIO ACCESS TECHNOLOGY HANDOVER - During inter-radio access technology (IRAT) handover between LTE and eHRPD technologies, Internet protocol (IP) service continuity at a user equipment (UE) may be maintained. Thus, a method, an apparatus, and a computer program product are provided for maintaining the IP service continuity during IRAT handover from an SRAT to a TRAT within an evolved packet core (EPC)—capable region. The apparatus attempts to transfer an EPC context to a TRAT, determines that a failure occurs when attempting to transfer the EPC context to the TRAT, and attempts to maintain at least one IP service continuity within the EPC context according to the failure. The attempt to maintain may include an attempt to maintain an entire EPC context or a set of parameters including at least one of an IP address, a domain name system (DNS) address, a proxy call session control function (P-CSCF) address, or a quality of service (QoS). | 12-20-2012 |
Smita Chitnis, San Diego, CA US
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20120046178 | PRODUCTS AND PROCESSES FOR MULTIPLEX NUCLEIC ACID IDENTIFICATION - Provided herein are products and processes for detecting the presence or absence of multiple target nucleic acids. Certain methods include amplifying the target nucleic acids, or portion thereof; extending oligonucleotides that specifically hybridize to the amplicons, where the oligonucleotides include distinguishable labels and a capture agent; capturing the extended oligonucleotides to a solid phase via the capture agent; releasing and detecting the distinguishable label, and thereby determining the presence or absence of each target nucleic acid by the presence or absence of the distinguishable label. | 02-23-2012 |
20130189678 | MACROPHAGE MIGRATION INHIBITORY FACTOR (MIF) PROMOTER POLYMORPHISM IN INFLAMMATORY DISEASE - Describe herein is a novel CATT-tetranucleotide repeat polymorphism at position −817 of the human Mif that functionally affects the activity of the Macrophage Inhibitory Factor (MIF) promoter in gene reporter assays. Four genotypes are described which comprise 5, 6, 7, or 8-CATT repeat units. Of these, the 5-CATT allele has the lowest level of basal and stimulated MIF promoter activity in vitro. The presence of the low expressing, 5-CATT repeat allele correlated with low disease severity in a cohort of rheumatoid arthritis patients. Methods, compositions and apparatus for detecting this CATT-tetranucleotide repeat polymorphism at position −817 of the human Mif gene, and for using same for assessing predisposition to severe inflammatory disease, are also disclosed. | 07-25-2013 |
Sunil P. Chitnis, San Jose, CA US
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20100023618 | SYSTEM AND METHOD FOR SUPPLICANT BASED ACCOUNTING AND ACCESS - The method of the present invention comprises initiating a connection to a port on an access device by a supplicant and associating supplicant identification information with the port. The access device may comprise any network connectivity device, including a wireless access point. Data packets transmitted over the port by the supplicant are statistically sampled as they are transmitted, with each of the sample data packets also associated with the supplicant identification information. The sample data packets are stored according to their associated supplicant identification information in order to perform accounting. The sample data packets, with the supplicant identification information, are sent to a network management system where the data is archived and presented in a human readable form, e.g., charts, etc. | 01-28-2010 |