Patent application number | Description | Published |
20080206701 | RECONFIGURABLE DENTAL MODEL SYSTEM FOR FABRICATION OF DENTAL APPLIANCES - The present invention provides a manipulable or reconfigurable dental model system and methods for its use to model a series of tooth configurations corresponding to sequential tooth movements during an orthodontic treatment. When a patient undergoes orthodontic treatment, teeth and bite configurations are realigned in a series of stages. Each stage represents a new pattern or dental configuration that will eventually lead to a proper final positioning of the entire dentition. Progress from the initial configuration, through the intermediate stages and finally to the final configuration may be accomplished using any one or a combination of different dental appliances. Of particular interest to the present invention, many of these appliances may be made using a dental mold representing the patient's dental configuration. In particular, thermoformable plastic positioning appliances which fit over the patient's teeth may be formed over a three-dimensional mold of the patient's dentition. When successive appliances are used throughout treatment to reposition the teeth from initial to final configuration, a new mold has typically been produced to fabricate the appliance for each stage. The present invention provides an apparatus and methods which employ a manipulable or reconfigurable mold to model patient dentition and gingiva at each stage of treatment. | 08-28-2008 |
20080248443 | Clinician review of an orthodontic treatment plan and appliance - A computer is used to create a plan for repositioning an orthodontic patient's teeth. The computer receives an initial digital data set representing the patient's teeth at their initial positions and a final digital data set representing the teeth at their final positions. The computer then uses the data sets to generate treatment paths along which teeth will move from the initial positions to the final positions. | 10-09-2008 |
20090292556 | METHOD AND SYSTEM FOR DISTRIBUTING PATIENT REFERRALS - Practitioners are certified to perform a medical procedure, such as an orthodontic procedure. Certified practitioners are maintained in a referral directory and classified within tiers based on criteria such as the number of procedures that they have performed. Inquiries are solicited from prospective patients, and referral lists are provided to those patients who request them. The referral lists are obtained from the referral directory with doctors from higher tiers who have performed more procedures receiving preferential inclusion on the referral lists. | 11-26-2009 |
20120244488 | COMPUTER AUTOMATED DEVELOPMENT OF AN ORTHODONTIC TREATMENT PLAN AND APPLIANCE - A computer is used to create a plan for repositioning an orthodontic patient's teeth. The computer receives an initial digital data set representing the patient's teeth at their initial positions and a final digital data set representing the teeth at their final positions. The computer then uses the data sets to generate treatment paths along which the teeth will move from the initial positions to the final positions. | 09-27-2012 |
Patent application number | Description | Published |
20110184762 | CLINICIAN REVIEW OF AN ORTHODONTIC TREATMENT PLAN AND APPLIANCE - A computer is used to create a plan for repositioning an orthodontic patient's teeth. The computer receives an initial digital data set representing the patient's teeth at their initial positions and a final digital data set representing the teeth at their final positions. The computer then uses the data sets to generate treatment paths along which teeth will move from the initial positions to the final positions. | 07-28-2011 |
20120225400 | SYSTEM AND METHOD FOR POSITIONING TEETH - Methods and apparatus fit a set of upper and lower teeth in a masticatory system by generating a computer representation of the masticatory system and computing an occlusion based on interactions in the computer representation of the masticatory system. | 09-06-2012 |
20130085721 | SYSTEM AND METHOD FOR POSITIONING TEETH - Methods and apparatus fit a set of upper and lower teeth in a masticatory system by generating a computer representation of the masticatory system and computing an occlusion based on interactions in the computer representation of the masticatory system. | 04-04-2013 |
20130191142 | METHOD AND SYSTEM FOR DISTRIBUTING PATIENT REFERRALS - Practitioners are certified to perform a medical procedure, such as an orthodontic procedure. Certified practitioners are maintained in a referral directory and classified within tiers based on criteria such as the number of procedures that they have performed. Inquiries are solicited from prospective patients, and referral lists are provided to those patients who request them. The referral lists are obtained from the referral directory with doctors from higher tiers who have performed more procedures receiving preferential inclusion on the referral lists. | 07-25-2013 |
20130302743 | COMPUTER AUTOMATED DEVELOPMENT OF AN ORTHODONTIC TREATMENT PLAN AND APPLIANCE - A computer is used to create a plan for repositioning an orthodontic patient's teeth. The computer receives an initial digital data set representing the patient's teeth at their initial positions and a final digital data set representing the teeth at their final positions. The computer then uses the data sets to generate treatment paths along which the teeth will move from the initial positions to the final positions. | 11-14-2013 |
20140108036 | METHOD AND SYSTEM FOR DISTRIBUTING PATIENT REFERRALS - Practitioners are certified to perform a medical procedure, such as an orthodontic procedure. Certified practitioners are maintained in a referral directory and classified within tiers based on criteria such as the number of procedures that they have performed. Inquiries are solicited from prospective patients, and referral lists are provided to those patients who request them. The referral lists are obtained from the referral directory with doctors from higher tiers who have performed more procedures receiving preferential inclusion on the referral lists. | 04-17-2014 |
20140180463 | COMPUTER AUTOMATED DEVELOPMENT OF AN ORTHODONTIC TREATMENT PLAN AND APPLIANCE - A computer is used to create a plan for repositioning an orthodontic patient's teeth. The computer receives an initial digital data set representing the patient's teeth at their initial positions and a final digital data set representing the teeth at their final positions. The computer then uses the data sets to generate treatment paths along which the teeth will move from the initial positions to the final positions. | 06-26-2014 |
20140288894 | CLINICIAN REVIEW OF AN ORTHODONTIC TREATMENT PLAN AND APPLIANCE - A computer is used to create a plan for repositioning an orthodontic patient's teeth. The computer receives an initial digital data set representing the patient's teeth at their initial positions and a final digital data set representing the teeth at their final positions. The computer then uses the data sets to generate treatment paths along which teeth will move from the initial positions to the final positions. | 09-25-2014 |
20140349242 | SYSTEMS AND METHODS FOR VARYING ELASTIC MODULUS APPLIANCES - The present invention provides improved devices, systems and methods for repositioning teeth from an initial tooth arrangement to a final tooth arrangement. Repositioning is accomplished with a system comprising a series of polymeric shell appliances configured to receive the teeth and incrementally reposition individual teeth in a series of successive steps. The individual appliances may be formed from layers having different stiffnesses (elastic moduluses), and the stiffnesses of successive appliances may be different, or both. | 11-27-2014 |
Patent application number | Description | Published |
20100146368 | PERFORMING MULTI-BIT ERROR CORRECTION ON A CACHE LINE - A processor may comprise a cache, which may be divided into a first and second section while the processor operates in a low-power mode. A cache line of the first section may be fragmented into segments. A first encoder may generate first data bits and check bits while encoding a first portion of a data stream and a second encoder may, separately, generate second data bits and check bits while encoding a second portion of the data stream. The first data bits may be stored in a first segment of the first section and the check bits in a first portion of the second section that is associated with the first segment. The first decoder may correct errors in multiple bit positions within the first data bits using the check bits stored in the first portion and the second decoder may, separately, decode the second data bits using the second set of check bits. | 06-10-2010 |
20110078340 | VIRTUAL ROW BUFFERS FOR USE WITH RANDOM ACCESS MEMORY - Methods, apparatuses and systems to decrease the energy consumption of a memory chip while increasing its effect bandwidth during the execution of any workload. Methods, apparatuses and systems may allow a memory chip utilize a plurality of virtual row buffers to respond to requests for data included in a memory array block. Methods, apparatuses and systems may further eliminate or reduce the cost associated with transferring unnecessary data from a memory array block to row buffers by altering the data transfer size between a memory array block and a row buffer. | 03-31-2011 |
20110088041 | Hardware support for thread scheduling on multi-core processors - A method, device, and system are disclosed. In one embodiment the method includes scheduling a thread to run on first core of a multi-core processor. The determination as to which core the thread is scheduled on uses one or more processes. These processes may include ranking all of the cores specific to a workload of the thread, establishing a current utilization of each core of the multi-core processor, and calculating an inter-core migration cost for the thread. | 04-14-2011 |
20110289380 | METHOD AND APPARATUS FOR USING CACHE MEMORY IN A SYSTEM THAT SUPPORTS A LOW POWER STATE - A cache memory system is provided that uses multi-bit Error Correcting Code (ECC) with a low storage and complexity overhead. The cache memory system can be operated at very low idle power, without dramatically increasing transition latency to and from an idle power state due to loss of state. | 11-24-2011 |
20120102270 | Methods and Apparatuses for Idle-Prioritized Memory Ranks - Embodiments of an apparatus to reduce memory power consumption are presented. In one embodiment, the apparatus comprises a cache memory, a memory, and a control unit. In one embodiment, the memory includes a plurality of memory ranks. The control unit is operable to select one or more memory ranks among the plurality of memory ranks to be idle-prioritized memory ranks such that access frequency to the idle-prioritized memory ranks is reduced. | 04-26-2012 |
20140173206 | Power Gating A Portion Of A Cache Memory - In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed. | 06-19-2014 |
20140173207 | Power Gating A Portion Of A Cache Memory - In an embodiment, a processor includes multiple tiles, each including a core and a tile cache hierarchy. This tile cache hierarchy includes a first level cache, a mid-level cache (MLC) and a last level cache (LLC), and each of these caches is private to the tile. A controller coupled to the tiles includes a cache power control logic to receive utilization information regarding the core and the tile cache hierarchy of a tile and to cause the LLC of the tile to be independently power gated, based at least in part on this information. Other embodiments are described and claimed. | 06-19-2014 |
20140380019 | SYSTEMS AND METHODS FOR MANAGING RECONFIGURABLE PROCESSOR CORES - Systems and methods for managing reconfigurable processor cores. An example processing system comprises a plurality of processor cores; a control register including a plurality of state bits, each state bit indicating a state of a corresponding processor core, the control register further including a plurality of inhibit bits, each inhibit bit indicating whether a corresponding processor core is allowed to merge with other processor cores; and a core management logic configured to merge a first processor core and a second processor core, responsive to determining that a first state bit corresponding to the first processor core is set, a first inhibit bit corresponding to the first processor core is cleared, a second state bit corresponding to the second processor core is cleared, and a second inhibit bit corresponding to the second processor core is cleared. | 12-25-2014 |
20150067259 | MANAGING SHARED CACHE BY MULTI-CORE PROCESSOR - Systems and methods for managing shared cache by multi-core processor. An example processing system comprises: a plurality of processing cores, each processing core communicatively coupled to a last level cache (LLC) slice; and a cache control logic coupled to the plurality of processing cores, the cache control logic configured to perform one of: making an LLC slice of an inactive processing core available to an active processing core or power gating the LLC slice, based on estimating cache requirements by active processing cores. | 03-05-2015 |
20150095918 | SYSTEM AND METHOD FOR THREAD SCHEDULING ON RECONFIGURABLE PROCESSOR CORES - Systems and methods for efficiently utilizing reconfigurable processor cores. An example processing system includes, for example, a control register comprising a plurality of inhibit bits, each inhibit bit indicating whether a corresponding processor core is allowed to merge with other processor cores; and dynamic core reallocation logic to temporarily merge a first processor core and a second processor core to speed execution of a first thread executed on the first processor core responsive to determining that a second thread executed on the second processor core has completed execution prior to a quantum associated with the second thread being reached and to determining that the inhibit bits indicate that the first and second cores may be merged. | 04-02-2015 |
20150149714 | CONSTRAINING PREFETCH REQUESTS TO A PROCESSOR SOCKET - In an embodiment, a processor includes at least one core having one or more execution units, a first cache memory and a first cache control logic. The first cache control logic may be configured to generate a first prefetch request to prefetch first data, where this request is to be aborted if the first data is not present in a second cache memory coupled to the first cache memory. Other embodiments are described and claimed. | 05-28-2015 |
20150278091 | METHOD AND APPARATUS FOR IMPLEMENTING A HETEROGENEOUS MEMORY SUBSYSTEM - An apparatus and method for implementing a heterogeneous memory subsystem is described. For example, one embodiment of a processor comprises: memory mapping logic to subdivide a system memory space into a plurality of memory chunks and to map the memory chunks across a first memory and a second memory, the first memory having a first set of memory access characteristics and the second memory having a second set of memory access characteristics different from the first set of memory access characteristics; and dynamic remapping logic to swap memory chunks between the first and second memories based, at least in part, on a detected frequency with which the memory chunks are accessed. | 10-01-2015 |