Patent application number | Description | Published |
20090267202 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a semiconductor chip, a number of pads, a number of lead bars and an encapsulation material. The semiconductor chip has an upper surface and an opposite bottom surface. Area of the upper surface exceeds that of the bottom surface. The pads are mounted on the upper surface of the semiconductor chip. The lead bars are located around the semiconductor chip and electrically connected with corresponding pads. The encapsulation material covers the semiconductor chip, the pads, the lead bars and the bonding wires. | 10-29-2009 |
20100221412 | METHOD FOR MANUFACTURING A SUBSTRATE - In a method for manufacturing a substrate, copper is applied to one surface of the substrate to form a plurality of circuit traces, defining one or more copper clearance areas therebetween. Dry film is coated on one portion of the circuit traces and the one or more copper clearance areas, and another portion of the plurality of copper traces remains uncoated. The dry film on the substrate is flattened to form a dry film layer. The other portion of the plurality of circuit traces is plated to form a plating layer. A surface of the plating layer is substantially coplanar with a surface of the dry film layer. | 09-02-2010 |
20100230826 | INTEGRATED CIRCUIT PACKAGE ASSEMBLY AND PACKAGING METHOD THEREOF - An integrated circuit (IC) package assembly includes a substrate including a plurality of golden fingers, a bonding pad integrally formed with the substrate, an IC fixed on the bonding pad, and a plurality of bonding wires. The IC includes a plurality of connecting pads. A width and a length of the IC are greater than a width and a length of the bonding pad. The plurality of bonding wires electrically connect the plurality of connecting pads to the plurality of golden fingers. | 09-16-2010 |
20100264535 | INTEGRATED CIRCUIT PACKAGE ASSEMBLY AND SUBSTRATE PROCESSING METHOD - An integrated circuit (IC) package assembly includes a substrate and an IC. The substrate defines a plurality of vias. Inner walls of the plurality of vias and surfaces of the substrate are coated with copper. The plurality of vias are filled with an adhesive. The copper coated on surfaces of the substrate among the plurality of vias are etched. The IC is fixed on the substrate by cohesion between the adhesive and the etched surfaces of the substrate. | 10-21-2010 |
20100273297 | CHIP PACKAGING METHOD - In a method for mounting a chip on a substrate, a plurality of grooves are defined in the substrate. A plurality of pads are formed in the grooves. A height of each of the plurality of pads is less than a depth of each corresponding groove. The chip configured with a plurality of soldering balls is positioned on the substrate with the plurality of soldering balls being received in the plurality of grooves and contacting the plurality of pads respectively. The chip is mounted onto the substrate by a melting process. | 10-28-2010 |
20100295163 | STACKED SEMICONDUCTOR PACKAGE ASSEMBLY - A stacked package assembly includes N (where N≧2) package bodies stacked together. Each package body is made up of a substrate which comprises a top surface and a bottom surface, and a chip packaged in the substrate. The top surface of the substrate of each package body includes (N−1) pads, and the bottom surface includes N pads. The Kth pad on the top surface of the substrate of each package body is electrically connected to the (K+1)th pad on the bottom surface thereof. The Kth (K=1, 2, . . . , (N−1)) pad on the top surface of the substrate of one lower package body corresponds to the Kth pad on the bottom surface of the substrate of another upper package body stacked above the lower package body. | 11-25-2010 |
20100327425 | FLAT CHIP PACKAGE AND FABRICATION METHOD THEREOF - A flat chip package comprises an encapsulation body, a plurality of connecting fingers, a plurality of conductive lines, a chip, a plurality of bond wires and an insulation layer. The conductive lines, the chip, and the bond wires are encapsulated in the encapsulation body. The connecting fingers comprise a ground finger, a power finger and at least one signal finger. One side of the connecting fingers adheres to a surface of the encapsulation body, the other side of the connecting fingers is left exposed. The conductive lines comprise a ground line connected to the ground finger, and a power line connected to the power finger. The chip comprises a ground pin, a power pin and at least one signal pin. The bond wires connect the connecting fingers, the conductive lines and the chip. The insulation layer is printed on the surface of the encapsulation body except for the connecting fingers. | 12-30-2010 |
20110096223 | CAMERA MODULE AND MANUFACTURING METHOD THEREOF - A camera module includes an image sensor, a first substrate, a lens, a second substrate, and a light shading cover. The first substrate includes a first surface and a second surface opposite to the first surface. The first substrate defines a first aperture. The image sensor is attached to the first surface. The lens is attached to the second surface. The second substrate is attached to a surface of the lens away from the first substrate. The second substrate defines a second aperture. The light shading cover defines a third aperture. The light shading cover is covered on the second substrate and defining a third aperture coaxial to the first aperture . The center of the first aperture, the second aperture, and the third aperture are located on the optical axis of the camera module. | 04-28-2011 |