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Ching-Wei
Ching-Wei Chang, Pa-Te City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090174605 | MODULAR ULTRA-WIDEBAND ANTENNA STRUCTURE - An ultra-wideband (UWB) modular antenna structure, it mainly has a radio-frequency module and an antenna unit combined to be suitable of assembling in a system of electronic equipment. The radio-frequency module is installed on a printed circuit board of the electronic equipment, and has at least a radio-frequency module circuit board; the antenna unit is installed above the radio-frequency module circuit board, and has a dual-face printed circuit board on the top of which a radiation member of an operation range of frequency band for ultra-wideband communication is formed with a feed-in portion extended out of it, the bottom face has a grounding portion extended out of it, the feed-in portion and the grounding portion are connected respectively to the radio-frequency module circuit board. Thereby, functions of mass production and volume reducing can be obtained, so that no instability issue may happen during installation and changing. | 07-09-2009 |
| 20110285594 | SUPPER-BROADBAND ANTENNA STRUCTURE - A supper-broadband antenna structure designed with a specific coplanar waveguide (CPW) mode to make its covering range of frequency be in a range of about 300 MHz˜9 GHz., of which the covering range of frequency is in a range of 300 MHz˜9 GHz having a rational efficiency of above 40% within the range of frequency band, and the return loss is better than the value −5 dB. The structure of a single supper-broadband antenna designed according to the present invention can be applied to many usages easily and accurately, e.g., for checking chamber stability, chamber to chamber verification etc. | 11-24-2011 |
Ching-Wei Chang, Tu-Cheng TW
| Patent application number | Description | Published |
|---|---|---|
| 20090318118 | SYSTEM AND METHOD FOR MANAGING MISSED CALLS AND UNREAD MESSAGES - A method and system for reporting missed calls and unread messages include setting a report function in a predetermined communication device, determining if the predetermined communication device receives a short message, which is substantially the same as a preset short message service (SMS) command. The method and the system further include invoking the report function to send unread short message and a list of missed calls of the predetermined communication device if the predetermined communication device receives a short message being substantially the same as the preset SMS command. | 12-24-2009 |
Ching-Wei Chen, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110049565 | OPTOELECTRONIC DEVICE AND PROCESS FOR MAKING SAME - The present invention discloses an optoelectronic device, comprising: a substrate made of a first material; a region in the substrate, the region being made of a second material different from the first material; and a photo diode formed in the region by ion implantation. The second material for example is silicon germanium (Si1-xGex) or silicon carbide (Si1-yCy), wherein 0| 03-03-2011 | |
Ching-Wei Hung, Hukou Shiang TW
| Patent application number | Description | Published |
|---|---|---|
| 20090236732 | THERMALLY-ENHANCED MULTI-HOLE SEMICONDUCTOR PACKAGE - A thermal-enhanced multi-hole semiconductor package is revealed, primarily comprising a substrate with a plurality of alignment holes, a chip disposed on the substrate, an internal heat sink attached to the chip, and an encapsulant. The internal hear sink has a plurality of alignment bars and a heat dissipation surface. The alignment bars are inserted into the alignment holes, but not fully occupying the alignment holes to provide a plurality of flowing channels therein. The encapsulant completely encapsulates the alignment bars through filling the flowing channels. Therefore, the internal heat sink can be aligned to the substrate and is integrally connected with the chip and the substrate utilizing a small amount of adhesive or without any adhesive to form a composite having high rigidity and strong adhesion. | 09-24-2009 |
Ching-Wei Hung, Hukou TW
| Patent application number | Description | Published |
|---|---|---|
| 20100147565 | WINDOW BALL GRID ARRAY SUBSTRATE AND ITS PACKAGE STRUCTURE - A window ball grid array substrate and its package structure includes a package substrate with a long slot arranged thereon, wherein the improvement is characterized by the long slot penetrating an end of the package substrate making the package substrate appear to be U-shaped. | 06-17-2010 |
Ching-Wei Lin, Tao-Yuan Hsien TW
| Patent application number | Description | Published |
|---|---|---|
| 20100110060 | SYSTEMS AND METHODS FOR GENERATING REFERENCE VOLTAGES - Systems and methods for generating reference voltages are provided. A representative system comprises a resistor circuit; a first switch coupled between a first end of the resistor circuit and a first power source; a second switch coupled between the first end of the resistor circuit and a second power source; a third switch coupled to a second end of the resistor circuit; a fourth switch coupled to the second end of the resistor circuit; a first resistor coupled between the first end of the resistor circuit and the first switch; a second resistor coupled between the first end of the resistor circuit and the second switch; a third resistor coupled between the second end of the resistor circuit and the third switch; a fourth resistor coupled between the second end of the resistor circuit and the fourth switch; and a control circuit for controlling the switches. | 05-06-2010 |
Ching-Wei Lin, Taichung TW
| Patent application number | Description | Published |
|---|---|---|
| 20080302677 | BEVERAGE CARTON - A one-piece beverage carton has two handle panels, two side panels, two fascia panels, a primary bottom panel, a secondary bottom panel and two side bottom panels. The handle panels abut each other and have hand holes formed therethrough. The side panels are formed adjacent to the handle panels and each side panel has a structural strip and two folding strips being shorter than, formed on and folding along opposite edges of the structural strip. The fascia panels have a top edge and are connected to the handle panels by at two partitions formed on and folded against the fascia and handle panels. The bottom panels are formed on and folded against the fascia and side panels to form a bottom of the carton. The beverage carton therefore creates less material waste, is strong and easily folded for storage and transportation. | 12-11-2008 |
Ching-Wei Liu, Taipei TW
| Patent application number | Description | Published |
|---|---|---|
| 20100267949 | Method of Synthesizing 6,7-Substituted 4-Anilino Quinazoline - A method of synthesizing 6,7-substituted 4-anilino quinazoline employs 3,4-substituted benzoic acid as an initial reactant, and the 6,7-substituted 4-anilino quinazoline is obtained by an esterifying step, a nitrating step, a reducing step, a cyclizing step, and an one-pot reaction. In the above method, the initial reactant has low cost and yield. of the 6,7-substituted 4-anilino quinazoline is high, therefore, production cost can be reduced effectively, and competitive power of the product of the 6,7-substituted 4-anilino quinazoline can be improved. | 10-21-2010 |
Ching-Wei Tsai, Taoyuan City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080237750 | Silicided metal gate for multi-threshold voltage configuration - A PMOS (p-channel metal oxide semiconductor) device having at low voltage threshold MOSFET (MOS field effect transistor) with an improved work function and favorable DIBL (drain-induced barrier lowering) and SCE (short channel effect) characteristics, and a method for making such a device. The PMOS device includes a gate structure that is disposed on a substrate and includes a silicided gate electrode. The silicide is preferably nickel-rich and includes a peak platinum concentration at or near the interface between the gate electrode and a dielectric layer that separates the gate electrode from the substrate. The platinum peak region is produced by a multi-step rapid thermal annealing or similar process. The PMOS device may also include two such MOSFETs, one of which is boron-doped and one of which is not. | 10-02-2008 |
| 20090090935 | High Performance CMOS Device Design - A semiconductor device includes a gate, which comprises a gate electrode and a gate dielectric underlying the gate electrode, a spacer formed on a sidewall of the gate electrode and the gate dielectric, a buffer layer having a first portion underlying the gate dielectric and the spacer and a second portion adjacent the spacer wherein the top surface of the second portion of the buffer layer is recessed below the top surface of the first portion of the buffer layer, and a source/drain region substantially aligned with the spacer. The buffer layer preferably has a greater lattice constant than an underlying semiconductor substrate. The semiconductor device may further include a semiconductor-capping layer between the buffer layer and the gate dielectric, wherein the semiconductor-capping layer has a smaller lattice constant then the buffer layer. | 04-09-2009 |
Ching-Wei Wu, Caotun TW
| Patent application number | Description | Published |
|---|---|---|
| 20120092944 | MEMORY DEVICE HAVING A CLOCK SKEW GENERATOR - A memory device is provided with memory components and a clock skew generator, supporting at least two read and write operations that can occur coincidentally in read-read, read-write and write-write modes of operation of the memory device. The clock skew generator produces at least two stable and balanced clock channels carrying the at least two clock signals and varies relative timing of the clock signal edges so as to displace the edges in time, in those modes of operation wherein simultaneous edges would lead to detrimental loading. | 04-19-2012 |
Ching-Wei Wu, Hsin Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090109768 | SRAM Device with Enhanced Read/Write Operations - An SRAM device includes: a first group of memory cells connected to a first local bit line and a first local complementary bit line for accessing data nodes thereof; a second group of memory cells connected to a second local bit line and a second local complementary bit line for accessing data nodes thereof; and a global bit line and a global complementary bit line connected to the first and second local bit lines for accessing data nodes of the first and second groups of memory cells, wherein the first local bit line, the first local complementary bit line, the second local bit line, the second local complementary bit line, the global bit line and the global complementary bit line are constructed on a same metallization level in the SRAM device. | 04-30-2009 |
| 20090268501 | Novel SRAM Cell Array Structure - This invention discloses a static random access memory (SRAM) cell array structure which comprises a first and second bit-line coupled to a column of SRAM cells, the first and second bit-lines being substantially parallel to each other and formed by a first metal layer, and a first conductive line being placed between the first and second bit-lines and spanning across the column of SRAM cells without making conductive coupling thereto, the first conductive line being also formed by the first metal layer. | 10-29-2009 |
Ching-Wei Wu, Caotun Town TW
| Patent application number | Description | Published |
|---|---|---|
| 20100259999 | KEEPERS, INTEGRATED CIRCUITS, AND SYSTEMS THEREOF - A keeper of an integrated circuit includes a first transistor having a first gate being coupled with an output end of an inverter. A second transistor is coupled with the first transistor in series. The second transistor has a second gate being coupled with an input end of the inverter. | 10-14-2010 |
| 20100271898 | ACCESS TO MULTI-PORT DEVICES - Mechanisms for improving static noise margin and/or reducing misread current in multi-port devices are disclosed. In some embodiments related to dual port SRAM a suppress device (e.g., transistor) is provided at each word line port. When both ports are activated, both suppress devices are on and lower the voltage level of these ports, which in turn lower the voltage level at the node storing the data for the memory. As the voltage level at the data node is lowered, noise margin is improved and read disturb can be avoided. | 10-28-2010 |
| 20110019458 | MEMORY CIRCUITS, SYSTEMS, AND METHODS FOR ROUTING THE MEMORY CIRCUITS - A memory circuit includes a first memory array. The first memory array includes at least one first memory cell for storing a first datum. The at least one first memory cell is coupled with a first word line and a second word line. A second memory array is coupled with the first memory array. The second memory array includes at least one second memory cell for storing a second datum. The at least one second memory cell is coupled with a third word line and a fourth word line. The first word line is coupled with the third word line. The first word line is misaligned from the third word line in a routing direction of the first word line in the first memory array. | 01-27-2011 |
| 20110019460 | MEMORY CIRCUITS, SYSTEMS, AND FABRICATION METHODS THEREOF - A memory circuit includes a plurality of bit lines. A first memory cell and a second memory cell are coupled in series. Each of the first memory cell and the second memory cell is capable of storing a first type datum. The first memory cell and the second memory cell share a first common source/drain (S/D) region. The first common S/D region is electrically isolated from all of the bit lines. | 01-27-2011 |
| 20110242904 | Read Only Memory and Operating Method Thereof - A read only memory (ROM) and an operating method thereof are provided. The read only memory includes: a control circuit, powered by a first power source for outputting a control signal within a first voltage range; a voltage shifter, for expanding the amplitude of the control signal to a second voltage range; a word line driver, powered by a second power source with a voltage which is higher than that of the first power source, for driving one of a plurality of word lines of a read only memory cell array according to the control signal which is expanded to be within the second voltage range; and an input/output circuit, for connecting the plurality of bit lines to read out messages. | 10-06-2011 |
| 20120014158 | MEMORY DEVICES - A memory device includes an array of transistors, a plurality of bit lines, and a plurality of source lines. The transistors include gate, drain and source terminals. The gate terminals are electrically coupled to word lines. The plurality of bit lines connect a power source to the drain terminals of the array of transistors and the plurality of source lines connect the power source to the source terminals of the array of transistors. The connections are made active during a standby mode, thereby limiting leakage current without entailing drawbacks associated with degraded memory access/cycle time. | 01-19-2012 |
Ching-Wei Wu, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080229161 | MEMORY PRODUCTS AND MANUFACTURING METHODS THEREOF - Memory products and manufacturing methods thereof. A memory product comprises at least one memory cell and at least one redundancy memory cell. The memory cell and the redundancy memory cell have different physical or electronic properties. The redundancy memory cells are used as repair schemes for the memory cell if the memory cell is determined to have experienced Vccmin failure. | 09-18-2008 |
Ching-Wei Yeh, Min-Hsiung Chia-Yi TW
| Patent application number | Description | Published |
|---|---|---|
| 20090108905 | Dynamic NP-swappable body bias circuit - A dynamic NP-swappable body bias circuit includes a core circuit, a power switch and a body bias controller. The core circuit includes a body bias terminal. The power switch includes a body bias terminal, and connects the core circuit to an external voltage supply. The body bias controller is connected to the body bias terminals of the core circuit and the power switch so that the power switch and the core circuit are under the control of the body bias controller. | 04-30-2009 |