| Patent application number | Description | Published |
|---|
| 20080198669 | METHOD OF OPERATING NON-VOLATILE MEMORY - A non-volatile memory is provided. A substrate having a number of trenches and a number of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjacent trenches respectively. A number of select gate dielectric layers are disposed between the select gates and the substrate. A number of composite layers are disposed over the surface of the trenches and each composite layer has a charge trapping layer. A number of word lines are arranged in parallel in a second direction, wherein each of the word lines fills the trenches between adjacent select gates and is disposed over the composite layers. | 08-21-2008 |
| 20080227282 | METHOD OF MANUFACTURING NON-VOLATILE MEMORY - A non-volatile memory is provided. A substrate having a number of trenches and a number of select gates is provided. The trenches are arranged in parallel and extend in a first direction. Each of the select gates is disposed on the substrate between two adjacent trenches respectively. A number of select gate dielectric layers are disposed between the select gates and the substrate. A number of composite layers are disposed over the surface of the trenches and each composite layer has a charge trapping layer. A number of word lines are arranged in parallel in a second direction, wherein each of the word lines fills the trenches between adjacent select gates and is disposed over the composite layers. | 09-18-2008 |
| 20080316791 | OPERATING METHOD OF ONE-TIME PROGRAMMABLE READ ONLY MEMORY - The present invention provides a method of operating a one-time programmable read only memory (OTPROM). The OTPROM includes at least a select transistor, an electrode and a dielectric layer disposed on a substrate, wherein the electrode is set up on the source region of the select transistor and the dielectric layer is set up between the electrode and the source region. The method of operating the one-time programmable read only memory includes performing a programming operation to write a digital data value of ‘1’ into the memory and performing a programming operation to write a digital data value of ‘0’ into the memory. | 12-25-2008 |
| 20090021986 | OPERATING METHOD OF NON-VOLATILE MEMORY DEVICE - An operating method for a non-volatile memory device is applicable on a non-volatile memory device in which a substrate is disposed. The substrate includes a trench, a first conductive type first well region disposed in the substrate, and a second conductive type second well region disposed above the first conductive type first well region. The operating method includes applying a first voltage to a control gate, a second voltage to a drain region, and a third voltage to a source region. Besides, a channel F-N tunneling effect is employed to program a memory cell. | 01-22-2009 |
| 20090042350 | MANUFACTURING METHOD OF NONVOLATILE MEMORY - A manufacturing method for a non-volatile memory includes first providing a substrate with a gate structure formed thereon. The gate structure includes a first gate and a gate dielectric layer located between the first gate and the substrate. A first doping and a second doping region are formed on the substrate at two sides of the gate, respectively. A first insulating layer is formed on the substrate, and a portion of the first insulating layer and a portion of the substrate are removed to form a trench, which divides the second doping region into a third doping region and a fourth doping region. Finally, a tunneling dielectric layer, a charge-trapping layer and a top dielectric layer are formed inside the trench, and a second gate which fills the trench is formed on the substrate. | 02-12-2009 |
| 20090134452 | NON-VOLATILE MEMORY - A non-volatile memory includes a substrate, a memory unit array, (N+1) bit lines, M word lines, M first control gate lines, and M second control gate lines. The memory unit array includes N memory unit columns, and each memory unit column includes M memory units. The (N+1) bit lines are disposed on the substrate and arranged in parallel in the column direction, and the (N+1) bit lines are corresponding to the N memory unit columns. The M word lines are disposed on the substrate and arranged in parallel in the row direction. The M first control gate lines are arranged on the substrate in parallel in the row direction and respectively connected to the first memory cell in the same row. The M second control gate lines are arranged on the substrate in parallel in the row direction and respectively connected to the second memory cell in the same row. | 05-28-2009 |
| 20090235365 | DATA ACCESS SYSTEM - A data access system includes a host and a storage device. The host has a security setup function and includes a first identity code storage block to store a first identity code. The storage device has a security check function and includes a second identity code storage block. The host executes the security setup function to set a second identity code according to the first identity code, and the second identity code is stored into the second identity code storage block. The storage device executes the security check function to determine if the host is allowed to access the storage device according to the first and second identity codes. | 09-17-2009 |
| 20090270071 | MOBILE PHONE ACCESSING SYSTEM AND RELATED STORAGE DEVICE - The present invention provides a mobile phone accessing system. The mobile phone accessing system comprises: a mobile phone having a first International Mobile Equipment Identity (IMEI) code; and a storage device comprising a first storage region for storing data, a second storage region for storing a second IMEI code, and a controller coupled to the first storage region and the second storage region for executing a security check function to determine whether the mobile phone is qualified to access the first storage region according to the first IMEI code. | 10-29-2009 |
| 20090270129 | MOBILE PHONE ACCESSING SYSTEM AND RELATED STORAGE DEVICE - The present invention provides a mobile phone accessing system. The mobile phone accessing system comprises: a mobile phone having a first Subscriber Identity Module (SIM) specification corresponding to a SIM card; and a storage device comprising a first storage region for storing data, a second storage region for storing a second SIM specification, and a controller coupled to the first storage region and the second storage region for executing a security check function to determine whether the mobile phone is qualified to access the first storage region according to the first SIM specification. | 10-29-2009 |
| 20090271585 | DATA ACCESSING SYSTEM AND RELATED STORAGE DEVICE - A data accessing system includes a host computer and a storage device. The host computer has a first media access control (MAC) address, and the storage device includes a first storage region, a second storage region, and a controller. The first storage region is utilized for storing data. The second storage region stores a second media access control address. The controller couples to the first storage region and the second storage region for executing a security checking function to determine if the host computer is qualified to access the first storage region according to the first media access control address. | 10-29-2009 |
| 20110024823 | NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE WITH INTRINSIC CHARGE TRAPPING LAYER - A non-volatile semiconductor memory device includes a substrate, a first gate formed on a first region of a surface of the substrate, a second gate formed on a second region of the surface of the substrate, a charge storage layer filled between the first gate and the second gate, a first diffusion region formed on a first side of the charge storage layer, and a second diffusion region formed opposite the charge storage layer from the first diffusion region. The first region and the second region are separated by a distance sufficient for forming a self-aligning charge storage layer therebetween. | 02-03-2011 |
| 20110031560 | READ-ONLY MEMORY AND METHOD OF MANUFACTURE THEREOF - A mask-defined read-only memory array is formed on a substrate, and includes a first ROM bit and a second ROM bit of opposite polarities. The first ROM bit has a first MOS transistor and a first block layer formed over a first region of the substrate. A second source/drain region of the first MOS transistor and a first diffusion region are formed in a first region of the substrate on opposite sides of the first block layer. The second ROM bit includes a second MOS transistor. | 02-10-2011 |
