Patent application number | Description | Published |
20130237079 | CARD CONNECTOR - A card connector includes an insulating housing defining a receiving chamber and an inserting chamber connected with the receiving chamber, electrical terminals assembled in the insulating housing, and a shielding shell enclosing the insulating housing. Two receiving fillisters are opened in two inner sides of two side walls forming at two opposite sides of the receiving chamber. Two restraining members each has a base strip disposed in the receiving fillister, and an elastic arm inclined inward into the receiving chamber. The elastic arms are pressed into the receiving fillisters when a SIM card is inserted in the receiving chamber. In the process of inserting a micro SIM card into the card connector, the elastic arms resist against two opposite side edges of the micro SIM card to guide a rear of the micro SIM card to be smoothly inserted into the inserting chamber. | 09-12-2013 |
20140030923 | CARD CONNECTOR - A card connector includes an insulating housing having a pair of side walls of which one protrudes outward to form two stop blocks spaced along a front-to-rear direction, a plurality of electrical terminals disposed in the insulating housing, an upper shielding shell covered downward on the insulating housing, and a lower shielding shell covered upward under the insulating housing. The upper shielding shell has a top plate and a pair of side plates of which one is die-cut to form a positioning slice restricted between the stop blocks of the corresponding side wall. A front of each side plate is punched outward to form a vertical arched restricting portion. The lower shielding shell has a bottom plate and a pair of lateral plates of which a front of each top edge is concaved downward to form a restricting gap buckling the corresponding restricting portion therein. | 01-30-2014 |
20140051297 | CARD CONNECTOR - A card connector includes an insulating housing having two side walls of which an inside defines an inserting fillister, electrical terminals including a switch terminal which has a first contact arm and a first contact tail protruding from a free end of the first contact arm, and an upper shielding shell covered on the insulating housing and having two side plates of which one is die-cut to form a connecting slice inserted in the inserting fillister. A bottom of the connecting slice is bent inward to form a ground slice. The card connector utilizes the cooperation of a controlling switch of an electronic card and the first contact arm to control connection and disconnection between the first contact tail and the ground slice so as to further control a write procedure of the electronic card, wherein the controlling switch is movable between a closed position and an open position. | 02-20-2014 |
Patent application number | Description | Published |
20110284843 | Probe Pad On A Corner Stress Relief Region In A Semiconductor Chip - A semiconductor chip includes a corner stress relief (CSR) region. An enhanced structure connects sides of a seal ring structure to surround the CSR region. A device under test (DUT) structure is disposed on the CSR region. A set of probe pad structures is disposed on the CSR region. Two of the set of probe pad structures are electrically connect to the DUT structure. | 11-24-2011 |
20120018875 | Reducing Delamination Between an Underfill and a Buffer layer in a Bond Structure - A die includes a metal pad, a passivation layer, and a patterned buffer layer over the passivation layer. The patterned buffer layer includes a plurality of discrete portions separated from each other. An under-bump-metallurgy (UBM) is formed in an opening in the patterned buffer layer and an opening in the passivation layer. A metal bump is formed over and electrically coupled to the UBM. | 01-26-2012 |
20120092033 | MEASUREMENT OF ELECTRICAL AND MECHANICAL CHARACTERISTICS OF LOW-K DIELECTRIC IN A SEMICONDUCTOR DEVICE - Provided is a test structure for testing an unpackaged semiconductor wafer. The test structure includes a force-application component that is coupled to an interconnect structure of the semiconductor wafer. The force-application component is operable to exert a force to the semiconductor wafer. The test structure also includes first and second test portions that are coupled to the interconnect structure. The first and second test portions are operable to measure an electrical performance associated with a predetermined region of the interconnect structure. The first and second test portions are operable to measure the electrical performance while the force is exerted to the semiconductor wafer. | 04-19-2012 |
20120175728 | SEAL RING STRUCTURE FOR INTEGRATED CIRCUIT CHIPS - A semiconductor device includes a substrate having a circuit region and a seal ring region. The seal ring region surrounds the circuit region. A seal ring structure is disposed over the seal ring region. The seal ring structure has a first portion and a second portion above the first portion. The first portion has a width W | 07-12-2012 |
20120235303 | REINFORCEMENT STRUCTURE FOR FLIP-CHIP PACKAGING - The present disclosure provides a carrier substrate, a device including the carrier substrate, and a method of bonding the carrier substrate to a chip. An exemplary device includes a carrier substrate having a chip region and a periphery region, and a chip bonded to the chip region of the carrier substrate. The carrier substrate includes a reinforcement structure embedded within the periphery region. | 09-20-2012 |
20140087522 | Reducing Delamination Between an Underfill and a Buffer Layer in a Bond Structure - A die includes a metal pad, a passivation layer, and a patterned buffer layer over the passivation layer. The patterned buffer layer includes a plurality of discrete portions separated from each other. An under-bump-metallurgy (UBM) is formed in an opening in the patterned buffer layer and an opening in the passivation layer. A metal bump is formed over and electrically coupled to the UBM. | 03-27-2014 |
20140145307 | Seal Ring Structure with Metal-Insulator-Metal Capacitor - A seal ring structure of an integrated circuit includes a seal ring and a metal-insulator-metal (MIM) capacitor. The MIM capacitor includes a top electrode, a bottom electrode disposed below the top electrode, and a first insulating layer disposed between the top electrode and the bottom electrode. The MIM capacitor is disposed within the seal ring and the MIM capacitor is insulated from the seal ring. | 05-29-2014 |
20140252608 | Method and Apparatus for Packaging Pad Structure - Methods and apparatus are disclosed for manufacturing metal contacts under ground-up contact pads within a device. A device may comprise a bottom metal layer with a bottom metal contact, a top metal layer with a top metal contact, and a plurality of middle metal layers. Any given metal layer of the plurality of middle metal layers comprises a metal contact, the metal contact is substantially vertically below the top metal contact, substantially vertically above the bottom metal contact, and substantially vertically above a metal contact in any metal layer that is below the given metal layer. The metal contacts may be of various and different shapes. All the metal contacts in the plurality of middle metal layers and the bottom metal contact may be smaller than the top metal contact, therefore occupying less area and saving more area for other functions such as device routing. | 09-11-2014 |
20140374899 | Package with Solder Regions Aligned to Recesses - A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad. | 12-25-2014 |
20150014846 | Self-alignment Structure for Wafer Level Chip Scale Package - A packaged semiconductor device includes a semiconductor substrate, a metal pad, a metal base, a polymer insulating layer, a copper-containing structure and a conductive bump. The metal pad and the metal base are disposed on the semiconductor substrate. The polymer insulating layer overlies the metal base and the semiconductor substrate. The copper-containing structure is disposed over the polymer insulating layer, and includes a support structure and a post-passivation interconnect (PPI) line. The support structure is aligned with the metal base. The PPI line is located partially within the support structure, and extends out through an opening of the support structure, in which a top of the support structure is elevated higher than a top of the PPI line. The conductive bump is held by the support structure. | 01-15-2015 |
20150076689 | Hollow Metal Pillar Packaging Scheme - An integrated circuit includes a bottom substrate, a metal layer disposed over the bottom substrate and a hollow metal pillar disposed on the metal layer. The metal layer and the hollow metal pillar are electrically connected. | 03-19-2015 |
20150102459 | Metal Insulator Metal Capacitor and Method for Making the Same - A semiconductor device includes one or more metal-insulator-metal (MiM) capacitors. The semiconductor device includes a bottom electrode, a dielectric layer located above, and in physical contact with, the bottom electrode, a top electrode located above, and in physical contact with, the dielectric layer, a first top contact contacting the top electrode, a first bottom contact contacting the bottom electrode from a top electrode direction, a first metal bump connecting to the top contact, and a second metal bump connecting to the bottom contact. The top electrode has a smaller area than the bottom electrode. The bottom electrode, the dielectric layer, and the top electrode is a MiM capacitor. Top electrodes of a number of MiM capacitors and bottom electrodes of a number of MiM capacitors are daisy chained to allow testing of the conductivity of the electrodes. | 04-16-2015 |
Patent application number | Description | Published |
20090168282 | ESD PROTECTION CIRCUIT - An ESD protection circuit includes: a voltage decreasing module, coupled between a first voltage level and a second voltage level, wherein the first voltage level is higher than the second voltage level; a gate trigger switch, coupled between the first voltage level and the second voltage level; and a detection circuit, coupled to the gate trigger switch, for detecting an ESD event to control the gate trigger switch. | 07-02-2009 |
20090195949 | INTEGRATED CIRCUIT WITH ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT - An integrated circuit with an electrostatic discharge protection circuit includes a first power pad, a second power pad, at least a circuit module, and a power clamp circuit. The circuit module includes a signal pad, an internal circuit and a first bipolar transistor. A first parasitical resistance is coupled between a collector of the first bipolar transistor and the second power pad. There is at least a metal-oxide semiconductor (MOS) transistor and at least a first parasitical bipolar transistor included within the power clamp circuit. | 08-06-2009 |
20110103034 | ELECTRONIC CHIP AND SUBSTRATE PROVIDING INSULATION PROTECTION BETWEEN CONDUCTING NODES - An electronic chip includes a plurality of conducting pins and a plurality of insulating blocks. The conducting pins are disposed on an outer side of the electronic chip to provide electrical connections between the electronic chip and an external circuit. Each of the insulating blocks is disposed between two adjacent conducting pins. | 05-05-2011 |
20110291697 | DIGITAL LOGIC CIRCUIT AND MANUFACTURE METHOD THEREOF - A digital logic circuit and a manufacture method of the digital logic circuit thereof are provided. The digital logic circuit includes a voltage rail, a ground rail, and a plurality of logic circuit rails, wherein each of the logic circuit rails is electrically connected to the voltage rail and the ground rail. The logic circuit rail includes a logic unit and an auxiliary unit electrically connected to the voltage rail and the ground rail. The logic unit includes a logic voltage end electrically connected to the voltage rail and a logic ground end electrically connected to the ground rail. The auxiliary unit includes an auxiliary voltage end electrically connected to the voltage rail and an auxiliary ground end electrically connected to the ground rail. At least one of the width ratio between the auxiliary voltage end and the logic voltage end and the width ratio between the auxiliary ground end and the logic ground end is greater than 1. | 12-01-2011 |
Patent application number | Description | Published |
20090315118 | TRANSMISSION GATE WITH BODY EFFECT COMPENSATION CIRCUIT - A transmission gate circuit includes a first PMOS device, a first NMOS device, a second PMOS device, a second NMOS device, and a third transistor. A gate electrode, a first electrode and a second electrode of the first PMOS device are coupled to a first control signal, an input end, and an output end, respectively. A gate electrode, a first electrode and a second electrode of the first NMOS device are coupled to a second control signal, the input end, and the output end, respectively. A gate electrode, a first electrode and a second electrode of the second PMOS device are coupled to the first control signal, an input end, and a body electrode of the first PMOS device, respectively. A gate electrode, a first electrode, and a second electrode of the second NMOS device are coupled to the second control signal, a body electrode of the first PMOS device, and the output end, respectively. A gate electrode, a first electrode and a second electrode of the third PMOS device are coupled to a second control signal, a first supply voltage, and the body electrode of the first PMOS device, respectively. | 12-24-2009 |
20100125686 | ELECTRONIC APPARATUS HAVING SWITCHING UNIT - An electronic apparatus having switching unit is described. The electronic apparatus includes a first peripheral device, a second peripheral device and a switching unit. The first peripheral device communicates with the host unit. The second peripheral device communicates with the host unit and the first peripheral device, respectively. The switching unit switches to the host unit and the first peripheral device for allowing the host unit to access the first peripheral device via a first path. The switching unit switches to the host unit and the second peripheral device for allowing the host unit to access the second peripheral device via a second path. The switching unit switches to the first peripheral device and the second peripheral device for allowing the first peripheral device to access the second peripheral device via a third path. | 05-20-2010 |