Patent application number | Description | Published |
20120079919 | OIL FILTER CANISTER ADAPTER - An oil filter canister adapter of the present invention mainly includes a base, a rotatable plate, three rotatable members, and three holders. The rotatable plate and the rotatable members are respectively disposed on the base. The rotatable members contact with the rotatable plate respectively, so that the rotatable plate can rotate and drive the rotatable members to rotate. The holders are detachably disposed on the rotatable members respectively. Distances between any two adjacent holders are consistent in value. The distances between the holders are adjustable when the rotatable members rotate. | 04-05-2012 |
20120222522 | OIL FILTER REPLACEMENT DEVICE - According to the present invention, the oil filter replacement device has a number of pins for clamping an oil filter, and the pins are extended eccentrically from corresponding secondary gear members. The secondary gear members are engaged to spin simultaneously by a main gear member. As such, the pins could be adjusted to fit on oil filters of various sizes. Additionally, each pin is rotatable and has at least a flat face. As the pins rolls along the circumference of the oil filter, their flat faces are turned to interface the flat faces around the oil filter. As such, the oil filter is tightly and reliably clamped by the oil filter replacement device, thereby preventing the problem of uneven exertion of force and deforming the oil filter. | 09-06-2012 |
20120284982 | DRAWING DEVICE - A drawing device of the present invention includes a first driving element, a bolt, a plurality of second driving elements, and a plurality of clipping rods. The first driving element drives the second driving elements to rotate simultaneously, so that the clipping rods are able to be rotated and operated. Also, a hook portion of each clipping rod is able to hook to a bottom of objects to be drawn out, and the bolt is disposed on a threaded hole of the first driving element and abuts against the objects to be drawn out. At the same time, the clipping rods are moved outward. | 11-15-2012 |
20130147505 | TEST PROBING STRUCTURE - A testing probe structure for wafer level testing semiconductor IC packaged devices under test (DUT). The structure includes a substrate, through substrate vias, a bump array formed on a first surface of the substrate for engaging a probe card, and at least one probing unit on a second surface of the substrate. The probing unit includes a conductive probe pad formed on one surface of the substrate and at least one microbump interconnected to the pad. The pads are electrically coupled to the bump array through the vias. Some embodiments include a plurality of microbumps associated with the pad which are configured to engage a mating array of microbumps on the DUT. In some embodiments, the DUT may be probed by applying test signals from a probe card through the bump and microbump arrays without direct probing of the DUT microbumps. | 06-13-2013 |
20130187156 | THREE DIMENSIONAL INTEGRATED CIRCUIT HAVING A RESISTANCE MEASURMENT STRUCTURE AND METHOD OF USE - A three-dimensional integrated circuit (3DIC) including a top chip having at least one active device and an interposer having conductive routing layers and vias. The 3DIC further includes a plurality of conductive connectors configured to electrically connect the top chip and the interposer. The 3DIC further includes a conductive line over at least one of the top chip or the interposer. The conductive line traces a perimeter of top chip or interposer parallel to an outer edge of the top chip or interposer. The conductive line is configured to electrically connect the conductive connectors. The 3DIC further includes at least one testing element over at least one of the top chip or the interposer. The testing element is configured to electrically connect to the plurality of conductive connectors. | 07-25-2013 |
20130290914 | Methods and Apparatus for Floorplanning and Routing Co-Design - Methods and apparatus of performing floorplanning and routing for function blocks within a die and among multiple die are disclosed. Multiple die together with function blocks within each die may be represented by a flexible hierarchical (FH) tree. An initial floorplan for multiple die may be generated and hot spots between die or among function blocks within a die may be identified. Spacer blocks may be inserted between die, and block inflation may be performed, to remove hot spots. More perturbation of the block positions can be performed on the FH tree to rearrange the blocks and die. After the multiple die floorplanning, a plurality of micro bumps may be mapped to a plurality of pins of blocks of the plurality of die, placement and routing may be performed for the plurality of blocks within each die and connections for the plurality of dies. | 10-31-2013 |
20130326463 | Method to Determine Optimal Micro-Bump-Probe Pad Pairing for Efficient PGD Testing in Interposer Designs - The present disclosure relates to a method of routing probe pads to micro-bumps of an interposer. An interposer is provided having target micro-bumps and probe pads. The probe pads are initially unassigned. Target micro-bump locations and probe pad locations are obtained. Possible route assignments from the probe pads to the target micro-bumps are obtained. Costs are developed for the possible route assignments at least partially according to the target micro-bump locations and the probe pad locations. Final assignments are selected from the possible assignments according to the costs. | 12-05-2013 |
20140176165 | Apparatus for Three Dimensional Integrated Circuit Testing - A three-dimensional integrated circuit testing apparatus comprises a probe card configured to couple a device-under-test of a three-dimensional integrated circuit with an automatic testing equipment board having a plurality of testing modules, wherein the probe card comprises a plurality of known good dies of the three-dimensional integrated circuit, a plurality of interconnects of the three-dimensional integrated circuit and a plurality of probe contacts, wherein the probe contacts are configured to couple the probe card with testing contacts of the device-under-test of the three-dimensional integrated circuit. | 06-26-2014 |
20140282305 | COMMON TEMPLATE FOR ELECTRONIC ARTICLE - One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor. | 09-18-2014 |
20150213182 | COMMON TEMPLATE FOR ELECTRONIC ARTICLE - One or more techniques or systems for incorporating a common template into a system on chip (SOC) design are provided herein. For example, a common template mask set is generated based on a first set of polygon positions from a first vendor and a second set of polygon positions from a second vendor. A third party creates a third party SOC design using a set of design rules generated based on the common template mask set. The common template is fabricated based on the third party SOC design using the common template mask set. Because the common template is formed using the common template mask set and because the common template mask set is based on polygon positions from both the first vendor and the second vendor, a part can be connected to the SOC regardless of whether the part is sourced from the first vendor or the second vendor. | 07-30-2015 |
20150234004 | METHOD OF TESTING A THREE-DIMENSIONAL INTEGRATED CIRCUIT - A method of testing a three-dimensional integrated circuit (3DIC) includes applying a voltage through at least one testing element and at least one conductive line, wherein the at least one conductive line traces a perimeter of at least one of a top chip or an interposer substantially parallel to an outer edge of the at least one top chip or the interposer, and the at least one conductive line is configured to electrically connect a plurality of conductive connectors. The method further includes measuring a current responsive to the applied voltage. The method further includes determining an integrity of the 3DIC based on the measured current. | 08-20-2015 |
Patent application number | Description | Published |
20130056795 | FinFET Design Controlling Channel Thickness - System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate. | 03-07-2013 |
20130113042 | MULTI-GATE SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin. | 05-09-2013 |
20130126981 | MULTI-GATE SEMICONDUCTOR DEVICES - A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion. | 05-23-2013 |
20140103438 | MULTI-GATE SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME - A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin. | 04-17-2014 |
20140151761 | Fin-Like Field Effect Transistor (FinFET) Channel Profile Engineering Method And Associated Device - A FinFET device and method for fabricating a FinFET device are disclosed. An exemplary method includes providing a substrate; forming a fin over the substrate; forming an isolation feature over substrate; forming a gate structure including a dummy gate over a portion of the fin, the gate structure traversing the fin, wherein the gate structure separates a source region and a drain region of the fin, a channel being defined in the portion of the fin between the source region and the drain region; and replacing the dummy gate of the gate structure with a metal gate, wherein during the replacing the dummy gate, a profile of the portion of the fin is modified. In an example, modifying the profile of the portion of the fin includes increasing a height of the portion of the fin and/or decreasing a width of the portion of the fin. | 06-05-2014 |
20140183641 | HIGH EFFICIENCY FINFET DIODE - Disclosed are a FinFET diode of high efficiency, designed to resolve the degradation problem with a conventional FinFET diode arising from reduced active area, and a method of fabrication. The FinFET diode has a doped substrate, two spaced-apart groups of substantially parallel, equally-spaced, elongated semiconductor fin structures, dielectric layers formed between the two groups and among the fin structures for insulation, a plurality of substantially equal-spaced and parallel elongated gate structures perpendicularly traversing both groups of the fin structures, and two groups of semiconductor strips respectively formed lengthwise upon the two groups of the fin structures. The two groups of semiconductor strips are doped to have opposite conductivity types, p-type and n-type. The FinFET diode further has metal contacts formed upon the semiconductor strips. In an embodiment, the semiconductor strips may be integrally formed with the fin structures by epitaxial growth and in-situ doped. | 07-03-2014 |
20150079752 | FinFET Design Controlling Channel Thickness - System and method for controlling the channel thickness and preventing variations due to formation of small features. An embodiment comprises a fin raised above the substrate and a capping layer is formed over the fin. The channel carriers are repelled from the heavily doped fin and confined within the capping layer. This forms a thin-channel that allows greater electrostatic control of the gate. | 03-19-2015 |
20150162334 | MULTI-GATE SEMICONDUCTOR DEVICES - A multi-gate semiconductor device is formed including a semiconductor substrate. The multi-gate semiconductor device also includes a first transistor including a first fin portion extending above the semiconductor substrate. The first transistor has a first channel region formed therein. The first channel region includes a first channel region portion doped at a first concentration of a first dopant type and a second channel region portion doped at a second concentration of the first dopant type. The second concentration is higher than the first concentration. The first transistor further includes a first gate electrode layer formed over the first channel region. The first gate electrode layer may be of a second dopant type. The first dopant type may be N-type and the second dopant type may be P-type. The second channel region portion may be formed over the first channel region portion. | 06-11-2015 |
Patent application number | Description | Published |
20080243383 | Integrated collision avoidance enhanced GN&C system for air vehicle - Collision with ground/water/terrain and midair obstacles is one of the common causes of severe aircraft accidents. The various data from the coremicro AHRS/INS/GPS Integration Unit, terrain data base, and object detection sensors are processed to produce collision warning audio/visual messages and collision detection and avoidance of terrain and obstacles through generation of guidance commands in a closed-loop system. The vision sensors provide more information for the Integrated System, such as, terrain recognition and ranging of terrain and obstacles, which plays an important role to the improvement of the Integrated Collision Avoidance System. | 10-02-2008 |
20090070058 | Miniaturized smart self-calibration electronic pointing method and system - An innovative configuration of Miniaturized Smart Self-calibration EPD for mortar applications, as the azimuth/heading and elevation measurement device. This innovative EPD configuration uses only two FOGs or DTG and accelerometers and it is self-contained. This leads to a new EPD implementation that produces a small and light device with lower cost and adequate accuracy for the small dismounted mortar applications. | 03-12-2009 |
20090073034 | 4D GIS virtual reality for controlling, monitoring and prediction of manned/unmanned system - A method and system for multi-tracking among independent individuals without a monitoring center, where an individual is a person, a vehicle, or any other property, enables the individuals to be networked in a group and each individual to search and track other individuals of interest. The portable multi-tracking system is also capable of tracking personnel inside a building, where a self-contained positioning device provides continuous carrier's position information. In the open area a GPS (Global Positioning System) unit is activated to provide precision absolute position data which can be blended with the self-contained data to improve the accuracy and robustness of the positioning services. Thus the present invention provides excellent position tracking outside a building. | 03-19-2009 |
20090087029 | 4D GIS based virtual reality for moving target prediction - The technology of the 4D-GIS system deploys a GIS-based algorithm used to determine the location of a moving target through registering the terrain image obtained from a Moving Target Indication (MTI) sensor or small Unmanned Aerial Vehicle (UAV) camera with the digital map from GIS. For motion prediction the target state is estimated using an Extended Kalman Filter (EKF). In order to enhance the prediction of the moving target's trajectory a fuzzy logic reasoning algorithm is used to estimate the destination of a moving target through synthesizing data from GIS, target statistics, tactics and other past experience derived information, such as, likely moving direction of targets in correlation with the nature of the terrain and surmised mission. | 04-02-2009 |
20090089001 | Self-calibrated azimuth and attitude accuracy enhancing method and system (SAAAEMS) - A method and system for Self-calibrated Azimuth and Attitude Accuracy Enhancing are disclosed, wherein SAAAEMS approach is based on fully auto-calibration self-contained INS principles, not depending on magnetometers for azimuth/heading determination, and thus the system outputs and performance are not affected by the environmental magnetic fields. In order to reduce the system size and cost, this new innovative methods and algorithms are used for SAAAEMS system configuration and integration. Compared to a conventional INS for gyrocompassing, AGNC's approach uses a smaller number of high accuracy sensors: SAAAEMS uses only one 2-axis high accuracy gyro (for example, one DTG) instead of 3-axis; the third axis gyro is a MEMS gyro. It uses only 2 high accuracy accelerometers instead of 3, since the two accelerometers are used only for gyrocompassing not for navigation. These two changes to the conventional INS system configuration remarkably reduce the whole system size and cost. SAAAEMS, uses dynamic gyrocompassing processing for isolation of Base motion disturbance/interference and vibration. SAAAEMS provides a method and system for using automatic methods for system calibration. | 04-02-2009 |
20100283832 | Miniaturized GPS/MEMS IMU integrated board - This invention documents the efforts on the research and development of a miniaturized GPS/MEMS IMU integrated navigation system. A miniaturized GPS/MEMS IMU integrated navigation system is presented; Laser Dynamic Range Imager (LDRI) based alignment algorithm for space applications is discussed. Two navigation cameras are also included to measure the range and range rate which can be integrated into the GPS/MEMS IMU system to enhance the navigation solution. | 11-11-2010 |
20110093250 | Gyrocompass modeling and simulation system (GMSS) and method thereof - A Modeling, Design, Analysis, Simulation, and Evaluation (MDASE) aspects of gyrocompassing in relation to Far-Target Location (FTL) systems include a Gyrocompass Modeling and Simulation System (GMSS). The GMSS is a modularized software system which has four major components: the 6DOF Motion Simulator, the IMU Sensor Simulator, the Gyrocompass System and Calibration Process Simulator, the Gyrocompass System Evaluation and Analysis Module. Each module has one or two graphic user interfaces (GUIs) as user interfaces for simulation components selection and parameter setting. The modular architecture of GMSS makes it very flexible for programming and testing. And, the component-based software development technology greatly eases system extension and maintenance. The simulators can be used as either an off-line tool or as a real-time simulation tool. The realization of the GMSS can be based on any computer platforms, for it is written in high level language and tools and is portable. The stochastic signal analysis and sensor testing and modeling tools comprise a suite of generic statistical analysis software, including Allan Variance and PSD analysis tools, which are available to every GMSS module and greatly enhanced the system functionality. | 04-21-2011 |
20110167024 | Embedded health monitoring system based upon Optimized Neuro Genetic Fast Estimator (ONGFE) - A real time kernel for deploying health monitoring functions in Condition Base Maintenance (CBM) and Real Time Monitoring (RTM) systems is disclosed in this invention. The Optimized Neuro Genetic Fast Estimator (ONGFE) allows embedding failure detection, identification, and prognostics (FDI&P) capability by using Intelligent Software Element (ISE) based upon Artificial Neural Network (ANN). ONGFE enables embedded fast and on-line training for designing ANNs, which perform very high performance FDI&P functions. An advantage is the optimization block based on pseudogenetic algorithms, which compensate for effects due to initial weight values and local minimums without the computational burden of genetic algorithms. It provides a synchronization block for communication with secondary diagnostic modules. Also a scheme for conducting sensor data validation is embedded in Smart Sensors (SS). The algorithms are designed for a distributed, scalar, and modular deployment. The system electronics is built upon a network of smart sensors and a health monitoring computer for providing data acquisition capability and distributed computational power. | 07-07-2011 |
20130012821 | Robotic module for natural orifice transluminal endoscopic surgery (NOTES) - A miniature in-vivo robotic module to be used for conducting dexterous manipulations on organs and other target entities in a patient's abdominal or peritoneal cavity as part of Natural Orifice Transluminal Endoscopic Surgery (NOTES) is disclosed in this invention. The robotic module is a serial manipulator consisting of seven cylindrical links and six actively controllable rotational degrees of freedom, thereby enabling an end effector equipped with a laparoscopic type instrument to assume a commanded position and orientation within the robot's workspace. After overtube navigation starting from a natural orifice or preexisting wound, the module must be anchored and guided to a designated location along the inner abdominal cavity wall. This is accomplished via magnetic coupling forces between internal embedded magnets and magnets fixed to the end of a different robotic manipulator located external to the patient. | 01-10-2013 |
Patent application number | Description | Published |
20110081667 | BIOMARKERS ASSOCIATED WITH NEPHROPATHY - Use of urine biomarkers for diagnosing nephropathy, monitoring nephropathy progress, and assessing efficacy of a nephropathy treatment. These urine biomarkers include leukocyte-associated Ig-like receptor-2, alpha-1 acid glycoprotein, their fragments, and combinations thereof. | 04-07-2011 |
20110081668 | BIOMARKERS ASSOCIATED WITH NEPHROPATHY - Use of urine biomarkers for diagnosing nephropathy, monitoring nephropathy progress, and assessing efficacy of a nephropathy treatment. These urine biomarkers include leukocyte-associated Ig-like receptor-2, alpha-1 acid glycoprotein, their fragments, and combinations thereof. | 04-07-2011 |
20110086372 | BIOMARKERS ASSOCIATED WITH NEPHROPATHY - Use of urine biomarkers for diagnosing nephropathy, monitoring nephropathy progress, and assessing efficacy of a nephropathy treatment. These urine biomarkers include leukocyte-associated Ig-like receptor-2, alpha-1 acid glycoprotein, their fragments, and combinations thereof. | 04-14-2011 |
20130266976 | BIOMARKERS ASSOCIATED WITH NEPHROPATHY - Use of urine biomarkers for diagnosing nephropathy, monitoring nephropathy progress, and assessing efficacy of a nephropathy treatment. These urine biomarkers include leukocyte-associated Ig-like receptor-2, alpha-1 acid glycoprotein, their fragments, and combinations thereof. | 10-10-2013 |