| Patent application number | Description | Published |
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| 20100084735 | SEMICONDUCTOR ASSEMBLY AND METHOD FOR FORMING SEAL RING - A method for forming a seal ring is disclosed. First, a substrate including a MEMS region, a logic region and a seal ring region is provided. Second, a trench is formed in the MEMS region and multiple recesses are formed in the seal ring region. An oxide fills the trench and the recesses. Later, a MOS is form in the logic region and a dielectric layer is formed on the substrate. Then, an etching procedure is carried out to partially remove the dielectric layer and simultaneously remove the oxide in the multiple recesses completely to form a seal ring space. Afterwards, a metal fills the seal ring space to from the seal ring. | 04-08-2010 |
| 20100096726 | METAL CAPACITOR AND METHOD OF MAKING THE SAME - A method of making a metal capacitor includes the following steps. A dielectric layer having a metal interconnection and a capacitor electrode is provided. Then, a treatment is performed to increase the dielectric constant of the dielectric layer surrounding the capacitor electrode. The treatment can be UV radiation, a plasma treatment or an ion implantation. Accordingly, the metal capacitor will have a higher capacitance and RC delay between the metal interconnection and the dielectric layer can be prevented. | 04-22-2010 |
| 20110012227 | SEMICONDUCTOR ASSEMBLY - A semiconductor assembly includes a substrate with at least a CMOS region and a seal ring region and an optional micro electro mechanical system (MEMS) region, a shallow trench isolation disposed in the CMOS region of the substrate, an optional micro electro mechanical system device disposed in the micro electro mechanical system region, a plurality of recesses disposed in the seal ring region of the substrate, a first metal-oxide semiconductor disposed in the CMOS region, a dielectric layer disposed on the substrate and on the recesses, and a seal ring disposed in the seal ring region and embedded in the dielectric layer to cover and fill up the recesses, wherein the seal ring region surrounds at least the CMOS region and the optional MEMS region. | 01-20-2011 |
| Patent application number | Description | Published |
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| 20080237144 | METHOD FOR REMOVING MICRO-BUBBLES AND/OR PARTICLES FROM LIQUID, LIQUID SUPPLY APPARATUS AND IMMERSION EXPOSURE APPARATUS - A liquid supply apparatus capable of removing micro-bubbles and particles is described, including a pipe, a laser provider and at least one micro-bubble/particle outlet. The laser provider provides a laser crossing the pipe, wherein the laser is provided in a manner such that a micro-bubble/particle blocking/repelling barrier is formed crossing the pipe blocking or repelling micro-bubbles, particles or both in the liquid in the pipe. The micro-bubble/particle outlet is disposed on the pipe between the barrier and the liquid inlet of the pipe, adjacent to the barrier for discharging micro-bubbles, particles or both. | 10-02-2008 |
| 20080237659 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A method of fabricating a semiconductor device is provided. Devices are formed on a core region and a non-core region in a substrate. A strain process is performed to the device on the core region but is not performed to the device on the non-core region. | 10-02-2008 |
| 20080246061 | STRESS LAYER STRUCTURE - A stress layer structure disposed on a substrate including a device region and a non-device region is provided. The device region includes active regions and a non-active region. The stress layer structure has stress patterns, at least one partition line, and at least one dummy stress pattern. Each of the stress patterns is disposed on the substrate of each of the active regions, respectively. The partition line exposes a portion of the substrate and divides the two adjacent stress patterns. The dummy stress pattern is disposed on the substrate in the partition line. | 10-09-2008 |
| 20080296695 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor is provided. The semiconductor device includes a transistor, a first strain layer and a second strain layer on a substrate. The first strain layer is configured at the periphery of the transistor. The second strain layer covers the transistor and a region exposed by the first strain layer. The stress provided by the second strain layer is different from that by the first strain layer. | 12-04-2008 |
| 20090079083 | INTERCONNECT STRUCTURE AND FABRICATING METHOD OF THE SAME - A fabricating method of an interconnect structure is provided. A first dielectric layer is formed on a substrate for covering an air gap region and a non-air gap region. Next, interconnects are formed in the first dielectric layer on the air gap region and in the first dielectric layer on the non-air gap region. Then, a cap layer is formed on the first dielectric layer. Thereafter, on the air gap region, a portion of the cap layer and a portion of the first dielectric layer are removed for forming first openings, and thereby a portion of the first dielectric layer are left between the interconnects for forming support pillars. After that, a second dielectric layer is formed over the substrate for covering the cap layer and the first openings, so as to form an air gap in each of the first openings. | 03-26-2009 |
| 20090212368 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME - A semiconductor device including transistors and strain layers is provided. Each transistor includes a source region and a drain region on a substrate and a gate structure on a channel region between the source region and the drain region. Lengths of the channel regions of these transistors are the same, but at least one source or drain region has a width along a channel length direction and the width is different from widths of other source or drain regions. The strain layers include first and second strain layers embedded separately at two sides of each gate structure in the substrate. A first width of each first strain layer along the channel length direction is the same, and a second width of each second strain layer along the channel length direction is the same. | 08-27-2009 |
| 20100090749 | MULTI-FUNCTION CHIP - A multi-function chip including a circuit and at least one control circuit is provided. The circuit having multiple functions includes an interconnection. The interconnection has at least one resistance-variable segment. The control circuit is electronically connected to the resistance-variable segment. One of the functions is carried out by adjusting the resistance of the resistance-variable segment with the control circuit. | 04-15-2010 |
