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| 20090053888 | Method of depositing a diffusion barrier layer which provides an improved interconnect - A method of depositing a duffusion barrier layer with overlying conductive layer or fill which lowers resistivity of a semiconductor device interconnect. The lower resistivity is achieved by inducing the formation of alpha tantalum within a tantalum-comprising barrier layer. | 02-26-2009 |
| 20090269922 | Method of depositing a metal seed layer over recessed feature surfaces in a semiconductor substrate - We disclose a method of depositing a metal seed layer on a wafer substrate comprising a plurality of recessed device features. The method comprises depositing a first portion of the metal seed layer on the wafer via plasma deposition at a sufficient ratio of wafer substrate bias to DC source power that bottom coverage is achieved while resputtering of surfaces of the recessed device features is inhibited. The method also comprises depositing a second portion of the metal seed layer at a ration of substrate RF bias to DC source power such that resputtering is not inhibited. | 10-29-2009 |
| 20100099270 | ATOMIC LAYER DEPOSITION APPARATUS - A method and apparatus for atomic layer deposition (ALD) is described. The apparatus comprises a deposition chamber and a wafer support. The deposition chamber is divided into two or more deposition regions that are integrally connected one to another. The wafer support is movable between the two or more interconnected deposition regions within the deposition chamber. | 04-22-2010 |
| 20110111603 | ATOMIC LAYER DEPOSITION APPARATUS - A method and apparatus for atomic layer deposition (ALD) is described. The apparatus comprises a deposition chamber and a wafer support. The deposition chamber is divided into two or more deposition regions that are integrally connected one to another. The wafer support is movable between the two or more interconnected deposition regions within the deposition chamber. | 05-12-2011 |
| 20110256716 | Method of depositing a uniform barrier layer and metal seed layer with reduced overhang over a plurality of recessed semiconductor features - A method of depositing a metal seed layer with underlying barrier layer on a wafer substrate comprising a plurality of recessed device features. A first portion of the barrier layer is deposited on the wafer substrate without excessive build-up of barrier layer material on the openings to the plurality of recessed device features, while obtaining bottom coverage without substantial sputtering of the bottom surface. Subsequently, a metal seed layer is deposited using the same techniques used to deposit the barrier layer, to avoid excessive build up of metal seed layer material on the openings to the features, with minimal sputtering of the barrier layer surface. | 10-20-2011 |
| 20110294293 | CHEMICAL PLANARIZATION OF COPPER WAFER POLISHING - Embodiments described herein relate to removing material from a substrate. More particularly, the embodiments described herein relate to polishing or planarzing a substrate by a chemical mechanical polishing process. In one embodiment, a method of chemical mechanical polishing (CMP) of a substrate is provided. The method comprises exposing a substrate having a conductive material layer formed thereon to a polishing solution comprising phosphoric acid, one or more chelating agents, one or more corrosion inhibitors, and one or more oxidizers, forming a passivation layer on the conductive material layer, providing relative motion between the substrate and a polishing pad and removing at least a portion of the passivation layer to expose a portion of the underlying conductive material layer, and removing a portion of the exposed conductive material layer. | 12-01-2011 |
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| 20100328116 | DEVICES FOR CONVERSION BETWEEN SERIAL AND PARALLEL DATA - Serial-to-parallel and parallel-to-serial conversion devices may provide for efficient conversion of serial bit streams into parallel data units (and vice versa). In one implementation, a device may include delay circuits, each of which being configured to receive a serial data stream. A rotator circuit may receive the delayed serial data streams and rearrange bits in the serial data streams. Register circuits may receive the output of the rotator circuit and collectively output, in parallel, a number of bits of one of the serial bit streams. | 12-30-2010 |
| 20100329066 | NON-BLOCKING MULTI-PORT MEMORY FORMED FROM SMALLER MULTI-PORT MEMORIES - A multi-port memory may be formed from a plurality of “simpler” memories. In one implementation, the memory includes a write port and a number of memories provided in groups, such that the write port supplies each of a plurality of copies of the data unit to a subset of the memories, each of the subset of memories being provided in a corresponding one of the groups, a number of the copies of the data unit being greater than two. Multiplexers may be implemented, each of which being associated with a corresponding one of the groups of the memories. One of the plurality of multiplexers may be configured to selectively supply one of the copies of the data unit from one of the memories. A read port may receive the one of the copies of the data unit from the one of the multiplexers and output the one of the copies of the data unit. | 12-30-2010 |
| 20110055491 | SIMULTANEOUS SWITCHING OF MULTIPLE TIME SLOTS IN AN OPTICAL NETWORK NODE - A switching frame buffer is described in which data units within a sequence of time slots, of a frame, may be simultaneously input and output at ports of the switching frame buffer. In one implementation, a write port may receive data units within a single cycle of the switch. A number of memories may be provided, where first selected ones of the memories constitute memory groups and second selected ones of the memories constitute a memory subsets, each of the memory groups including a corresponding one of the memory subsets. The write port may supply each of a number of copies of the data units to a corresponding one of the memory subsets. Multiplexers may be associated with the groups of the memories and a read port may receive one of the copies of a number of the data units from different ones of the multiplexers. | 03-03-2011 |
| 20110083051 | INTERLEAVED CORRECTION CODE TRANSMISSION - An optical device transmits ECC codewords using an interleaved technique in which a single ECC codeword is transmitted over multiple optical links. In one particular implementation, the device may include an ECC circuit configured to supply ECC codewords in series, the codewords being generated by the ECC circuit based on input data and each of the codewords including error correction information and a portion of the data. The device may further include a serial-to-parallel circuit configured to receive each of the codewords in succession, and supply data units in parallel, each of the data units including information from a corresponding one of the codewords; an interleaver circuit to receive the data units in parallel and output a second data units in parallel, each of the second data units including bits from different ones of the data units; and a number of output lines, each of which supplying a corresponding one of the second data units. | 04-07-2011 |
| 20110235438 | TEMPORAL ALIGNMENT OF DATA UNIT GROUPS IN A SWITCH - Consistent with the present disclosure, a plurality of FIFO buffers, for example, are provided in a switch, which also includes a switch fabric. Each of the plurality of FIFOs is pre-filled with data for a duration based on a skew or time difference between the time that a data unit group is supplied to its corresponding FIFO and a reference time. The reference time is the time, for example, after a delay period has lapsed following the leading edge of a synch signal, the timing of which is a known system parameter and is used to trigger switching in the switch fabric. Typically, the delay period may be equal to the latency (often, another known system parameter) or length of time required for the data unit to propagate from an input circuit, such as a line card of the switch or another switch, to the FIFO that receives the data unit. At the reference time, temporally aligned data unit groups may be read or output from each FIFO and supplied to the switch fabric. Since the timing of the output from the FIFOs is based on known system parameters, instead of the actual arrival of the slowest data unit group at its corresponding FIFO, time aligned data unit groups may be output regardless of whether the slowest data unit group is available. | 09-29-2011 |
| 20110235646 | METHOD AND APPARATUS FOR DETERMINING PROPAGATION DELAY IN A NETWORK - A propagation delay in the transmission of a frame from an initiator node to a peer node is determined by initially identifying a frame number and byte offset of a first incoming frame from the peer node at a time when the initiator node outputs a portion of a transmitted frame. The portion of the transmitted frame may be the first byte of a sub-frame within the transmitted frame. At the peer node, the frame number and byte offset of a second frame to be supplied to the initiator node is identified at a later time when the frame portion transmitted by the initiator node is received by the peer node, and such information is transmitted to the initiator node. Thus, since the frames output and received by the initiator node are typically of fixed duration, the frame number and byte offset of the incoming frame represent the time when the initiator node outputs the frame portion (a transmit time). In addition, the frame number and byte offset of the second frame represents the time at which the frame portion is received by the peer node (a receive time). Accordingly, by comparing the frame numbers and byte offsets of the first and second frames received from the peer node, a difference between transmit and receive times or propagation delay can be obtained. | 09-29-2011 |
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| 20080273880 | Redundant channel implementation to extend optical transceiver lifetime and relibility - Embodiments introduce redundant optical channels to significantly extend the lifetime of parallel optical transceivers. A plurality of transmitters, N, transmit on a plurality of optical channels, where N is an integer number of optical channels greater than 1. One or more redundant channels, M, are also provided. N+M multiple input shift registers provide multiple paths for signals from each of the transmitters to connect to N+M laser diodes. In the event up to M of the N+M laser diodes fail, the multiple input shift registers connect the N transmitters to functioning ones of the N+M laser diodes thus extending the life of the device. A corresponding scheme is also described for the receiver side. | 11-06-2008 |
| 20110123144 | UNIVERSAL SERIAL BUS (USB) CONNECTOR HAVING AN OPTICAL-TO-ELECTICAL/ELECTRICAL-TO-OPTICAL CONVERSI0N MODULE (OE MODULE) AND HIGH-SPEED ELECTRICAL CONNECTIONS INTEGRATED THEREIN - A USB connector is provided that has an OE module and high-speed electrical connections integrated therein. The OE module includes an optical module, at least one laser diode, at least one photodiode, an optical transceiver IC, and a PCB. The optical module, the laser diode, the photodiode, and the IC are mounted on a surface of the PCB. The OE module is secured within the USB connector. The PCB includes conductive traces and electrical contact pads. The conductive traces electrically connect the IC with the contact pads. The contact pads are electrically connected via through holes formed in the PCB to the high-speed electrical connections, which, in turn, are electrically connected to conductive traces of a motherboard or a computer. | 05-26-2011 |
