Patent application number | Description | Published |
20080270955 | METHOD AND APPARATUS FOR MODIFYING EXISTING CIRCUIT DESIGN - The illustrative embodiments provide a computer implemented method and apparatus for modifying an existing circuit design. For a modification in a design of a circuit, the circuit design tool receives a code describing the modification, and a design of the circuit. The design of the circuit includes a first design, which includes a design for a number of metallic layers in the circuit. The design of the circuit further includes a second design, which includes and a design for a number of non-metallic layers in the circuit. The circuit design tool identifies a set of hooks, a set of disconnected components, and a set of filler cells in the design of the circuit. The circuit design tool produces a modification design, which is implemented in a revision of the first design, using the code, and one or more of the hooks, the disconnected components, and the filler cells. | 10-30-2008 |
20080288905 | Method and Apparatus for Congestion Based Physical Synthesis - A computer implemented method, apparatus, and computer usable program product for modifying a circuit design are provided in the illustrative embodiments. A set of candidate areas within the circuit design is identified for making a change to the circuit design. A cost associated with each candidate area in the set of candidate areas is determined to form a set of costs. The cost associated with a candidate area is the cost of making the change to the circuit design in the candidate area. Using the set of costs, a candidate area is selected from the set of candidate areas in which to make the change to the circuit design. | 11-20-2008 |
20080295051 | SLEW CONSTRAINED MINIMUM COST BUFFERING - A buffer insertion technique addresses slew constraints while minimizing buffer cost. The method builds initial solutions for the sinks, each having an associated cost, slew and capacitance. As a solution propagates toward a source, wire capacitance and wire slew are added to the solution. When a buffer is selected for possible insertion, the slew of the solution is set to zero while the cost of the solution is incremented based on the selected buffer and the capacitance is set to an intrinsic capacitance of the buffer. The solutions of two intersecting wire branches are merged by adding branch capacitances and costs, and selecting the highest branch slew. The solution sets are updated by disregarding solutions which have a slew component greater than a slew constraint, and any solution that is dominated by another solution is eliminated. The solution having the smallest cost is selected as the final solution. | 11-27-2008 |
20090089721 | METHOD FOR INCREMENTAL, TIMING-DRIVEN, PHYSICAL-SYNTHESIS OPTIMIZATION - A method, data processing system and computer program product for optimizing the placement of logic gates of a subcircuit in a physical synthesis flow. A Rip Up and Move Boxes with Linear Evaluation (RUMBLE) utility identifies movable gate(s) for timing-driven optimization. The RUMBLE utility isolates an original subcircuit corresponding to the movable gate(s) and builds an unbuffered model of the original subcircuit. Notably, a new optimized placement of the movable gate is yielded to optimize the timing (i.e., maximize the minimum slack) of the original subcircuit, while accounting for future interconnect optimizations. The new subcircuit containing the new optimized gate placement and interconnect optimization is evaluated as to whether a timing degradation exists in the new subcircuit. If a timing degradation exists in the new subcircuit, the RUMBLE utility can restore an original subcircuit and a timing state associated with the original subcircuit. | 04-02-2009 |
20090125859 | Methods for Optimal Timing-Driven Cloning Under Linear Delay Model - A timing-driven cloning method iteratively partitions sinks of the net into different sets of clusters and for each set computes a figure of merit for a cloned gate location which optimizes timing based on linear delay, that is, a delay proportional to the distance between the cloned gate location and the sinks. The set having the highest figure of merit is selected as the best solution. The original gate may also be moved to a timing-optimized location. The sinks are advantageously partitioned using boundaries of Voronoi polygons defined by a diamond region surrounding the original gate, or vice versa. The figure of merit may be for example worst slack, a sum of slacks at the sinks in the second cluster, or a linear combination of worst slack and sum of the slacks. | 05-14-2009 |
20090132970 | METHOD FOR INCREMENTAL, TIMING-DRIVEN, PHYSICAL-SYNTHESIS OPTIMIZATION UNDER A LINEAR DELAY MODEL - A method, data processing system and computer program product for optimizing the placement of logic gates of a subcircuit in a physical synthesis flow. A Pyramids utility identifies and selects movable gate(s) for timing-driven optimization. A delay pyramid and a required arrival time (RAT) surface are generated for each net in the selected subcircuit. A slack pyramid for each net is generated from the difference between the RAT surface and delay pyramid of each net. The slack pyramids are grown and tested using test points to generate a worst-case slack region based on a plurality of slack pyramids in the selected subcircuit. The worst-case slack region is mapped on a placement region and a set of coordinates representing the optimal locations of the movable element(s) in the placement region are determined and outputted. | 05-21-2009 |
20090193376 | CLOCK POWER MINIMIZATION WITH REGULAR PHYSICAL PLACEMENT OF CLOCK REPEATER COMPONENTS - Power, routability and electromigration have become crucial issues in modem microprocessor designs. In high performance designs, clocks are the highest consumer of power. Arranging clocking components with regularity so as to minimize the capacitance on the clock nets can help reduce clock power, however, it may hurt performance due to some loss of flexibility in physically placing those components. The present invention provides techniques to optimally place clock components in a regular fashion so as to minimize clock power within a performance constraint. A rectangular grid is created and clock distribution structures are assigned to the grid intersection points. Latches are then located around the clock distribution structures to minimize an overall distance for connections between the latches and respective clock distribution structures. The horizontal and vertical pitches of the grid may be independently adjusted to achieve a more uniform spread of the clock distribution structures. | 07-30-2009 |
20090193377 | REGULAR LOCAL CLOCK BUFFER PLACEMENT AND LATCH CLUSTERING BY ITERATIVE OPTIMIZATION - Power, routability and electromigration have become crucial issues in modem microprocessor designs. In high performance designs, clocks are the highest consumer of power. Arranging clocking components with regularity so as to minimize the capacitance of the clock nets can help reduce clock power, however, it may hurt performance due to some loss of flexibility in physically placing those components. The present invention provides techniques to optimally design a clock network by logically assigning clusters of the latches to respective clock distribution structures, placing clock pins at favored pin locations, and placing clock distribution structures directly underneath the clock pins. The clock distribution structures may be moved to favored distribution locations along the clock stripes, and new optimal clustering generated between the latches and the clock distribution structures. These three optimizations are preferably repeated iteratively to derive a local optimal solution for the clock network. | 07-30-2009 |
20100199243 | METHOD AND SYSTEM FOR POINT-TO-POINT FAST DELAY ESTIMATION FOR VLSI CIRCUITS - The present disclosure is directed to a method for estimating an interconnect delay for a source-to-sink path of a net within a Very Large Scale Integration (VLSI) circuit, the source-to-sink path connecting a source and a sink in the net. The method may comprise estimating a total wire capacitance; calculating a delay contribution based on delay of the source-to-sink path and delay of a plurality of off-path sinks; and estimating the interconnect delay for the source-to-sink path based on the delay contribution. | 08-05-2010 |
20100223586 | TECHNIQUES FOR PARALLEL BUFFER INSERTION - The present disclosure is directed to a method for determining a plurality of buffer insertion locations in a net for an integrated circuit design. The method may comprise calculating a plurality of resistive-capacitive (RC) influences in parallel, each RC influence corresponding to one of a plurality of buffering options available for a first sub-tree for the addition of a wire segment to the first sub-tree; updating the plurality of RC influences for the addition of a buffer for the first sub-tree, the buffer comprising one of a plurality of buffer types; and merging the first sub-tree with a second sub-tree in parallel by grouping the plurality of buffering options available for the first sub-tree and a plurality of buffering options available for the second sub-tree into a plurality of merging groups, and merging at least two groups of the plurality of merging groups in parallel. | 09-02-2010 |
20110154280 | PROPAGATING DESIGN TOLERANCES TO SHAPE TOLERANCES FOR LITHOGRAPHY - An approach is provided that computes electrical delay ranges that correspond to a number of shapes included in a hardware design layout. The electrical delay ranges are converted to shape tolerances for each of the shapes. A lithography mask of the hardware design layout is generated using the shape tolerances so that the images of the shapes in the mask produced lie within the shape tolerances that correspond to the respective shape. | 06-23-2011 |
20110320992 | BUFFER-AWARE ROUTING IN INTEGRATED CIRCUIT DESIGN - A method, system, and computer usable program product for buffer-aware routing in integrated circuit design are provided in the illustrative embodiments. The design has cells, and the circuit includes buffers and wires. A route is received from a set of routes. The route couples a first point in the circuit to a second point in the circuit and including at least one buffer between the first point and the second point. A determination is made whether the route violates a set of hard constraints for a part of the circuit, where the set of hard constraints includes a reach length constraint. In response to the route not violating any hard constraint in the set of hard constraints, the route is selected as a buffer-aware routing solution between the first and the second points in the circuit. | 12-29-2011 |
20120017186 | SPECIFYING CIRCUIT LEVEL CONNECTIVITY DURING CIRCUIT DESIGN SYNTHESIS - Exemplary embodiments include a method for modifying a circuit synthesis flow having automated instructions, the method including receiving circuit design input for a circuit design, receiving custom specifications to the circuit design input, synthesizing high level logic from the circuit design input, placing logic on the circuit design, refining the circuit design and generating a circuit description from the circuit design. | 01-19-2012 |
20120110532 | LATCH CLUSTERING WITH PROXIMITY TO LOCAL CLOCK BUFFERS - A method, system, and computer usable program product for latch clustering with proximity to local clock buffers (LCBs) where an algorithm is used to cluster a plurality of latches into a first plurality of groups in an integrated circuit. A number of groups in the first plurality of groups of clustered latches is determined. A plurality of LCBs are added where a number of added LCBs is the same as the number of groups in the first plurality of groups. A cluster radius for a subset of the first plurality of groups of clustered latches is determined, a group in the subset having a cluster radius that is a maximum cluster radius in the subset. The plurality of latches are reclustered into a second plurality of groups responsive to the maximum cluster radius exceeding a radius threshold, the second plurality of groups exceeding the first plurality of groups by one. | 05-03-2012 |
20120124539 | Clock Optimization with Local Clock Buffer Control Optimization - A physical synthesis tool for dock optimization with local clock buffer control optimization is provided. The physical synthesis flow consists of delaying the exposure of clock routes until after the clock optimization placement stage. The physical synthesis tool clones first local clock buffers. Then, the physical synthesis tool runs timing analysis on the whole design to compute the impact of this necessarily disruptive step. After cloning local clock buffers, the physical synthesis tool adds an extra optimization step to target the control signals that drive the local clock buffers. This optimization step may includes latch cloning, timing-driven placement, buffer insertion, and repowering. The flow alleviates high-fanout nets and produces significantly better timing going into clock optimization placement. After placement, the physical synthesis tool fixes latches and local clock buffers in place, inserts clock routes, and repowers local clock buffers. | 05-17-2012 |
20120240093 | ROUTING AND TIMING USING LAYER RANGES - A method, system, and computer program product for improved routing using layer ranges in the design of an integrated circuit (IC) are provided in the illustrative embodiments. Using an application executing in a data processing system, a score is computed for a net in a set of nets routed using a set of layers in the design. The set of nets is sorted according to scores associated with nets in the set of nets. A layer range from a set of layer ranges is assigned to a net in the sorted list such that a net with a higher than threshold score is assigned a high layer range. | 09-20-2012 |
20120324409 | ACCURACY PIN-SLEW MODE FOR GATE DELAY CALCULATION - The input slew at a selected gate of an integrated circuit design is computed by assigning a default slew rate to the output gate of a previous logic stage which is greater than a median slew rate for the design. This default slew rate is propagated through the logic stage to generate an input slew rate at the selected gate. The default slew rate corresponds to a predetermined percentile applied to a limited sample of preliminary slew rates for randomly selected gates in the design. The default slew rate is adjusted as a function of known characteristics of the wirelength from the output gate to a first gate in the second logic stage. The delay of the selected gate is calculated based on the input slew rate. The input slew rate can be stored during one optimization iteration and used as a default slew rate during a later optimization iteration. | 12-20-2012 |
20130086544 | CONSIDERATION OF LOCAL ROUTING AND PIN ACCESS DURING VLSI GLOBAL ROUTING - Global routing and congestion evaluation is enhanced by including consideration of local routing and pin access. Pin information is computed for each global edge based on adjacent tiles, and the wiring track capacity for an edge is reduced based on the pin information. After global routing, the wiring track capacities are increased by previous reduction amounts for detailed routing. The pin information can include pin count for an associated tile, the Steiner tree length for the pins, or relative locations of the pins. Wiring track capacities are preferably reduced by creating blockages in tracks of a particular metal layer of the circuit design used for logic gates of the pins. The blockage tracks can be spread evenly across the wiring tracks of a given edge. | 04-04-2013 |
20130086545 | EVALUATING ROUTING CONGESTION BASED ON AVERAGE GLOBAL EDGE CONGESTION HISTOGRAMS - Global routing congestion in an integrated circuit design is characterized by computing global edge congestions and constructing a histogram of averages of the global edge congestions for varying percentages of worst edge congestion, e.g., 0.5%, 1%, 2%, 5%, 10% and 20%. Horizontal and vertical global edges are handled separately. Global edges near blockages can be skipped to avoid false congestion hotspots. The histogram of the current global routing can be compared to a histogram for a previous global routing to select a best routing solution. The histograms can also be used in conjunction with congestion-driven physical synthesis tools. | 04-04-2013 |
20130272126 | CONGESTION AWARE ROUTING USING RANDOM POINTS - In congestion aware point-to-point routing using a random point in an integrated circuit (IC) design, the random point is selected in a bounding area defined in a layout of the IC design. A set of pattern routes is constructed between a source pin and a sink pin in the bounding area, a pattern route in the set of pattern routes passing through the random point. A set of congestion cost corresponding to the set of pattern routes is computed. A congestion cost in the set of congestion costs corresponds to a pattern route in the set of pattern routes. A preferred pattern route is selected from the set of pattern routes, the preferred pattern route having the smallest congestion cost in the set of congestion costs. The preferred pattern route is output as a point-to-point route between the source pin and the sink pin. | 10-17-2013 |
20130275934 | SOLVING CONGESTION USING NET GROUPING - A method, system, and computer program product for solving a congestion problem in an integrated circuit (IC) design are provided in the illustrative embodiments. A congested g-edge is selected from a set of congested g-edges. A set of congesting nets is selected, wherein the set of congesting nets cause congestion in the selected congested g-edges by crossing the selected congested g-edge. A vacancy data structure corresponding to the selected congested g-edge is populated. A subset of the set of the congesting nets is selected. The subset of the set of the congesting nets is rerouted to a candidate g-edge identified in the vacancy data structure. | 10-17-2013 |
20130326455 | ELEMENT PLACEMENT IN CIRCUIT DESIGN BASED ON PREFERRED LOCATION - An improved circuit design system may include a computer processor to perform a placement for a circuit by physical synthesis. The system may also include a controller to compute a preferred location of at least one selected element of the circuit, and to calculate placement constraints for each selected element. The system may further include an updated design for the circuit generated by performing another round of physical synthesis with the placement constraints. | 12-05-2013 |
20130326456 | DESIGNING A ROBUST POWER EFFICIENT CLOCK DISTRIBUTION NETWORK - An electronic automation design tool with a sink locator unit creates clusters of loads from a plurality of loads within a sector of a clock network design based on balancing magnitudes of the loads among the clusters of loads and based on minimal delays of each of the clusters and respective ones of a plurality of sink locations in the sector of the clock network design. The tool determines centers of the clusters of loads, and sink locations corresponding to the centers of the clusters for connecting output terminal points of sector buffers are determined. Each of the sector buffers drive a clock signal to a corresponding one of the clusters of loads. | 12-05-2013 |
20140007034 | ROUTING OF LOCAL CLOCK INTERCONNECTS | 01-02-2014 |
20140071827 | SOLVING NETWORK TRAFFIC CONGESTION USING DEVICE GROUPING - A method, system, and computer program product for solving a network traffic congestion problem are provided in the illustrative embodiments. Using an application executing using a processor and a memory in a data processing system, a congested network route section is selected from a set of congested network route sections. A set of congesting devices is selected, where the set of congesting devices causes congestion in the selected congested network route sections by using the selected congested network route section. A vacancy data structure corresponding to the selected congested network route section is populated. A subset of the set of the congesting devices is selected. The subset of the set of the congesting devices is rerouted to a candidate network route section identified in the vacancy data structure. | 03-13-2014 |
20140074389 | SOLVING TRAFFIC CONGESTION USING VEHICLE GROUPING - A method, system, and computer program product for solving a traffic congestion problem are provided in the illustrative embodiments. Using an application executing using a processor and a memory in a data processing system, a congested route section is selected from a set of congested route sections. A set of congesting vehicles is selected, where the set of congesting vehicles cause congestion in the selected congested route sections by being positioned on the selected congested route section. A vacancy data structure corresponding to the selected congested route section is populated. A subset of the set of the congesting vehicles is selected. The subset of the set of the congesting vehicles is rerouted to a candidate route section identified in the vacancy data structure. | 03-13-2014 |
20140081478 | SOLVING TRAFFIC CONGESTION USING VEHICLE GROUPING - A method, system, and computer program product for solving a traffic congestion problem are provided in the illustrative embodiments. Using an application executing using a processor and a memory in a data processing system, a congested route section is selected from a set of congested route sections. A set of congesting vehicles is selected, where the set of congesting vehicles cause congestion in the selected congested route sections by being positioned on the selected congested route section. A vacancy data structure corresponding to the selected congested route section is populated. A subset of the set of the congesting vehicles is selected. The subset of the set of the congesting vehicles is rerouted to a candidate route section identified in the vacancy data structure. | 03-20-2014 |
20140088791 | SOLVING TRAFFIC CONGESTION USING VEHICLE GROUPING - A method, system, and computer program product for solving a traffic congestion problem are provided in the illustrative embodiments. Using an application executing using a processor and a memory in a data processing system, a congested route section is selected from a set of congested route sections. A set of congesting vehicles is selected, where the set of congesting vehicles cause congestion in the selected congested route sections by being positioned on the selected congested route section. A vacancy data structure corresponding to the selected congested route section is populated. A subset of the set of the congesting vehicles is selected. The subset of the set of the congesting vehicles is rerouted to a candidate route section identified in the vacancy data structure. | 03-27-2014 |
20140143746 | DIRECT CURRENT CIRCUIT ANALYSIS BASED CLOCK NETWORK DESIGN - A design tool with a direct current (DC) transformation analysis unit determines combinations of candidate sink locations for sector buffers within a sector of a clock network design. For each of the combination of candidate sink locations, the design tool transforms resistances of the sector with the combination of candidate sink locations into resistances of an electrical circuit. The design tool transforms capacitances of the sector with the combination of candidate sink locations into current sources of an electrical circuit. The design tool performs a DC circuit analysis, wherein results of the DC circuit analysis include a variance of voltage at nodes of the sector and a maximum value of current from currents flowing between pairs of the nodes of the sector. The design tool determines which of the combination of candidate sink locations has the minimum variance of voltage with the results of the DC circuit analysis. | 05-22-2014 |
20140149957 | STRUCTURED PLACEMENT OF LATCHES/FLIP-FLOPS TO MINIMIZE CLOCK POWER IN HIGH-PERFORMANCE DESIGNS - A latch placement tool determines a shape for a cluster of latches from a preliminary layout (or based on a netlist), including an aspect ratio of the shape, and generates a template for placement of the latches in conformity with the shape. Latches are placed around a local clock buffer (LCB) based on latch size, from largest latch first to smallest latch last, and based on their ideal locations given the target aspect ratio. The ideal locations may be further based on the clock driver pin configuration of the LCB. The final template preferably has an aspect ratio that is approximately equal to the aspect ratio of the shape of the cluster, but the latch placement may be constrained by clock routing topology. Latch placement within a cluster can be further optimized by swapping one of the latches with another to minimize total wirelength of the design. | 05-29-2014 |
20140181772 | DETERMINING HIGH QUALITY INITIAL CANDIDATE SINK LOCATIONS FOR ROBUST CLOCK NETWORK DESIGN - A design tool with an initial sink locator unit determines a number of clock buffers for driving clock signals to loads in a clock distribution network. The design tool determines clusters of loads in the clock distribution network, wherein the number of clusters is equal to the number of clock buffers and the loads are uniformly distributed amongst the clusters. The design tool determines centers of the clusters as initial candidate sink locations for the clock buffers. The design tool iteratively determines new clusters and determines centers of the new clusters as optimized initial candidate sink locations. | 06-26-2014 |
20140195998 | Automatic Generation of Wire Tag Lists for a Metal Stack - Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition. The mechanisms generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library. In addition, the mechanisms store the pruned layer trait library for performing wire routing of an integrated circuit design. | 07-10-2014 |
20140223397 | Automatic Generation of Wire Tag Lists for a Metal Stack - Mechanisms are provided for pruning a layer trait library for use in wire routing in an integrated circuit design process. The mechanisms receive a plurality of wirecodes and a metal stack definition. The mechanisms generate a verbose layer trait library based on all possible combinations of the wirecodes and layers of the metal stack definition. The mechanisms generate a pruned layer trait library by pruning the verbose layer trait library to remove redundant layer traits from the verbose layer trait library. In addition, the mechanisms store the pruned layer trait library for performing wire routing of an integrated circuit design. | 08-07-2014 |