| Patent application number | Description | Published |
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| 20080270955 | METHOD AND APPARATUS FOR MODIFYING EXISTING CIRCUIT DESIGN - The illustrative embodiments provide a computer implemented method and apparatus for modifying an existing circuit design. For a modification in a design of a circuit, the circuit design tool receives a code describing the modification, and a design of the circuit. The design of the circuit includes a first design, which includes a design for a number of metallic layers in the circuit. The design of the circuit further includes a second design, which includes and a design for a number of non-metallic layers in the circuit. The circuit design tool identifies a set of hooks, a set of disconnected components, and a set of filler cells in the design of the circuit. The circuit design tool produces a modification design, which is implemented in a revision of the first design, using the code, and one or more of the hooks, the disconnected components, and the filler cells. | 10-30-2008 |
| 20080288905 | Method and Apparatus for Congestion Based Physical Synthesis - A computer implemented method, apparatus, and computer usable program product for modifying a circuit design are provided in the illustrative embodiments. A set of candidate areas within the circuit design is identified for making a change to the circuit design. A cost associated with each candidate area in the set of candidate areas is determined to form a set of costs. The cost associated with a candidate area is the cost of making the change to the circuit design in the candidate area. Using the set of costs, a candidate area is selected from the set of candidate areas in which to make the change to the circuit design. | 11-20-2008 |
| 20080295051 | SLEW CONSTRAINED MINIMUM COST BUFFERING - A buffer insertion technique addresses slew constraints while minimizing buffer cost. The method builds initial solutions for the sinks, each having an associated cost, slew and capacitance. As a solution propagates toward a source, wire capacitance and wire slew are added to the solution. When a buffer is selected for possible insertion, the slew of the solution is set to zero while the cost of the solution is incremented based on the selected buffer and the capacitance is set to an intrinsic capacitance of the buffer. The solutions of two intersecting wire branches are merged by adding branch capacitances and costs, and selecting the highest branch slew. The solution sets are updated by disregarding solutions which have a slew component greater than a slew constraint, and any solution that is dominated by another solution is eliminated. The solution having the smallest cost is selected as the final solution. | 11-27-2008 |
| 20090089721 | METHOD FOR INCREMENTAL, TIMING-DRIVEN, PHYSICAL-SYNTHESIS OPTIMIZATION - A method, data processing system and computer program product for optimizing the placement of logic gates of a subcircuit in a physical synthesis flow. A Rip Up and Move Boxes with Linear Evaluation (RUMBLE) utility identifies movable gate(s) for timing-driven optimization. The RUMBLE utility isolates an original subcircuit corresponding to the movable gate(s) and builds an unbuffered model of the original subcircuit. Notably, a new optimized placement of the movable gate is yielded to optimize the timing (i.e., maximize the minimum slack) of the original subcircuit, while accounting for future interconnect optimizations. The new subcircuit containing the new optimized gate placement and interconnect optimization is evaluated as to whether a timing degradation exists in the new subcircuit. If a timing degradation exists in the new subcircuit, the RUMBLE utility can restore an original subcircuit and a timing state associated with the original subcircuit. | 04-02-2009 |
| 20090125859 | Methods for Optimal Timing-Driven Cloning Under Linear Delay Model - A timing-driven cloning method iteratively partitions sinks of the net into different sets of clusters and for each set computes a figure of merit for a cloned gate location which optimizes timing based on linear delay, that is, a delay proportional to the distance between the cloned gate location and the sinks. The set having the highest figure of merit is selected as the best solution. The original gate may also be moved to a timing-optimized location. The sinks are advantageously partitioned using boundaries of Voronoi polygons defined by a diamond region surrounding the original gate, or vice versa. The figure of merit may be for example worst slack, a sum of slacks at the sinks in the second cluster, or a linear combination of worst slack and sum of the slacks. | 05-14-2009 |
| 20090132970 | METHOD FOR INCREMENTAL, TIMING-DRIVEN, PHYSICAL-SYNTHESIS OPTIMIZATION UNDER A LINEAR DELAY MODEL - A method, data processing system and computer program product for optimizing the placement of logic gates of a subcircuit in a physical synthesis flow. A Pyramids utility identifies and selects movable gate(s) for timing-driven optimization. A delay pyramid and a required arrival time (RAT) surface are generated for each net in the selected subcircuit. A slack pyramid for each net is generated from the difference between the RAT surface and delay pyramid of each net. The slack pyramids are grown and tested using test points to generate a worst-case slack region based on a plurality of slack pyramids in the selected subcircuit. The worst-case slack region is mapped on a placement region and a set of coordinates representing the optimal locations of the movable element(s) in the placement region are determined and outputted. | 05-21-2009 |
| 20090193376 | CLOCK POWER MINIMIZATION WITH REGULAR PHYSICAL PLACEMENT OF CLOCK REPEATER COMPONENTS - Power, routability and electromigration have become crucial issues in modem microprocessor designs. In high performance designs, clocks are the highest consumer of power. Arranging clocking components with regularity so as to minimize the capacitance on the clock nets can help reduce clock power, however, it may hurt performance due to some loss of flexibility in physically placing those components. The present invention provides techniques to optimally place clock components in a regular fashion so as to minimize clock power within a performance constraint. A rectangular grid is created and clock distribution structures are assigned to the grid intersection points. Latches are then located around the clock distribution structures to minimize an overall distance for connections between the latches and respective clock distribution structures. The horizontal and vertical pitches of the grid may be independently adjusted to achieve a more uniform spread of the clock distribution structures. | 07-30-2009 |
| 20090193377 | REGULAR LOCAL CLOCK BUFFER PLACEMENT AND LATCH CLUSTERING BY ITERATIVE OPTIMIZATION - Power, routability and electromigration have become crucial issues in modem microprocessor designs. In high performance designs, clocks are the highest consumer of power. Arranging clocking components with regularity so as to minimize the capacitance of the clock nets can help reduce clock power, however, it may hurt performance due to some loss of flexibility in physically placing those components. The present invention provides techniques to optimally design a clock network by logically assigning clusters of the latches to respective clock distribution structures, placing clock pins at favored pin locations, and placing clock distribution structures directly underneath the clock pins. The clock distribution structures may be moved to favored distribution locations along the clock stripes, and new optimal clustering generated between the latches and the clock distribution structures. These three optimizations are preferably repeated iteratively to derive a local optimal solution for the clock network. | 07-30-2009 |
| 20100199243 | METHOD AND SYSTEM FOR POINT-TO-POINT FAST DELAY ESTIMATION FOR VLSI CIRCUITS - The present disclosure is directed to a method for estimating an interconnect delay for a source-to-sink path of a net within a Very Large Scale Integration (VLSI) circuit, the source-to-sink path connecting a source and a sink in the net. The method may comprise estimating a total wire capacitance; calculating a delay contribution based on delay of the source-to-sink path and delay of a plurality of off-path sinks; and estimating the interconnect delay for the source-to-sink path based on the delay contribution. | 08-05-2010 |
| 20100223586 | TECHNIQUES FOR PARALLEL BUFFER INSERTION - The present disclosure is directed to a method for determining a plurality of buffer insertion locations in a net for an integrated circuit design. The method may comprise calculating a plurality of resistive-capacitive (RC) influences in parallel, each RC influence corresponding to one of a plurality of buffering options available for a first sub-tree for the addition of a wire segment to the first sub-tree; updating the plurality of RC influences for the addition of a buffer for the first sub-tree, the buffer comprising one of a plurality of buffer types; and merging the first sub-tree with a second sub-tree in parallel by grouping the plurality of buffering options available for the first sub-tree and a plurality of buffering options available for the second sub-tree into a plurality of merging groups, and merging at least two groups of the plurality of merging groups in parallel. | 09-02-2010 |
| 20110154280 | PROPAGATING DESIGN TOLERANCES TO SHAPE TOLERANCES FOR LITHOGRAPHY - An approach is provided that computes electrical delay ranges that correspond to a number of shapes included in a hardware design layout. The electrical delay ranges are converted to shape tolerances for each of the shapes. A lithography mask of the hardware design layout is generated using the shape tolerances so that the images of the shapes in the mask produced lie within the shape tolerances that correspond to the respective shape. | 06-23-2011 |
