Patent application number | Description | Published |
20130239071 | METHOD AND APPARATUS FOR ENHANCED OPTICAL PROXIMITY CORRECTION - Provided is an integrated circuit (IC) design method. The method includes receiving an IC design layout having a feature with an outer boundary, performing a dissection on the feature to divide the outer boundary into a plurality of segments, and performing, using the segments, an optical proximity correction (OPC) on the feature to generate a modified outer boundary. The method also includes simulating a photolithography exposure of the feature with the modified outer boundary to create a contour and performing an OPC evaluation to determine if the contour is within a threshold. Additionally, the method includes repeating the performing a dissection, the performing an optical proximity correction, and the simulating if the contour does not meet the threshold, wherein each repeated dissection and each repeated optical proximity correction is performed on the modified outer boundary generated by the previously performed optical proximity correction. | 09-12-2013 |
20150017571 | PHOTOLITHOGRPAHY SCATTERING BAR STRUCTURE AND METHOD - Provided is an integrated circuit (IC) photo mask. The IC photo mask includes a main feature of the IC, the main feature having a plurality of sides, and a plurality of assist features, the assist features being spaced from each other and spaced from the main feature, wherein each one of the assist features is adjacent to one of the sides, each one of the assist features has an elongated shape along a direction, whereby extending the shape in the direction would intersect at least another one of the assist features and the assist features are sub-resolution correction features for correcting for optical proximity effect in a photolithography process. | 01-15-2015 |
20150040081 | Method and Apparatus for Integrated Circuit Mask Patterning - Provided is an integrated circuit (IC) design method. The method includes receiving a design layout of the IC, the design layout having a first main feature, and adding a negative assist feature to the design layout, wherein the negative assist feature has a first width, the negative assist feature divides the first main feature into a second main feature and a third main feature by the first width, and the first width is sub-resolution in a photolithography process. | 02-05-2015 |
20150082265 | DESIGN STRUCTURE FOR CHIP EXTENSION - One embodiment relates to a method of achieving an circuit dimension which is greater than a size of an exposure field of an illumination tool. A first area of a first reticle field and a second area of a second reticle field are defined. An extension zone is created as a region outside the first area, and includes a first layout shape formed on a first design level. A corresponding forbidden zone is created for the second reticle field as a region inside the second area where no layout shape on the first design level is permitted. A second layout shape is formed on a second design level within the forbidden zone. The first and second areas are then abutted. Upon abutment of the first and second areas, the second layout shape overlaps the first layout shape to form a connection between circuitry of the first and second reticle fields. | 03-19-2015 |
20150106771 | METHOD OF LITHOGRAPHIC PROCESS EVALUATION - Some embodiments of the present disclosure relate to a method to simulate patterning of a layout. The method comprises simulating formation of a layout pattern under a first lithography condition. The first lithography condition comprises a set of parameters, wherein a value of each parameter is defined by a corresponding process model. The method further comprises randomly varying the value of each parameter of the first lithography condition within a range of values defined by the corresponding process model of the parameter, to create a second lithography condition. Formation of a layout pattern is then re-simulated under the second lithography condition. Random variation of the value of each parameter is repeated to create additional lithography conditions. And, each lithography condition is re-simulated until the value of each parameter has been substantially varied across a range of its respective process model. | 04-16-2015 |
Patent application number | Description | Published |
20090020838 | APPARATUS AND METHOD FOR REDUCING OPTICAL CROSS-TALK IN IMAGE SENSORS - An image sensor device includes a semiconductor substrate having a front surface and a back surface; an array of pixels formed on the front surface of the semiconductor substrate, each pixel being adapted for sensing light radiation; an array of color filters formed over the plurality of pixels, each color filter being adapted for allowing a wavelength of light radiation to reach at least one of the plurality of pixels; and an array of micro-lens formed over the array of color filters, each micro-lens being adapted for directing light radiation to at least one of the color filters in the array. The array of color filters includes structure adapted for blocking light radiation that is traveling towards a region between adjacent micro-lens. | 01-22-2009 |
20120007156 | METHOD AND STRUCTURE TO REDUCE DARK CURRENT IN IMAGE SENSORS - A method to fabricate an image sensor includes providing a semiconductor substrate having a pixel region and a periphery region, forming a light sensing element on the pixel region, and forming at least one transistor in the pixel region and at least one transistor in the periphery region. The step of forming the at least one transistor in the pixel region and periphery region includes forming a gate electrode in the pixel region and periphery region, depositing a dielectric layer over the pixel region and periphery region, partially etching the dielectric layer to form sidewall spacers on the gate electrode and leaving a portion of the dielectric layer overlying the pixel region, and forming source/drain (S/D) regions by ion implantation. | 01-12-2012 |
20130147993 | Apparatus and Method for Reducing Optical Cross-Talk in Image Sensors - An image sensor device includes a semiconductor substrate having a front surface and a back surface; an array of pixels formed on the front surface of the semiconductor substrate, each pixel being adapted for sensing light radiation; an array of color filters formed over the plurality of pixels, each color filter being adapted for allowing a wavelength of light radiation to reach at least one of the plurality of pixels; and an array of micro-lens formed over the array of color filters, each micro-lens being adapted for directing light radiation to at least one of the color filters in the array. The array of color filters includes structure adapted for blocking light radiation that is traveling towards a region between adjacent micro-lens. | 06-13-2013 |
20130185479 | DATA PROTECTING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS - A data protecting method for protecting a sub-directory and at least one pre-stored file in a rewritable non-volatile memory module is provided. The method includes receiving a write command from a host system and determining whether a write address indicated by the write command is an address storing a file description block of the sub-directory. The method also includes, when the write address is the address storing a file description block of the sub-directory, determining whether a portion of data streams corresponding to the write command is the same as a corresponding content recorded in the file description block of the sub-directory. The method further includes, when the portion of data streams corresponding to the write command is not the same as the corresponding content recorded in the file description block of the sub-directory, transmitting a write failure signal to the host system. | 07-18-2013 |
20150175406 | SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING - A semiconductor device includes a device substrate and a conductive capping substrate. The device substrate includes at least one micro-electro mechanical system (MEMS) device. The conductive capping substrate is bonded to the device substrate and includes a cap portion covering the MEMS device, and a conductor portion in electrical contact with the device substrate. | 06-25-2015 |