Patent application number | Description | Published |
20080233722 | METHOD OF FORMING SELECTIVE AREA COMPOUND SEMICONDUCTOR EPITAXIAL LAYER - A method of forming a selective area semiconductor compound epitaxy layer is provided. The method includes the step of using two silicon-containing precursors as gas source for implementing a process of manufacturing the selective area semiconductor compound epitaxy layer, so as to form a semiconductor compound epitaxy layer on an exposed monocrystalline silicon region of a substrate. | 09-25-2008 |
20080293222 | METHOD FOR FORMING SILICON-GERMANIUM EPITAXIAL LAYER - A method for forming a SiGe epitaxial layer is described. A first SEG process is performed under a first condition, consuming about 1% to 20% of the total process time for forming the SiGe epitaxial layer. Then, a second SEG process is performed under a second condition, consuming about 99% to 80% of the total process time. The first condition and the second condition include different temperatures or pressures. The first and the second SEG processes each uses a reactant gas that includes at least a Si-containing gas and a Ge-containing gas. | 11-27-2008 |
20120292638 | PROCESS FOR MANUFACTURING STRESS-PROVIDING STRUCTURE AND SEMICONDUCTOR DEVICE WITH SUCH STRESS-PROVIDING STRUCTURE - A process for manufacturing a stress-providing structure is applied to the fabrication of a semiconductor device. Firstly, a substrate with a channel structure is provided. A silicon nitride layer is formed over the substrate by chemical vapor deposition in a halogen-containing environment. An etching process is performed to partially remove the silicon nitride layer to expose a portion of a surface of the substrate beside the channel structure. The exposed surface of the substrate is etched to form a recess in the substrate. Then, the substrate is thermally treated at a temperature between 750° C. and 820° C. After the substrate is thermally treated, a stress-providing material is filled in the recess to form a stress-providing structure within the recess. The semiconductor device includes a substrate, a recess and a stress-providing structure. The recess has a round inner surface. The stress-providing structure has a round outer surface. | 11-22-2012 |
20130026464 | TEST PATTERN FOR MEASURING SEMICONDUCTOR ALLOYS USING X-RAY DIFFRACTION - A test pattern for measuring semiconductor alloys using X-ray diffraction (XRD) includes a first region to an Nth region defined on a wafer, and a plurality of test structures positioned in the first region and so forth up to in the Nth region. The test structures in the same region have sizes identical to each other and the test structures in different regions have sizes different from each other. | 01-31-2013 |
20130026538 | SEMICONDUCTOR DEVICE HAVING EPITAXIAL STRUCTURES - A semiconductor device having epitaxial structures includes a gate structure positioned on a substrate, epitaxial structures formed in the substrate at two sides of the gate structure, and an undoped cap layer formed on the epitaxial structures. The epitaxial structures include a dopant, a first semiconductor material having a first lattice constant, and a second semiconductor material having a second lattice constant, and the second lattice constant is larger than the first lattice constant. The undoped cap layer also includes the first semiconductor material and the second semiconductor material. The second semiconductor material in the epitaxial structures includes a first concentration, the second semiconductor material in the undoped cap layer includes at least a first concentration, and the second concentration is lower than the first concentration. | 01-31-2013 |
20130052778 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate. An oxide layer is formed on the substrate without the fin-shaped structure being formed thereon. A gate is formed to cover a part of the oxide layer and a part of the fin-shaped structure. An etching process is performed to etch a part of the fin-shaped structure beside the gate, therefore at least a recess is formed in the fin-shaped structure. An epitaxial process is performed to form an epitaxial layer in the recess, wherein the epitaxial layer has a hexagon-shaped profile structure. | 02-28-2013 |
20130069172 | SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME - A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a gate structure, a source region and a drain region. The gate structure is disposed on a substrate. The source and drain regions disposed at respective sides of the gate structure include a boron-doped silicon germanium (SiGeB) layer substantially without stress relaxation. The boron-doped silicon germanium (SiGeB) layer has a germanium concentration greater than 30 at % and an in-situ doping concentration of boron ranging between 2.65×10 | 03-21-2013 |
20130092954 | Strained Silicon Channel Semiconductor Structure and Method of Making the Same - A method for fabricating a strained channel semiconductor structure includes providing a substrate, forming at least one gate structure on said substrate, performing an etching process to form two recesses in said substrate at opposites sides of said gate structure, the sidewall of said recess being concaved in the direction to said gate structure and forming an included angle with respect to horizontal plane, and performing a pre-bake process to modify the recess such that said included angle between the sidewall of said recess and the horizontal plane is increased. | 04-18-2013 |
20130105861 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING EPITAXIAL LAYER | 05-02-2013 |
20130122691 | METHOD FOR MAKING SEMICONDUCTOR STRUCTURE - A method for forming a semiconductor structure is provided. First, multiple recesses are formed in a substrate. Second, a precursor mixture is provided to form a non-doped epitaxial layer on the inner surface of the recesses. The precursor mixture includes a silicon precursor, an epitaxial material precursor and a hydrogen-halogen compound. The flow rate ratio of the silicon precursor to the epitaxial material precursor is greater than 1.7. Later, a doped epitaxial layer including Si, the epitaxial material and the dopant is formed and substantially fills up the recess. | 05-16-2013 |
20130122698 | METHOD FOR MANUFACTURING MULTI-GATE TRANSISTOR DEVICE - A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer and a patterned hard mask sequentially formed thereon, removing the patterned hard mask, performing a thermal treatment to rounding the patterned semiconductor layer with a process temperature lower than 800° C., and sequentially forming a gate dielectric layer and a gate layer covering a portion of the patterned semiconductor layer on the semiconductor substrate. | 05-16-2013 |
20130126949 | MOS DEVICE AND METHOD FOR FABRICATING THE SAME - A method for fabricating a metal oxide semiconductor (MOS) device is described, including following steps. Two recesses are formed in a substrate. A first epitaxy growth process is performed, so as to form a first semiconductor compound layer in each of the recesses. A second epitaxy growth process is performed with an epitaxial temperature lower than 700° C., so as to form a cap layer on each of the first semiconductor compound layers. Each of the cap layers includes a second semiconductor compound layer protruding from a surface of the substrate. The first and the second semiconductor compound layers are composed of a first Group IV element and a second Group IV element, wherein the second Group IV element is a nonsilicon element. The content of the second Group IV element in the second semiconductor compound layers is less than that in the first semiconductor compound layers. | 05-23-2013 |
20130137243 | SEMICONDUCTOR PROCESS - First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below −30° C. | 05-30-2013 |
20130256701 | STRAINED SILICON CHANNEL SEMICONDUCTOR STRUCTURE - A strained silicon channel semiconductor structure comprises a substrate having an upper surface, a gate structure formed on the upper surface, at least one recess formed in the substrate at lateral sides of the gate structure, wherein the recess has at least one sidewall which has an upper sidewall and a lower sidewall concaved in the direction to the gate structure, and the included angle between the upper sidewall and horizontal plane ranges between 54.5°-90°, and an epitaxial layer filled into the two recesses. | 10-03-2013 |
20130264585 | SEMICONDUCTOR DEVICE WITH STRESS-PROVIDING STRUCTURE - A semiconductor device is provided. The semiconductor device includes a substrate, a recess and a stress-providing structure. A channel structure is formed in the substrate. The recess is formed in the substrate and arranged beside the channel structure. The recess has a round inner surface. The stress-providing structure is formed within the recess. Corresponding to the profile of the round inner surface of the recess, the stress-providing structure has a round outer surface. | 10-10-2013 |
20130264613 | SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF - A semiconductor structure includes agate structure, an epitaxial layer and a carbon-containing silicon germanium cap layer. The gate structure is located on a substrate. The epitaxial layer is located in the substrate beside the gate structure. The carbon-containing silicon germanium cap layer is located on the epitaxial layer. Otherwise, semiconductor processes for forming said semiconductor structure are also provided. | 10-10-2013 |
20130288448 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A semiconductor substrate is provided. The semiconductor substrate has a patterned isolation layer and the patterned isolation layer has an opening exposing a silicon area of the semiconductor substrate. A silicon rich layer is formed on the sidewalls of the opening. An epitaxial process is performed to form an epitaxial structure on the silicon area in the opening. | 10-31-2013 |
20130330898 | MOS TRANSISTOR PROCESS - A MOS transistor process includes the following steps. A gate structure is formed on a substrate. A source/drain is formed in the substrate beside the gate structure. After the source/drain is formed, (1) at least a recess is formed in the substrate beside the gate structure. An epitaxial structure is formed in the recess. (2) A cleaning process may be performed to clean the surface of the substrate beside the gate structure. An epitaxial structure is formed in the substrate beside the gate structure. | 12-12-2013 |
20130341638 | MULTI-GATE FIELD-EFFECT TRANSISTOR AND PROCESS THEREOF - A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from bottom to top. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor. | 12-26-2013 |
20140124835 | SEMICONDUCTOR STRUCTURE - A semiconductor structure includes agate structure, an epitaxial layer and a carbon-containing silicon germanium cap layer. The gate structure is located on a substrate. The epitaxial layer is located in the substrate beside the gate structure. The carbon-containing silicon germanium cap layer is located on the epitaxial layer. Otherwise, semiconductor processes for forming said semiconductor structure are also provided. | 05-08-2014 |
20140124904 | EPITAXIAL LAYER AND METHOD OF FORMING THE SAME - A method of forming an epitaxial layer includes the following steps. At first, a first epitaxial growth process is performed to form a first epitaxial layer on a substrate, and a gas source of silicon, a gas source of carbon, a gas source of phosphorous and a gas source of germanium are introduced during the first epitaxial growth process to form the first epitaxial layer including silicon, carbon, phosphorous and germanium. Subsequently, a second epitaxial growth process is performed to form a second epitaxial layer, and a number of elements in the second epitaxial layer is smaller than a number of elements in the first epitaxial layer. | 05-08-2014 |
20140191285 | SEMICONDUCTOR DEVICE HAVING EPITAXIAL STRUCTURES - A semiconductor device having epitaxial structures includes a gate structure positioned on a substrate, epitaxial structures formed in the substrate at two sides of the gate structure, and an undoped cap layer formed on the epitaxial structures. The epitaxial structures include a dopant. The epitaxial structures and the undoped cap layer include a first semiconductor material having a first lattice constant and a second semiconductor material having a second lattice constant. The second lattice constant is larger than the first lattice constant. The second semiconductor material in the epitaxial structure includes a first concentration and the second semiconductor material in the undoped cap layer includes a second concentration. The second concentration is lower than the first concentration, and is upwardly decreased. | 07-10-2014 |
20140235038 | SEMICONDUCTOR DEVICE AND METHOD OF FORMING EPITAXIAL LAYER - A method for forming epitaxial layer is disclosed. The method includes the steps of providing a semiconductor substrate, and forming an undoped first epitaxial layer in the semiconductor substrate. Preferably, the semiconductor substrate includes at least a recess, the undoped first epitaxial layer has a lattice constant, a bottom thickness, and a side thickness, in which the lattice constant is different from a lattice constant of the semiconductor substrate and the bottom thickness is substantially larger than or equal to the side thickness. | 08-21-2014 |
20140295634 | MULTI-GATE FIELD-EFFECT TRANSISTOR PROCESS - A Multi-Gate Field-Effect Transistor includes a fin-shaped structure, a gate structure, at least an epitaxial structure and a gradient cap layer. The fin-shaped structure is located on a substrate. The gate structure is disposed across a part of the fin-shaped structure and the substrate. The epitaxial structure is located on the fin-shaped structure beside the gate structure. The gradient cap layer is located on each of the epitaxial structures. The gradient cap layer is a compound semiconductor, and the concentration of one of the ingredients of the compound semiconductor has a gradient distribution decreasing from inner to outer. Moreover, the present invention also provides a Multi-Gate Field-Effect Transistor process forming said Multi-Gate Field-Effect Transistor. | 10-02-2014 |
20140335674 | MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE - A manufacturing method of a semiconductor device is provided. The method includes at least the following steps. A gate structure is formed on a substrate. An epitaxial structure is formed on the substrate, wherein the epitaxial structure comprises SiGe, and the Ge concentration in the epitaxial structure is equal to or higher than | 11-13-2014 |
20150041855 | SEMICONDUCTOR DEVICE - A semiconductor device includes at least two fin-shaped structures, a gate structure, at least two epitaxial structures and a silicon cap. The fin-shaped structures are disposed on a substrate and are covered by the gate structure. The epitaxial structures are disposed at one side of the gate structure and respectively directly contact each fin-shaped structure, wherein the epitaxial structures are spaced apart from each other. The silicon cap simultaneously surrounds the epitaxial structures. | 02-12-2015 |
20150044831 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A first gate and a second gate are formed on a substrate. A first stress layer is formed to cover the first gate and the second gate. The first stress layer covering the first gate is etched to form a first spacer beside the first gate, but reserves the first stress layer covering the second gate. A first epitaxial layer is formed beside the first spacer. The first stress layer and the first spacer are entirely removed. A second stress layer is formed to cover the first gate and the second gate. The second stress layer covering the second gate is etched to form a second spacer beside the second gate, but reserves the second stress layer covering the first gate. A second epitaxial layer is formed beside the second spacer. The second stress layer and the second spacer are entirely removed. | 02-12-2015 |
20150044879 | REMOVING METHOD - A removing method including the following steps. A substrate is transferred into an etching machine, wherein the substrate has a material layer formed thereon. A cycle process is performed. The cycle process includes performing an etching process to remove a portion of the material layer, and performing an annealing process to remove a by-product generated by the etching process. The cycle process is repeated at least one time. The substrate is transferred out of the etching machine. In the removing method of the invention, the cycle process is performed multiple times to effectively remove the undesired thickness of the material layer and reduce the loading effect. | 02-12-2015 |