Patent application number | Description | Published |
20110193144 | SEMICONDUCTOR DEVICE HAVING ELEVATED STRUCTURE AND METHOD OF MANUFACTURING THE SAME - A semiconductor device includes a semiconductor substrate; a gate stack overlying the substrate, a spacer formed on sidewalls of the gate stack, and a protection layer overlying the gate stack for filling at least a portion of a space surrounded by the spacer and the top surface of the gate stack. A top surface of the spacer is higher than a top surface of the gate stack. | 08-11-2011 |
20110294287 | METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING DUAL FULLY-SILICIDED GATE - A method of manufacturing the semiconductor device having a dual fully-silicided gate includes the following steps. A substrate having a first transistor and a second transistor formed thereon is provided, wherein the first transistor includes a first gate and a first source/drain and the second transistor includes a second gate and a second source/drain. The gate height of the first gate is different from that of the second gate. A first silicidation process is performed to respectively transform the first gate and the second gate into a first silicided gate and a second silicided gate simultaneously, wherein the material of the first silicided gate is different from that of the second silicided gate. | 12-01-2011 |
20120138897 | SOURCE/DRAIN STRESSOR HAVING ENHANCED CARRIER MOBILITY AND METHOD FOR MANUFACTURING SAME - Various source/drain stressors that can enhance carrier mobility, and methods for manufacturing the same, are disclosed. An exemplary source/drain stressor includes a seed layer of a first material disposed over a substrate of a second material, the first material being different than the second material; a relaxed epitaxial layer disposed over the seed layer; and an epitaxial layer disposed over the relaxed epitaxial layer. | 06-07-2012 |
20130252175 | Litho Cluster and Modulization to Enhance Productivity - The present disclosure relates to a lithographic tool arrangement for semiconductor workpiece processing. The lithographic tool arrangement groups lithographic tools into clusters, and selectively transfers a semiconductor workpiece between a plurality of lithographic tools of a first type in a first cluster to a plurality of lithographic tools of a second type in a second cluster. The selective transfer is achieved though a transfer assembly, which is coupled to a defect scan tool that identifies defects generated in the lithographic tool of the first type. The disclosed lithographic tool arrangement also utilizes shared structural elements such as a housing assembly, and shared functional elements such as gases and chemicals. The lithographic tool arrangement may consist of baking, coating, exposure, and development units configured to provide a modularization of these various components in order to optimize throughput and efficiency for a given lithographic fabrication process. | 09-26-2013 |
20140113424 | Source/Drain Stressor Having Enhanced Carrier Mobility and Method for Manufacturing Same - Various source/drain stressors that can enhance carrier mobility, and methods for manufacturing the same, are disclosed. An exemplary source/drain stressor includes a seed layer of a first material disposed over a substrate of a second material, the first material being different than the second material; a relaxed epitaxial layer disposed over the seed layer; and an epitaxial layer disposed over the relaxed epitaxial layer. | 04-24-2014 |
20140213048 | Method of Making a FinFET Device - A FinFET device is fabricated by first receiving a FinFET precursor. The FinFET precursor includes a substrate, fins on the substrate, isolation regions on sides of the fins and dummy gate stacks on the substrate including wrapping a portion of the fin, which is referred to as a gate channel region. The dummy gate stacks is removed to form a gate trench and a gate dielectric layer is deposited in the gate trench. A metal stressor layer (MSL) is conformably deposited on the gate dielectric layer. A capping layer is deposited on the MSL. A thermal treatment is applied to the MSL to achieve a volume expansion. Then the capping layer is removed and a metal gate (MG) is formed on the MSL. | 07-31-2014 |
20150129990 | SEMICONDUCTOR DEVICE HAVING ELEVATED STRUCTURE - A semiconductor device includes a gate stack overlying a substrate. The semiconductor device further includes a spacer on sidewalls of the gate stack, where a top surface of the spacer is above a top surface of the gate stack. Additionally, the semiconductor device includes a protection layer overlying the gate stack and filling at least a portion of a space surrounded by the spacer above the top surface of the gate stack. Furthermore, the semiconductor device includes a contact hole over the spacer, where the contact hole extends over the gate stack, and where a sidewall of the contact hole has a step-wise shape. | 05-14-2015 |
20150221751 | METHOD OF MAKING A FINFET DEVICE - A FinFET device is fabricated by first receiving a FinFET precursor. The FinFET precursor includes a substrate, fins on the substrate, isolation regions on sides of the fins and dummy gate stacks on the substrate including wrapping a portion of the fin, which is referred to as a gate channel region. The dummy gate stacks is removed to form a gate trench and a gate dielectric layer is deposited in the gate trench. A metal stressor layer (MSL) is conformably deposited on the gate dielectric layer. A capping layer is deposited on the MSL. A thermal treatment is applied to the MSL to achieve a volume expansion. Then the capping layer is removed and a metal gate (MG) is formed on the MSL. | 08-06-2015 |