| Patent application number | Description | Published |
|---|
| 20080252375 | Voltage-clamping device and operational amplifier and design method thereof - A voltage-clamping device used in an operational amplifier is provided. The operational amplifier comprises a first transistor. The cross-voltage between the gate and the source of the first transistor is near to a specific voltage and the cross-voltage between the drain and the source of the first transistor is not equal to zero, so as to generate a big substrate current. The voltage-clamping device comprises a second transistor whose source and gate are respectively coupled to the drain of the first transistor and used for receiving a bias signal, so that the second transistor is biased in saturation region, and the voltage at the source of the second transistor is made equal to the difference between the bias signal and the threshold voltage of the second transistor. Thus, the cross-voltage between the drain and the source of the first transistor is reduced and the substrate current is reduced accordingly. | 10-16-2008 |
| 20080252667 | Digital-to-analog converter and method thereof - A digital-to-analog (D/A) converter comprises a decoder apparatus and an operational amplifier. The decoder apparatus comprises first and second decoder unit. The first decoder unit selects a voltage of first voltage set as first and second voltage in response to a value of first gray level set. The second decoder unit selects first border voltage of second voltage set as the first and the second voltages and second border voltage of that as the first and the second voltages in response to the maximum and the minimum value of second gray level set respectively. The second decoder unit further selects the first and the second boarder voltage as the first and the second voltage respectively in response to an intermediate value of the second gray level set. The operational amplifier generates a pixel voltage having level between the first and the second voltage accordingly. | 10-16-2008 |
| 20080253482 | Receiving circuit and method thereof - A receiving circuit is provided for receiving a data signal and a clock signal, which are RSDS signals, and outputting an output data signal to a data driver. The receiving circuit includes a data comparator, a data intermediate circuit, a clock comparator, a clock intermediate, and a flip-flop. The data comparator, driven with a data bias current, receives the data signal, and outputs a compared data signal. The clock comparator, driven with a clock bias current, receives the clock signal, and outputs a compared clock signal. The flip-flop receives the compared data signal via the data intermediate circuit and the compared clock signal via the clock intermediate circuit. The phase difference between the compared data signal and the compared clock signal is improved by adjusting the data and the clock bias currents. | 10-16-2008 |
| 20080253500 | Flip-flop and shift register - A flip-flop is provided. The flip-flop is used in a shift register in a source driver. The flip-flop is used to receive a first clock signal, an input signal and output an output signal. The output signal is fed back to the flip-flop. The flip-flop includes a flop core for receiving the input signal and output the output signal. When the input signal and the output signal are all disabled, the flop core is disabled to function. When the input signal or the output signal is enabled, the flop core is enabled to function to output the output signal. | 10-16-2008 |
| 20080260090 | Shift register and shift registering apparatus - A shift register is provided for use in a data driver. The shift register includes a shift registering unit. The shift registering unit selectively receives a clock signal. The shift registering unit includes a flip-flop; and a first selection circuit. The first selection circuit selectively sends the clock signal to the flip-flop according to a first selection signal, wherein before the flip-flop receives a data signal that is enabled, the first selection circuit sends the clock signal to the flip-flop according to the first selection signal so that the flip-flop correctly outputs the enabled data signal according to the clock signal. | 10-23-2008 |
| 20080266220 | Scan driver - A scan driver for a liquid crystal display (LCD) includes first and second address logic units, first and second level shifters and a decoder. The first address logic unit enables an i | 10-30-2008 |
| 20090161275 | INTEGRATED CONTROLLING CHIP - An integrated controlling chip includes a signal processing unit, a resistance unit and an electrostatic discharge protection circuit. The signal processing unit includes an input port. The resistance unit includes a first node coupled to a signal pin of the integrated controlling chip, and includes a second node coupled to the input port of the signal processing unit. The electrostatic discharge protection circuit includes a node coupled between the first node of the resistance unit and the signal pin of the integrated controlling chip. | 06-25-2009 |
| 20100097142 | DRIVING CIRCUIT SYSTEM AND METHOD OF ELEVATING SLEW RATE OF OPERATIONAL AMPLIFIER - The invention discloses a driving circuit system and a method of elevating a slew rate of an operational amplifier. The driving circuit system comprises an operational amplifier, a judging module and a bias enhancing module. The operational amplifier has an input stage driven by a bias current. The bias enhancing module is electrically connected to the judging module and the input stage of the operational amplifier respectively. The judging module is used to generate a bias enhancing signal according to an edge-trigger of a control signal. When the bias enhancing module receives the bias enhancing signal, the bias enhancing module provides an additional current, which cooperates with the bias current, for driving the input stage of the operational amplifier, so as to elevating a slew rate of the operational amplifier. | 04-22-2010 |
| 20100164929 | SOURCE DRIVER - The invention discloses a source driver. The source driver comprises a plurality of channels and a control module. Each of the plurality of channels comprises an output buffer, an output pad, a driving switch, and a charge sharing switch. The control module is used to control a gate signal of the driving switch or the charge sharing switch in each channel to be changed linearly. By doing so, a peak current generated by the source driver can be lowered to reduce the electromagnetic interference (EMI). | 07-01-2010 |
| 20110102406 | GATE DRIVER AND OPERATING METHOD THEREOF - A gate driver applied to a LCD apparatus is disclosed. The gate driver includes a pulse modulation controlling module. When a pulse modulation controlling signal received by the pulse modulation controlling module is changed from a high level to a low level, the pulse modulation controlling module closes an active switch according to the pulse modulation controlling signal, so that a high level power signal will begin discharging to have a modulated pulse form. | 05-05-2011 |
