Patent application number | Description | Published |
20100283152 | INTEGRATED CIRCUITS INCLUDING ILD STRUCTURE, SYSTEMS, AND FABRICATION METHODS THEREOF - An integrated circuit includes a gate of a transistor disposed over a substrate. A connecting line is disposed over the substrate. The connecting line is coupled with an active area of the transistor. A level difference between a top surface of the connecting line and a top surface of the gate is about 400 Å or less. A via structure is coupled with the gate and the connecting line. A metallic line structure is coupled with the via structure. | 11-11-2010 |
20100308469 | METHOD AND APPARATUS OF FORMING A VIA - The present disclosure provides a semiconductor device that includes, a substrate; a first conductive line located over the substrate and extending along a first axis, the first conductive line having a first length and a first width, the first length being measured along the first axis; a second conductive line located over the first conductive line and extending along a second axis different from the first axis, the second conductive line having a second length and a second width, the second length being measured along the second axis; and a via coupling the first and second conductive lines, the via having an upper surface that contacts the second conductive line and a lower surface that contacts the first conductive line. The via has an approximately straight edge at the upper surface, the straight edge extending along the second axis and being substantially aligned with the second conductive line. | 12-09-2010 |
20110108994 | INTEGRATED CIRCUITS AND METHODS FOR FORMING THE INTEGRATED CIRCUITS - A method for forming an integrated circuit includes forming a first dielectric layer over a gate electrode of a transistor. An etch-stop layer is formed over the first dielectric layer. An opening is formed through the first dielectric layer and the etch-stop layer, exposing a source/drain (S/D) region of the transistor. A metal layer is formed in the opening, contacting the S/D region of the transistor. The metal layer has a surface that is at least partially substantially level with a first top surface of the etch-stop layer. A damascene structure is formed and coupled with the metal layer. | 05-12-2011 |
20110215477 | INTEGRATED CIRCUITS INCLUDING AIR GAPS AROUND INTERCONNECT STRUCTURES, AND FABRICATION METHODS THEREOF - An integrated circuit includes an interconnect structure at least partially disposed in at least one opening of a dielectric layer that is disposed over a substrate. At least one air gap is disposed between the dielectric layer and the interconnect structure. At least one first liner material is disposed under the at least one air gap. At least one second liner material is disposed around the interconnect structure. The at least one first liner material is disposed between the dielectric layer and at least one second liner material. | 09-08-2011 |
20110245949 | METHOD AND APPARATUS OF PATTERNING SEMICONDUCTOR DEVICE - Provided is an apparatus for fabricating a semiconductor device. The apparatus includes a first photomask and a second photomask. The first photomask has a plurality of first features thereon, and the first photomask having a first global pattern density. The second photomask has a plurality of second features thereon, and the second photomask has a second global pattern density. The plurality of first and second features collectively define a layout image of a layer of the semiconductor device. The first and second global pattern densities have a predetermined ratio. | 10-06-2011 |
20110291281 | PARTIAL AIR GAP FORMATION FOR PROVIDING INTERCONNECT ISOLATION IN INTEGRATED CIRCUITS - Partial air gap formation for providing interconnect isolation in integrated circuits is described. One embodiment is an integrated circuit (“IC”) structure includes a substrate having two adjacent interconnect features formed thereon; caps formed over and aligned with each of the interconnect features; sidewalls formed on opposing sides of each of the interconnect features and a gap formed between the interconnect features; and a dielectric material layer disposed over the substrate to cover the caps and the gap. | 12-01-2011 |
20120227018 | Method and Apparatus of Patterning Semiconductor Device - Provided is an apparatus for fabricating a semiconductor device. The apparatus includes a first photomask and a second photomask. The first photomask has a plurality of first features thereon, and the first photomask having a first global pattern density. The second photomask has a plurality of second features thereon, and the second photomask has a second global pattern density. The plurality of first and second features collectively define a layout image of a layer of the semiconductor device. The first and second global pattern densities have a predetermined ratio. | 09-06-2012 |
20130221541 | INTEGRATED CIRCUITS INCLUDING AIR GAPS AROUND INTERCONNECT STRUCTURES, AND FABRICATION METHODS THEREOF - An integrated circuit which includes an interconnect structure disposed at least partially in at least one opening of a dielectric layer. The integrated circuit further includes at least one air gap disposed between the dielectric layer and the interconnect structure. The integrated circuit further includes at least one first liner material disposed under the at least one air gap, the at least one first liner material extending along a bottom portion of a sidewall of the at least one opening of the dielectric layer. | 08-29-2013 |
20130256902 | INTERCONNECT STRUCTURE HAVING SMALLER TRANSITION LAYER VIA - An interconnect structure including a bottom layer over a substrate, where the bottom layer includes at least one bottom layer line and at least one bottom layer via. The interconnect structure further includes a transition layer over the bottom layer, where the transition layer includes at least one transition layer line and at least one transition layer via. The interconnect structure further includes a top layer over the transition layer, where the top layer includes at least one top layer line and at least one top layer via. The at least one transition layer via has a cross sectional area at least 30% less than a cross sectional area of the at least one top layer via. | 10-03-2013 |
20140220769 | INTEGRATED CIRCUITS INCLUDING ILD STRUCTURE, SYSTEMS, AND FABRICATION METHODS THEREOF - A method of forming an integrated circuit comprises forming a gate of a transistor over a substrate. The method further comprises forming a connecting line over the substrate, the connecting line being coupled with an active area of the transistor. The method also comprises forming a dielectric layer surrounding the gate and the connecting line. The method additionally comprises forming an etch stop layer over the dielectric layer and covering a portion of a top surface of the connecting line. The method further comprises forming a via structure comprising a via in physical contact with a top surface of the gate and another portion of the top surface of the connecting line. The method also comprises forming a metallic line structure being coupled with the via structure. | 08-07-2014 |
20150044865 | METHODS OF MAKING INTEGRATED CIRCUITS INCLUDING AIR GAPS AROUND INTERCONNECT STRUCTURES - A method of making an integrated circuit includes forming an interconnect structure in an opening in a dielectric layer. The method further includes forming an air gap between the dielectric layer and the interconnect structure, where a first liner layer along a bottom portion of a sidewall of the opening of the dielectric layer is under the air gap, and a top portion of the first liner layer is below a lowest portion of the air gap. | 02-12-2015 |