| Patent application number | Description | Published |
|---|
| 20090020757 | Flash Anneal for a PAI, NiSi Process - A structure and a method for mitigation of the damage arising in the source/drain region of a MOSFET is presented. A substrate is provided having a gate structure comprising a gate oxide layer and a gate electrode layer, and a source and drain region into which impurity ions have been implanted. A PAI process generates an amorphous layer within the source and drain region. A metal is deposited and is reacted to create a silicide within the amorphous layer, without exacerbating existing defects. Conductivity of the source and drain region is then recovered by flash annealing the substrate. | 01-22-2009 |
| 20100151639 | METHOD FOR MAKING A THERMALLY-STABLE SILICIDE - Provided is a method of fabrication a semiconductor device that includes providing a semiconductor substrate, forming a gate structure over the substrate, the gate structure including a gate dielectric and a gate electrode disposed over the gate dielectric, forming source/drain regions in the semiconductor substrate at either side of the gate structure, forming a metal layer over the semiconductor substrate and the gate structure, the metal layer including a refractory metal layer or a refractory metal compound layer; forming an alloy layer over the metal layer; and performing an annealing thereby forming metal alloy silicides over the gate structure and the source/drain regions, respectively. | 06-17-2010 |
| 20100273324 | METHODS OF MANUFACTURING METAL-SILICIDE FEATURES - A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening. The metal-silicide layer may then be annealed. | 10-28-2010 |
| 20100314698 | METHODS OF MANUFACTURING METAL-SILICIDE FEATURES - A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening. The metal-silicide layer may then be annealed. | 12-16-2010 |
| Patent application number | Description | Published |
|---|
| 20110212590 | HIGH TEMPERATURE IMPLANTATION METHOD FOR STRESSOR FORMATION - An integrated circuit device and method of fabricating the integrated circuit device is disclosed. According to one of the broader forms of the invention, a method involves providing a semiconductor substrate. A combination of a pre-amorphous implantation process, a high temperature carbon implantation process, and/or an annealing process are performed on the substrate to form a stressor region. | 09-01-2011 |
| 20110212592 | METHOD OF FORMING ULTRA-SHALLOW JUNCTIONS IN SEMICONDUCTOR DEVICES - A method of forming MOS transistor includes the steps of performing a pocket implantation process on a substrate having a gate stack, performing a co-implanted ion implantation process on the substrate at a temperature less than room temperature, performing a lightly doped source/drain implantation process on the substrate, and forming source and drain regions in the substrate, adjacent the gate stack. | 09-01-2011 |
| 20110295539 | METHOD AND APPARATUS FOR MEASURING INTRA-DIE TEMPERATURE - A method for measuring the intra-die temperature of a wafer with a fast response time is described. The method includes providing a wafer in a thermal process chamber, radiating the wafer in a first predetermined radiation range to heat the wafer to a predetermined temperature range for a predetermined time, receiving the radiation reflected from a die area while the wafer is being heated and detecting reflected radiation having a second predetermined radiation range, and determining a temperature of the die area by a processor being responsive to the detected second predetermined radiation range. | 12-01-2011 |
| 20120012903 | METHOD FOR MAKING A DISILICIDE - Methods for fabricating a semiconductor device are disclosed. A metal-rich silicide and/or a mono-silicide is formed on source/drain (S/D) regions. A millisecond anneal is provided to the metal-rich silicide and/or the mono-silicide to form a di-silicide with limited spikes at the interface between the silicide and substrate. The di-silicide has an additive which can lower the electron Schottky barrier height. | 01-19-2012 |
