| Patent application number | Description | Published |
|---|
| 20090039521 | Semiconductor structure and semiconductor manufacturing method - A semiconductor structure comprising a first signal layer, a second signal layer, a wiring layer and at least one via is provided. The wiring layer is formed between the first signal layer and the second signal layer. A conducting wire is disposed between a first terminal and a second terminal on the wiring layer. At least one via is used to conduct the first signal layer and the second signal layer. The at least one via is disposed adjacent to the first terminal and the second terminal. | 02-12-2009 |
| 20090152721 | SEMICONDUCTOR PACKAGE AND METHOD FOR MAKING THE SAME - The present invention relates to a semiconductor package and a method for making the same. The semiconductor package includes a substrate, a first passivation layer, a first metal layer, a second passivation layer, a second metal layer and a third metal layer. The substrate has a surface having at least one first pad and at least one second pad. The first passivation layer covers the surface of the substrate and exposes the first pad and the second pad. The first metal layer is formed on the first passivation layer and is electrically connected to the second pad. The second passivation layer is formed on the first metal layer and exposes the first pad and part of the first metal layer. The second metal layer is formed on the second passivation layer and is electrically connected to the first pad. The third metal layer is formed on the second passivation layer and is electrically connected to the first metal layer. | 06-18-2009 |
| 20100051341 | Circuit substrate having power/ground plane with grid holes - The present invention relates to a circuit substrate having a first conductive layer. The first conductive layer includes at least one power/ground plane. The power/ground plane includes at least one plane edge and plurality of grid lines. Each grid line has a width. The grid lines intersect each other to define a plurality of first grid holes, wherein the distance between the first grid hole that is closest to the plane edge and the plane edge is 1.5 times the width. Thus, the influence on the resistance of power signal and ground signal caused by the first grid holes is reduced, power integrity is improved, and heat generation is reduced. | 03-04-2010 |
| 20100065312 | Substrate for window ball grid array package - The present invention relates to a substrate for a window ball grid array package. The substrate has at least one window, a plurality of fingers and at least one power/ground section (or power/ground ring). The window penetrates the substrate. The fingers are disposed at the periphery of the window. The power/ground section (or power/ground ring) is disposed between the fingers and the window. The power/ground section (or power/ground ring) is connected to a power/ground voltage so that the power/ground section (or power/ground ring) can improve the smoothness of the current and power integrity, and reduce the heat generation. | 03-18-2010 |
| 20100071939 | Substrate of window ball grid array package - The present invention relates to a substrate of a window ball grid array package. The substrate includes at least one window, a first conductive layer, a second conductive layer, a dielectric layer, a plurality of first vias and a plurality of second vias. The window penetrates the substrate. The first conductive layer has a plurality of fingers and at least one first power/ground plane, and the fingers are disposed at the periphery of the window. The second conductive layer has at least one second power/ground plane. The dielectric layer is disposed between the first conductive layer and the second conductive layer. The first vias electrically connect the first power/ground plane to the second power/ground plane. The second vias are disposed between the fingers and the window, and electrically connect some of the fingers to the second power/ground plane. Thus, the substrate can control the characteristic impedance and increase the signal integrity. | 03-25-2010 |
| 20100102447 | Substrate of window ball grid array package and method for making the same - The present invention relates to a substrate of a window ball grid array package and a method for making the same. The substrate includes a core layer, a first conductive layer, a second conductive layer, at least one window and at least one via. The window includes a first through hole and a third conductive layer. The first through hole penetrates the substrate and has a first sidewall. The third conductive layer is disposed on the first sidewall and connects the first conductive layer and the second conductive layer. The via includes a second through hole and a fourth conductive layer. The second through hole penetrates the substrate and has a second sidewall. The fourth conductive layer is disposed on the second sidewall and connects the first conductive layer and the second conductive layer. As a result, the substrate has the effect of controlling the characteristic impedance and increasing the signal integrity. | 04-29-2010 |
| 20100283139 | Semiconductor Device Package Having Chip With Conductive Layer - The present invention relates to a semiconductor device package having a chip with a conductive layer. The semiconductor device package includes a substrate, a chip, at least one first electrical connecting element and at least one second electrical connecting element. The substrate has a first surface and a first circuit layer. The first circuit layer is disposed adjacent to the first surface. The chip is attached to the substrate and has a surface, at least one first pad, a plurality of second pads and a conductive layer. The first pad, the second pads and the conductive layer are disposed adjacent to the surface, and the conductive layer connects the second pads. | 11-11-2010 |
