Patent application number | Description | Published |
20140091272 | RESISTANCE VARIABLE MEMORY STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a conductive structure. The resistance variable memory structure is over the conductive structure. The resistance variable memory structure includes a first electrode over the conductive structure. A resistance variable layer is disposed over the first electrode. A cap layer is disposed over the resistance variable layer. The cap layer includes a first metal material. A second electrode disposed over the cap layer. The second electrode includes a second metal material different from the first metal material. | 04-03-2014 |
20140131650 | RESISTANCE VARIABLE MEMORY STRUCTURE - A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a dielectric layer. The resistance variable memory structure is over the dielectric layer. The resistance variable memory structure includes a first electrode disposed over the dielectric layer. The first electrode has a sidewall surface. A resistance variable layer has a first portion which is disposed over the sidewall surface of the first electrode and a second portion which extends from the first portion away from the first electrode. A second electrode is over the resistance variable layer. | 05-15-2014 |
20140131651 | LOGIC COMPATIBLE RRAM STRUCTURE AND PROCESS - A memory cell and method including a first electrode conformally formed through a first opening in a first dielectric layer, a resistive layer conformally formed on the first electrode, a second electrode conformally formed on the resistive layer, and a second dielectric layer conformally formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer is formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond a region defined by the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the region defined by the first opening. The second electrode is coupled to a second metal layer using a via that extends through the second opening. | 05-15-2014 |
20140131654 | LOGIC COMPATIBLE RRAM STRUCTURE AND PROCESS - A memory cell and method including a first electrode conformally formed through a first opening in a first dielectric layer, a resistive layer conformally formed on the first electrode, a spacing layer conformally formed on the resistive layer, a second electrode conformally formed on the resistive layer, and a second dielectric layer conformally formed on the second electrode, the second dielectric layer including a second opening. The first dielectric layer is formed on a substrate including a first metal layer. The first electrode and the resistive layer collectively include a first lip region that extends a first distance beyond the first opening. The second electrode and the second dielectric layer collectively include a second lip region that extends a second distance beyond the first opening. The spacing layer extends from the second distance to the first distance. The second electrode is coupled to a second metal layer using a via that extends through the second opening. | 05-15-2014 |
20140166961 | RESISTIVE RANDOM ACCESS MEMORY (RRAM) AND METHOD OF MAKING - The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure electrically connected to the transistor. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer over the bottom electrode and having a same width as the top portion of the bottom electrode, and a top electrode over the resistive material layer and having a smaller width than the resistive material layer. | 06-19-2014 |
20140175365 | RESISTIVE RANDOM ACCESS MEMORY (RRAM) STRUCTURE AND METHOD OF MAKING THE RRAM STRUCTURE - The present disclosure provides a resistive random access memory (RRAM) cell. The RRAM cell includes a transistor, a bottom electrode adjacent to a drain region of the transistor and coplanar with the gate, a resistive material layer on the bottom electrode, a top electrode on the resistive material layer, and a conductive material connecting the bottom electrode to the drain region. | 06-26-2014 |
20140175366 | RESISTANCE VARIABLE MEMORY STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a resistance variable memory structure. The semiconductor structure also includes a dielectric layer. The resistance variable memory structure is over the dielectric layer. The resistance variable memory structure includes a first electrode disposed over the dielectric layer. The first electrode has a sidewall surface. A resistance variable layer has a first portion which is disposed over the sidewall surface of the first electrode and a second portion which extends from the first portion away from the first electrode. A second electrode is over the resistance variable layer. | 06-26-2014 |
20140203236 | ONE TRANSISTOR AND ONE RESISTIVE RANDOM ACCESS MEMORY (RRAM) STRUCTURE WITH SPACER - The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode; a spacer surrounding the capping layer; and, a top electrode on the capping layer having a smaller width than the resistive material layer. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer. | 07-24-2014 |
20140247644 | Resistive Memory Reset - A resistive memory cell includes a switch and a resistive switching device. The switch includes a first terminal connected to a select line and a gate terminal connected to a word line. The resistive switching device is connected between a second terminal of the switch and a bit line. The resistive switching device is resettable by having a positive bias applied to the word line and a negative bias applied to the bit line. | 09-04-2014 |
20140252295 | ONE TRANSISTOR AND ONE RESISTIVE (1T1R) RANDOM ACCESS MEMORY (RRAM) STRUCTURE WITH DUAL SPACERS - The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode, a first spacer surrounding the capping layer and a top electrode, a second spacer surround the top portion of the bottom electrode and the first spacer, and the top electrode. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer. | 09-11-2014 |
20140252297 | Resistive Memory Cell Array with Top Electrode Bit Line - A method for forming a resistive memory cell within a memory array includes forming a patterned stopping layer on a first metal layer formed on a substrate and forming a bottom electrode into features of the patterned stopping layer. The method further includes forming a resistive memory layer. The resistive memory layer includes a metal oxide layer and a top electrode layer. The method further includes patterning the resistive memory layer so that the top electrode layer acts as a bit line within the memory array and a top electrode of the resistive memory cell. | 09-11-2014 |
20140254237 | Method for Operating RRAM Memory - Methods for operating memory are disclosed. A method includes applying a select word line voltage to a word line node of a first resistive random access memory (RRAM) cell; applying a first programming voltage to a source line node of the first RRAM cell; and setting the first RRAM cell comprising applying a second programming voltage to a bit line node of the first RRAM cell. The first programming voltage is greater than zero volts, and the second programming voltage is greater than the first programming voltage. Other disclosed methods include concurrently setting and resetting RRAM cells. | 09-11-2014 |
20140264222 | Resistive Switching Random Access Memory with Asymmetric Source and Drain - The present disclosure provides one embodiment of a resistive random access memory (RRAM) structure. The RRAM structure includes a resistive memory element formed on a semiconductor substrate and designed for data storage; and a field effect transistor (FET) formed on the semiconductor substrate and coupled with the resistive memory element. The FET includes asymmetric source and drain. The resistive element includes a resistive material layer and further includes first and second electrodes interposed by the resistive material layer. | 09-18-2014 |
20140264229 | LOW FORM VOLTAGE RESISTIVE RANDOM ACCESS MEMORY (RRAM) - The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a non-planar portion, a resistive material layer conformally covering the non-planar portion of the bottom electrode; and, a top electrode on the resistive material layer. The via portion of the bottom electrode is embedded in a first RRAM stop layer. The non-planar portion of the bottom electrode has an apex and is centered above the via portion. | 09-18-2014 |
20140264233 | RESISTANCE VARIABLE MEMORY STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, protection spacers and a second electrode. The first electrode has a top surface and a first outer sidewall surface on the memory region. The resistance variable layer has a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection spacers are disposed over a portion of the top surface of the first electrode and surround at least the second portion of the resistance variable layer. The protection spacers are configurable to protect at least one conductive path in the resistance variable layer. The protection spacers have a second outer sidewall surface substantially aligned with the first outer sidewall surface of the first electrode. The second electrode is disposed over the resistance variable layer. | 09-18-2014 |
20140264234 | RESISTANCE VARIABLE MEMORY STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor structure includes a memory region. A memory structure is disposed on the memory region. The memory structure includes a first electrode, a resistance variable layer, a protection material and a second electrode. The first electrode has a top surface on the memory region. The resistance variable layer has at least a first portion and a second portion. The first portion is disposed over the top surface of the first electrode and the second portion extends upwardly from the first portion. The protection material surrounds the second portion of the resistance variable layer. The protection material is configurable to protect at least one conductive path in the resistance variable layer. The second electrode is disposed over the resistance variable layer. | 09-18-2014 |
20150090949 | RRAM CELL STRUCTURE WITH LATERALLY OFFSET BEVA/TEVA - The present disclosure relates to a resistive random access memory (RRAM) cell architecture, with off-axis or laterally offset top electrode via (TEVA) and bottom electrode via (BEVA). Traditional RRAM cells having a TEVA and BEVA that are on-axis can cause high contact resistance variations. The off-axis TEVA and BEVA in the current disclosure pushes the TEVA away from the insulating layer over the RRAM cell, which can improve the contact resistance variations. The present disclosure also relates to a memory device having a rectangular shaped RRAM cell having a larger area that can lower the forming voltage and improve data retention. | 04-02-2015 |
20150144859 | Top Electrode Blocking Layer for RRAM Device - An integrated circuit device including a resistive random access memory (RRAM) cell formed over a substrate. The RRAM cell includes a top electrode having an upper surface. A blocking layer covers a portion of the upper surface. A via extends above the top electrode within a matrix of dielectric. The upper surface of the top electrode includes an area that interfaces with the blocking layer and an area that interfaces with the via. The area of the upper surface that interfaces with the via surrounds the area of the upper surface that interfaces with the blocking layer. The blocking layer is functional during processing to protect the RRAM cell from etch damage while being structured in such a way as to not interfere with contact between the overlying via and the top electrode. | 05-28-2015 |
20150147864 | ONE TRANSISTOR AND ONE RESISTIVE (1T1R) RANDOM ACCESS MEMORY (RAM) STRUCTURE WITH DUAL SPACERS - The present disclosure provides methods of making resistive random access memory (RRAM) cells. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode, a first spacer surrounding the capping layer and a top electrode, a second spacer surround the top portion of the bottom electrode and the first spacer, and the top electrode. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer. | 05-28-2015 |
20150214276 | RESISTIVE RANDOM ACCESS MEMORY (RRAM) STRUCTURE - A resistive random access memory (RRAM) cell comprises a transistor having a gate and a source/drain region, a bottom electrode having an upper surface coplanar with a top surface of the gate, a resistive material layer on the bottom electrode, a top electrode on the resistive material layer, and a conductive material connecting the bottom electrode to the source/drain region. | 07-30-2015 |
20150325786 | RRAM CELL STRUCTURE WITH LATERALLY OFFSET BEVA/TEVA - The present disclosure relates to a method of forming a resistive random access memory (RRAM) cell. The method forms a bottom electrode over a bottom electrode via. The method further forms a variable resistive dielectric layer over the bottom electrode, and a top electrode over the variable resistive dielectric layer. The method forms a top electrode via vertically extending outward from an upper surface of the top electrode at a position centered along a first axis that is laterally offset from a second axis centered upon the bottom electrode via. The top electrode via has a smaller width than the top electrode. Laterally offsetting the top electrode via from the bottom electrode via provides the top electrode via with good contact resistance. | 11-12-2015 |
20150380063 | SEMICONDUCTOR ARRANGEMENT AND METHODS OF USE - A semiconductor arrangement and method of use are provided. A semiconductor arrangement includes a resistance random access memory (RRAM) component including a source line electrically coupled to a first active area. The source line of the RRAM comprises a first metal line in parallel with a second metal line, where both the first metal line and the second metal line are electrically coupled to the first active area. The RRAM component also includes a resistor electrically coupled to a second active area. A positive bias is applied to a selected RRAM component during at least one of a set operation or reset operation while a negative bias is concurrently applied to a non-selected RRAM component of the semiconductor arrangement. | 12-31-2015 |
20150380644 | METHOD OF FORMING A SEMICONDUCTOR STRUCTURE - A method of forming a semiconductor structure includes depositing a first electrode material over a conductive structure and a dielectric layer, patterning the first electrode material to form a first electrode contacting the conductive structure, depositing a resistance variable layer over the first electrode and the dielectric layer, depositing a second electrode material over the resistance variable layer, and etching a portion of the second electrode material and the resistance variable layer to form a second electrode over a remaining portion of the resistance variable layer. | 12-31-2015 |
20160035975 | TOP ELECTRODE FOR DEVICE STRUCTURES IN INTERCONNECT - Some embodiments relate to an integrated circuit device. The integrated circuit device includes a resistive random access memory (RRAM) cell, which includes a top electrode and a bottom electrode that are separated by a RRAM dielectric layer. The top electrode of the RRAM cell has a recess in its upper surface. A via is disposed over the RRAM cell and contacts the top electrode within the recess. | 02-04-2016 |
Patent application number | Description | Published |
20090215216 | Packaging method of image sensing device - A packaging method for an image sensing device is disclosed. The packaging method includes the steps of a) mounting an image sensing module, having a light-receiving region exposed, on a substrate; b) connecting the image sensing module and the substrate via a plurality of bonding wires; c) forming a protecting layer on the light-receiving region of the image sensing module; d) forming a molding layer to seal the plurality of bonding wires; e) flattening the protecting layer and the molding layer; f) removing the protecting layer to expose the light-receiving region of the image sensing module; and g) forming a transparent lid. | 08-27-2009 |
20090256222 | Packaging method of image sensing device - A packaging method for an image sensing device is disclosed. The packaging method includes the steps of a) providing an annular dam on a substrate; b) mounting an image sensing module, having a light-receiving region exposed, inside the annular dam on the substrate; c) connecting the image sensing module and the substrate via a plurality of bonding wires; d) forming a barrier around the light-receiving region on the image sensing module; e) filling an adhesive between the barrier and the annular dam with the plurality of bonding wires being encapsulated; f) forming a transparent lid above the light-receiving region; and g) cutting off the annular dam. | 10-15-2009 |
20100025795 | Image sensing device and packaging method thereof - An image sensing device and packaging method thereof is disclosed. The packaging method includes the steps of a) providing an image sensing module, having a light-receiving region exposed, on a first substrate; b) forming a plurality of first contacts around the light-receiving region on the image sensing module; c) providing a second substrate, having a plurality of second contacts corresponding to the plurality of first contacts and an opening for allowing the light-receiving region to be exposed while the second substrate is placed over the image sensing module, the plurality of second contacts being disposed around the opening; d) connecting the plurality of first contacts and the plurality of second contacts; and e) disposing a transparent lid above the light-receiving region, on a side of the second substrate which is opposite to the plurality of second contacts. | 02-04-2010 |
20100295099 | IMAGE SENSING DEVICE AND PACKAGING METHOD THEREOF - An image sensing device and packaging method thereof is disclosed. The packaging method includes the steps of a) providing an image sensing module, having a light-receiving region exposed, on a first substrate; b) forming a plurality of first contacts around the light-receiving region on the image sensing module; c) providing a second substrate, having a plurality of second contacts corresponding to the plurality of first contacts and an opening for allowing the light-receiving region to be exposed while the second substrate is placed over the image sensing module, the plurality of second contacts being disposed around the opening; d) connecting the plurality of first contacts and the plurality of second contacts; and e) disposing a transparent lid above the light-receiving region, on a side of the second substrate which is opposite to the plurality of second contacts. | 11-25-2010 |
Patent application number | Description | Published |
20130154900 | WIRELESS COMMUNICATION DEVICE HAVING METAL END PORTION OF HOUSING THEREOF - An exemplary wireless communication device includes a circuit board, a metal end portion, an antenna, and a connecting member. The antenna is positioned on the circuit board. The connecting member interconnects the circuit board and the end portion. The connecting member serves as a feeding point of the antenna. The end portion is a portion of a housing of the wireless communication device and further serves as a radiating portion of the antenna. | 06-20-2013 |
20130241786 | ANTENNA ASSEMBLY - An antenna assembly includes a carrier, a metal sheet, and an antenna. The metal sheet is attached to the carrier and defining at least one notch. The antenna is connected to the metal sheet and includes a radio body for receiving and transmitting wireless signals. The radio body is positioned above the metal sheet. The length of current path in a peripheral wall of the at least one notch is in a predetermined proportion to the wavelength of the wireless signals, enabling the metal sheet to resonate with the radio body to increase the bandwidth of the antenna. | 09-19-2013 |
20130259486 | WIRELESS COMMUNICATION DEVICE - A wireless communication device includes a first antenna, a second antenna, a first light sensor adjacent to the first antenna, a second light sensor adjacent to the second antenna, a controller, and a magnetic member movably located between the first antenna and the second antenna. When one of the first and second antennas in a state of receiving/transmitting wireless signals is covered by a user's hand, the nearby light sensor sends a pulse signal to the controller. The controller receiving the pulse signal controls the first and second antennas to change their magnetic polarity, enabling the magnetic member to be separated from one of the first and second antennas and attached to the another one, thereby choosing one of the first and second antennas, or a combination of one of the two antennas and the magnetic member to receive/transmit the wireless signals. | 10-03-2013 |
20140327592 | ANTENNA STRUCTURE AND WIRELESS COMMUNICATION DEVICE EMPLOYING SAME - An antenna structure includes an antenna and a metal member located between the antenna and an electronic member. The antenna is configured for receiving and sending wireless signals. An electrical length of the metal member is greater than or equal to a quarter wavelength of a resonance frequency band of the antenna. The metal member transmits wireless signals generated by the electronic member to ground to prevent signals generated by the electronic member from interfering with the antenna. | 11-06-2014 |
20140333487 | WIRELESS COMMUNICATION DEVICE - An exemplary wireless communication device includes a circuit board, a first antenna, a second antenna, and an end portion. The circuit board includes a feed terminal. The first antenna is located on the circuit board adjacent to the feed terminal. The second antenna is electronically connected to the feed terminal. The end portion serves as a portion of a metal housing of the wireless communication device and includes a positioning portion. The positioning portion secures the first antenna and the end portion to the circuit board. | 11-13-2014 |
Patent application number | Description | Published |
20090311628 | METHOD FOR ETCHING AN ULTRA THIN FILM - A method for etching an ultra thin film is provided which includes providing a substrate having the ultra thin film formed thereon, patterning a photosensitive layer formed over the ultra thin film, etching the ultra thin film using the patterned photosensitive layer, and removing the patterned photosensitive layer. The etching process includes utilizing an etch material with a diffusion resistant carrier such that the etch material is prevented from diffusing to a region underneath the photosensitive layer and removing portions of the ultra thin film underneath the photosensitive layer. | 12-17-2009 |
20100261118 | Intensity Selective Exposure Method And Apparatus - A gradated photomask is provided. The photomask includes a first region including a first plurality of sub-resolution features and a second region including a second plurality of sub-resolution features. The first region blocks a first percentage of the incident radiation. The second region blocks a second percentage of the incident radiation. The first and second percentage are different. An intensity selective exposure method is also provided. | 10-14-2010 |
20100279234 | DOUBLE PATTERNING METHOD USING METALLIC COMPOUND MASK LAYER - A hard mask layer and a developable bottom anti-reflective coating (dBARC) layer are formed over a dielectric layer of a substrate. A first photosensitive layer is formed above the dBARC layer, exposed, and developed to form a first pattern. The dBARC layer is developed. The first pattern is etched into the hard mask layer to form a first pattern of openings in the hard mask layer. Following removal of the first photosensitive layer, a second photosensitive layer is formed within the first pattern of openings. The second photosensitive layer is exposed and developed to form a second pattern. The dBARC layer is developed. The second pattern is etched into the hard mask layer to form a second pattern of openings in the hard mask layer. Following the removal of the second photosensitive layer and the dBARC layer, the first and the second patterns are etched into the dielectric layer. | 11-04-2010 |
20110217630 | INTENSITY SELECTIVE EXPOSURE PHOTOMASK - An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage. Each of the features of the first and second array includes an opening disposed in an area of attenuating material. | 09-08-2011 |
20120040278 | INTENSITY SELECTIVE EXPOSURE PHOTOMASK - An intensity selective exposure photomask, also describes as a gradated photomask, is provided. The photomask includes a first region including a first array of sub-resolution features. The first region blocks a first percentage of the incident radiation. The photomask also includes a second region including a second array of sub-resolution features. The second region blocks a second percentage of the incident radiation different that the first percentage. | 02-16-2012 |
20120074498 | METHOD AND APPARATUS FOR IMPROVING GATE CONTACT - A method of fabricating a semiconductor device includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface disposed below the first surface, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface disposed below the first surface, a gate structure, and a contact engaging the gate structure over the recess. | 03-29-2012 |
20130056837 | SELF-ALIGNED INSULATED FILM FOR HIGH-K METAL GATE DEVICE - A method of making an integrated circuit includes providing a semiconductor substrate and forming a gate dielectric over the substrate, such as a high-k dielectric. A metal gate structure is formed over the semiconductor substrate and the gate dielectric and a thin dielectric film is formed over that. The thin dielectric film includes oxynitride combined with metal from the metal gate. The method further includes providing an interlayer dielectric (ILD) on either side of the metal gate structure. | 03-07-2013 |
20130328134 | Method and Apparatus for Improving Gate Contact - A method of fabricating a semiconductor device includes providing a substrate having a first surface, forming an isolation structure disposed partly in the substrate and having an second surface higher than the first surface by a step height, removing a portion of the isolation structure to form a recess therein having a bottom surface disposed below the first surface, and forming a contact engaging the gate structure over the recess. A different aspect involves an apparatus that includes a substrate having a first surface, an isolation structure disposed partly in the substrate and having a second surface higher than the first surface by a step height, a recess extending downwardly from the second surface, the recess having a bottom surface disposed below the first surface, a gate structure, and a contact engaging the gate structure over the recess. | 12-12-2013 |
20140170537 | METHOD OF DEFINING AN INTENSITY SELECTIVE EXPOSURE PHOTOMASK - An embodiment of a feed-forward method of determining a photomask pattern is provided. The method includes providing design data associated with an integrated circuit device. A thickness of a coating layer to be used in fabricating the integrated circuit device is predicted based on the design data. This prediction is used to generate a gradating pattern. A photomask is formed having the gradating pattern. | 06-19-2014 |
20140367802 | SELF-ALIGNED INSULATED FILM FOR HIGH-K METAL GATE DEVICE - An integrated circuit includes a semiconductor substrate, a gate dielectric over the substrate, a metal gate structure over the semiconductor substrate and the gate dielectric, a dielectric film on the metal gate structure, the dielectric film comprising oxynitride combined with metal from the metal gate, and an interlayer dielectric (ILD) on either side of the metal gate structure. | 12-18-2014 |