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Chih-Wen
Chih-Wen Chang, Sanchong City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110302541 | Methods and Systems for Evaluating Checker Quality of a Verification Environment - Methods and systems for evaluating checker quality of a verification environment are provided. In some embodiments, an overall sensitivity for the verification environment and an individual sensitivity for a respective checker are calculated. The overall sensitivity is a probability that a plurality of problematic design behaviors, which are propagated to a checker system including at least one checker, can be detected by the verification environment. The individual sensitivity is a probability that a plurality of problematic design behaviors, which are propagated to at least one specific probe among a plurality of probes of a design, can be detected by the checker corresponding to the specific probe. The overall checker sensitivity numbers can show the robustness of the check system. The individual checker sensitivity can guide the user which individual checker or checkers to improve. | 12-08-2011 |
Chih-Wen Chen, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110169018 | Liquid Crystal Display Device - An exemplary liquid crystal display device includes a data line, a pixel, a first gate line, a second gate line, an additional electrode and an additional gate line. The pixel includes a first sub-pixel and a second sub-pixel. The first gate line is electrically coupled to the first sub-pixel. The second gate line is electrically coupled to the second sub-pixel. The first sub-pixel is electrically coupled to the data line to receive a signal provided from the data line. The second sub-pixel is electrically coupled to the first sub-pixel through the additional electrode and to receive a signal provided from the data line through the first sub-pixel. The additional gate line is arranged crossing over the additional electrode and whereby a compensation capacitance is formed between the additional gate line and the additional electrode. | 07-14-2011 |
| 20120013606 | Parallax Barrier and Application Thereof - Disclosed herein is a parallax barrier including a first substrate, a second substrate and a liquid crystal layer disposed between the first and the second substrates. A plurality of first strip electrodes and a plurality of second strip electrodes are arranged on the first substrate, whereas a plurality of third electrodes and a plurality of fourth electrodes are arranged on the second substrate. Each of the third electrodes has a step-shaped first portion and each of the fourth electrodes has a step-shaped second portion. | 01-19-2012 |
Chih-Wen Chen, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110141410 | TRANSFLECTIVE LIQUID CRYSTAL DISPLAY DEVICE - The present invention in one aspect relates to a transflective liquid crystal display (LCD) comprising a plurality of pixels. Each pixel includes a first structure defining a reflective area and a transmissive area adjacent to the reflective area, a second structure positioned apart from the first structure to define a single cell gap therebetween, a liquid crystal layer positioned in the cell gap, and a plurality of electrodes formed on one of the first structure and the second structure such that at least two electrodes are positioned in the transmissive area and define a first distance, d1, therebetween, and at least two electrodes are positioned in the reflective area and define a second distance, d2, therebetween, where d2>d1, preferably, d2=√{square root over (2)}d1. | 06-16-2011 |
| 20110263251 | SCANNING METHODS AND SYSTEMS FOR WIRELESS NETWORKS - Scanning methods and systems for wireless networks are provided. In response to an operation, at least a waiting time corresponding to a wireless network scanning procedure is changed from a default time length to a predefined time length, and the wireless network scanning procedure is accordingly performed. When the wireless network scanning procedure is terminated, the waiting time is changed from the predefined time length back to the default time length. If a specific wireless access point detected in a second scanning operation is not detected in a first scanning operation, which is performed subsequent to the second scanning operation, an alive count corresponding to the specific wireless access point is subtracted by a predefined value. If the alive count does not equal to a specific value, the specific wireless access point and at least one wireless access point detected in the first scanning operation are displayed. | 10-27-2011 |
| 20120042377 | PORTABLE DEVICE WITH PASSWORD VERIFICATION FUNCTION AND SYSTEM HAVING THEREOF - A portable device with password verification function includes several input units, a storage unit and a processing unit. The processing unit is electrically connected with the input units and the storage unit. Each of the input units is different from others. Password information is stored in the storage unit. The processing unit includes a receiving module and a password verification module. The receiving module receives several input signals from the input units respectively. The password verification module verifies if the input signals match the password information. | 02-16-2012 |
Chih-Wen Ho, Kaohsiung TW
| Patent application number | Description | Published |
|---|---|---|
| 20100109159 | BUMPED CHIP WITH DISPLACEMENT OF GOLD BUMPS - A bumped chip is revealed, including a chip, a UBM layer, an Ag bump, and a creeping-resist layer. The chip has a bonding pad and a passivation layer covering one surface of the chip and exposing the bonding pad. The UBM layer is disposed on the bonding pad and covers the passivation layer at the peripheries of the opening. The Ag bump is disposed on the UBM layer to form as a pillar bump having a top surface and a pillar sidewall. The creeping-resist layer is formed at least on the pillar sidewall to fully encapsulate the Ag bump. Therefore, the disclosed bumped chip will have no Ag-creeping due to exerting stresses nor changing of joint heights under high temperature environment to meet the bumping requirements of lead-free, high reliability, and lower cost. | 05-06-2010 |
Chih-Wen Hsiao, Hsin Chu Hsien TW
| Patent application number | Description | Published |
|---|---|---|
| 20090096738 | DRIVING CIRCUIT CAPABLE OF SIMULTANEOUSLY DRIVING THREE-COLOR BISTABLE LIQUID CRYSTALS - This invention provides a driving circuit for simultaneously driving three-color bistable liquid crystals, which employs a voltage-shift circuit to provide different-color bistable liquid crystals with respective level-shift voltages. A grey-scale voltage is respectively added to the respective level-shift voltages. By this invention, the whole grey-scale voltages are capable of falling in the voltage ranges for displaying grey scales for the different-color bistable liquid crystals. The grey-scale display can be optimized. | 04-16-2009 |
Chih-Wen Huang, Tapei TW
| Patent application number | Description | Published |
|---|---|---|
| 20100172111 | CIRCUIT BOARD - A circuit board including a first patterned metal layer and a second patterned metal layer is provided. The first patterned metal layer has metal blocks and spiral structures. A gap is kept between any two adjacent metal blocks. Each of the spiral structures is electrically connected between any two adjacent metal blocks. The second patterned metal layer is disposed beside the first patterned metal layer and has jumper segments. Each of the jumper segments has a first end and a second end opposite to the first end. Each of the spiral structures has an outer end and an inner end. The outer end is connected to one of the two adjacent metal blocks. The inner end is electrically connected to the first end of one of the jumper segments, and the second end of the jumper segment is electrically connected to the other one of the two the metal blocks. | 07-08-2010 |
Chih-Wen Huang, Kao-Hsiung Hsien TW
| Patent application number | Description | Published |
|---|---|---|
| 20090175157 | ECHO CANCELLATION DEVICE FOR FULL DUPLEX COMMUNICATION SYSTEMS - An apparatus for echo cancellation in a transceiver of a full duplex communication system, where the transceiver includes a transmitter for transmitting a transmit signal and a receiver for receiving a receive signal, includes: an echo cancellation signal generator, coupled to the transmitter, for receiving the transmit signal and for generating an echo cancellation signal according to the transmit signal, wherein the echo cancellation signal reflects an effect of an impedance of a channel and a parasitic capacitor of the transceiver; and a calculation module coupled to the transmitter, the receiver, and the echo cancellation signal generator for receiving the receive signal and for canceling the echo of the receive signal according to the echo cancellation signal to generate an echo-cancelled signal, wherein the effect of the impedance of the channel and the parasitic capacitor of the transceiver in the echo-cancelled signal is reduced. | 07-09-2009 |
Chih-Wen Huang, Taipei TW
| Patent application number | Description | Published |
|---|---|---|
| 20090056984 | SIGNAL TRANSMISSION STRUCTURE AND LAYOUT METHOD FOR THE SAME - A signal transmission structure is provided. The signal transmission structure includes conduction blocks periodically formed at a power plane, neck blocks connecting adjacent conduction blocks, and openings formed corresponding to the neck blocks at a ground plane for reducing equivalent capacitance between the neck blocks and the ground plane, so as to improve the noise isolation performance. | 03-05-2009 |
| 20100126759 | STRUCTURE OF MULTI-LAYER PRINTED CIRCUIT BOARD - A structure of a multi-layer printed circuit board includes a power layer, a ground layer, and a dielectric layer. The dielectric layer is located between the power layer and the ground layer. The dielectric layer has a relative permittivity and a relative permeability, wherein the product of the relative permittivity and the relative permeability substantially decreases along with an increase in frequency within a frequency range. | 05-27-2010 |
| 20100200281 | CIRCUIT BOARD STRUCTURE - A circuit board structure includes a dielectric layer, a first metal layer, a second metal layer and a first ferrite element. The first metal layer is disposed on an upper surface of the dielectric layer and has a first circuit area, a second circuit area and a first metallic neck connecting the first circuit and the second circuit areas. The second metal layer is disposed on a lower surface of the dielectric layer and has a third circuit area, a fourth circuit area and at least a second metallic neck connecting the third circuit and the fourth circuit areas. The orthogonal projections of the first and the second metallic necks on the upper surface are not overlapped. The first ferrite element is disposed on the upper surface and overlays at least one of the orthogonal projections of the first and the second metallic necks on the upper surface. | 08-12-2010 |
| 20110208461 | MEASUREMENT CORRECTING SYSTEM AND METHOD THEREOF - A measurement correcting system including a field measuring unit and a processing unit is provided. The field measuring unit simultaneously senses a first signal to be measured and a second signal to be measured which have opposite polarities and substantially the same magnitude, and generates a first output signal and a second output signal correspondingly. The processing unit determines the first signal to be measured according to the first output signal and the second output signal. A measurement correcting method is also provided. | 08-25-2011 |
Chih-Wen Lin, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090174049 | ULTRA THIN IMAGE SENSOR PACKAGE STRUCTURE AND METHOD FOR FABRICATION - An image sensor package having at least one chip supporting bar secured to a top surface of an image sensor chip. The thickness of the chip supporting bar is absorbed within a vertical dimension of wire loops that connect bonding pads to leads so that the chip supporting bar does not contribute to the thickness of the image sensor package. An exposed back surface of the image sensor chip enhances thermal dissipation. | 07-09-2009 |
Chih-Wen Liu, Taipei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090012363 | ENDOSCOPE AND MAGNETIC FIELD CONTROL METHOD THEREOF - An endoscope device is provided. The endoscope device includes a capsule sensor entering a human body for detection and sending a signal, a driving device movably disposed outside of the human body and moving and rotating the capsule sensor in the human body with non-contact force for omni-directional human body detection, a data receiving device disposed outside of the human body and receiving signals from the capsule sensor, and a power supply device providing power to the driving device and the data receiving device. | 01-08-2009 |
Chih-Wen Lu, Pingtung County TW
| Patent application number | Description | Published |
|---|---|---|
| 20120089756 | NETWORK-ATTACHED STORAGE AND METHOD OF CONFIGURING NETWORK-ATTACHED STORAGE - When a NAS apparatus is directly connected to a network and an external apparatus simultaneously, the external apparatus is able to access the NAS apparatus, and the NAS apparatus concurrently communicates with the network for executing a specific function. A method of configuring the NAS apparatus includes: allocating a first storage unit in the NAS apparatus; and setting an attribute of the first storage unit such that the first storage unit is allowed to be read by the NAS apparatus or the external apparatus, and written by the NAS apparatus or the external apparatus. | 04-12-2012 |
Chih-Wen Lu, Jhumen Village TW
| Patent application number | Description | Published |
|---|---|---|
| 20090115715 | LIQUID CRYSTAL DISPLAY SOURCE DRIVER INTEGRATED CIRCUIT - A source driver eliminates the need for a level shifter and enables the use of a low voltage digital-to-analog converter by using an operational buffer that performs voltage amplification in addition to driving a TFT panel. | 05-07-2009 |
Chih-Wen Yang, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20090251185 | DATA RETENTION DEVICE FOR MULTIPLE POWER DOMAINS - A data retention device includes a first latch disposed between a data input terminal and a data output terminal for storing a data signal received from the data input terminal and transmitting the data signal through a data forward path to the data output terminal according to a clock signal in an operational mode; a second latch disposed in a branch of the data forward path between the first latch and the data output terminal for receiving the data signal in the operational mode and retaining the data signal in a sleep mode; and a first tri-state buffer disposed in the data forward path between the first latch and the branched second latch and enabled to conduct the data forward path in the operational mode and disabled to cut off the data forward path in the sleep mode according to a data retention signal. | 10-08-2009 |
Chih-Wen Yang, Taipei TW
| Patent application number | Description | Published |
|---|---|---|
| 20100142198 | Configurable Light Emitting System - A configurable light emitting system includes a plurality of light emitting units, at least a first external conductor, and at least a second external conductor. Each of the light emitting units includes an anode, a cathode, a first electrical contact electrically connected to the anode, and a second electrical contact electrically connected to the cathode. The first external conductor is electrically connected to the first electrical contact of each of the light emitting unit, and configured to supply a positive voltage thereto. The second external conductor is electrically connected to the second electrical contact of each of the light emitting unit, and configured to supply a negative voltage thereto. The plurality of the light emitting units are configured as a tile structure or a brick structure, and are electrically connected together through the first external conductor and second external conductor. | 06-10-2010 |
| 20100193825 | LIGHT-EMITTING DIODE PACKAGE AND METHOD FOR FABRICATING THE SAME - A light-emitting diode (LED) package is disclosed. The LED package includes a metal substrate, a first insulating polymer layer disposed on the metal substrate, an upper metal layer disposed on surface of the first insulating polymer layer, and at least a LED chip. The first insulating polymer layer includes a cavity and first insulating polymer layer surrounding the cavity includes a reflecting slope, and the LED chip is disposed in the cavity of the first insulating polymer layer and electrically connected to the upper metal layer. | 08-05-2010 |