Patent application number | Description | Published |
20110101527 | MECHANISMS FOR FORMING COPPER PILLAR BUMPS - The mechanism of forming a metal bump structure described above resolves the delamination issues between a conductive layer on a substrate and a metal bump connected to the conductive layer. The conductive layer can be a metal pad, a post passivation interconnect (PPI) layer, or a top metal layer. By performing an in-situ deposition of a protective conductive layer over the conductive layer (or base conductive layer), the under bump metallurgy (UBM) layer of the metal bump adheres better to the conductive layer and reduces the occurrence of interfacial delamination. In some embodiments, a copper diffusion barrier sub-layer in the UBM layer can be removed. In some other embodiments, the UBM layer is not needed if the metal bump is deposited by a non-plating process and the metal bump is not made of copper. | 05-05-2011 |
20110254151 | METHOD FOR FABRICATING BUMP STRUCTURE WITHOUT UBM UNDERCUT - A method for fabricating bump structure without UBM undercut uses an electroless Cu plating process to selectively form a Cu UBM layer on a Ti UBM layer within an opening of a photoresist layer. After stripping the photoresist layer, there is no need to perform a wet etching process on the Cu UBM layer, and thereby the UBM structure has a non-undercut profile. | 10-20-2011 |
20110260317 | CU PILLAR BUMP WITH ELECTROLYTIC METAL SIDEWALL PROTECTION - A copper pillar bump has a sidewall protection layer formed of an electrolytic metal layer. The electrolytic metal layer is an electrolytic nickel layer, an electrolytic gold layer, and electrolytic copper layer, or an electrolytic silver layer. | 10-27-2011 |
20110287628 | Activation Treatments in Plating Processes - A method of forming a device includes performing a first plating process to form a first metallic feature, and performing an activation treatment to a surface of the first metallic feature in an activation treatment solution, wherein the activation treatment solution includes a treatment agent in de-ionized (DI) water. After the step of performing the activation treatment, performing a second plating process to form a second metallic feature and contacting the surface of the first metallic feature. | 11-24-2011 |
20120007228 | CONDUCTIVE PILLAR FOR SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURE - An embodiment of the disclosure includes a conductive pillar on a semiconductor die. A substrate is provided. A bond pad is over the substrate. A conductive pillar is over the bond pad. The conductive pillar has a top surface, edge sidewalls and a height. A cap layer is over the top surface of the conductive pillar. The cap layer extends along the edge sidewalls of the conductive pillar for a length. A solder material is over a top surface of the cap layer. | 01-12-2012 |
20120043654 | MECHANISMS FOR FORMING COPPER PILLAR BUMPS USING PATTERNED ANODES - The mechanisms of preparing bump structures described by using patterned anodes may simplify bump-making process, reduce manufacturing cost, and improve thickness uniformity within die and across the wafer. In addition, the mechanisms described above allow forming bumps with different heights to allow bumps to be integrated with elements on a substrate with different heights. Bumps with different heights expand the application of copper post bumps to enable further chip integration. | 02-23-2012 |
20120091574 | CONDUCTIVE PILLAR STRUCTURE - The invention relates to a bump structure of a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a contact pad over the substrate; a passivation layer extending over the substrate having an opening over the contact pad; and a conductive pillar over the opening of the passivation layer, wherein the conductive pillar comprises an upper portion substantially perpendicular to a surface of the substrate and a lower portion having tapered sidewalls. | 04-19-2012 |
20120178251 | METHOD OF FORMING METAL PILLAR - The disclosure relates to fabrication of to a metal pillar. An exemplary method of fabricating a semiconductor device comprises the steps of providing a substrate having a contact pad; forming a passivation layer extending over the substrate having an opening over the contact pad; forming a metal pillar over the contact pad and a portion of the passivation layer; forming a solder layer over the metal pillar; and causing sidewalls of the metal pillar to react with an organic compound to form a self-assembled monolayer or self-assembled multi-layers of the organic compound on the sidewalls of the metal pillar. | 07-12-2012 |
20120267781 | MECHANISMS FOR FORMING COPPER PILLAR BUMPS USING PATTERNED ANODES - This disclosure relates to a bump structure on a substrate including a copper layer, wherein the copper layer fills an opening created in a dielectric layer and a polymer layer. The bump structure further includes an under-bump-metallurgy (UBM) layer lines the opening and the copper layer is deposited over the UBM layer. The bump structure further includes a surface of the copper layer facing away from the substrate is curved. This disclosure also relates to two bump structures with different heights on a substrate where a thickness of the first bump structure is different than a thickness of the second bump structure. This disclosure also relates to a semiconductor device including a bump structure. | 10-25-2012 |
20120299181 | Package-on-Package Process for Applying Molding Compound - A method of packaging includes placing a package component over a release film, wherein solder balls on a surface of the package component are in physical contact with the release film. Next, A molding compound filled between the release film and the package component is cured, wherein during the step of curing, the solder balls remain in physical contact with the release film. | 11-29-2012 |
20120322255 | Metal Bump Formation - A system and method for forming metal bumps is provided. An embodiment comprises attaching conductive material to a carrier medium and then contacting the conductive material to conductive regions of a substrate. Portions of the conductive material are then bonded to the conductive regions using a bonding process to form conductive caps on the conductive regions, and residual conductive material and the carrier medium are removed. A reflow process is used to reflow the conductive caps into conductive bumps. | 12-20-2012 |
20130009307 | Forming Wafer-Level Chip Scale Package Structures with Reduced number of Seed Layers - A method includes forming a passivation layer over a metal pad, which is overlying a semiconductor substrate. A first opening is formed in the passivation layer, with a portion of the metal pad exposed through the first opening. A seed layer is formed over the passivation layer and to electrically coupled to the metal pad. The seed layer further includes a portion over the passivation layer. A first mask is formed over the seed layer, wherein the first mask has a second opening directly over at least a portion of the metal pad. A PPI is formed over the seed layer and in the second opening. A second mask is formed over the first mask, with a third opening formed in the second mask. A portion of a metal bump is formed in the third opening. After the step of forming the portion of the metal bump, the first and the second masks are removed. | 01-10-2013 |
20130062761 | Packaging Methods and Structures for Semiconductor Devices - Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL. | 03-14-2013 |
20130075921 | Forming Packages Having Polymer-Based Substrates - A method includes applying a polymer-comprising material over a carrier, and forming a via over the carrier. The via is located inside the polymer-comprising material, and substantially penetrates through the polymer-comprising material. A first redistribution line is formed on a first side of the polymer-comprising material. A second redistribution line is formed on a second side of the polymer-comprising material opposite to the first side. The first redistribution line is electrically coupled to the second redistribution line through the via. | 03-28-2013 |
20130089952 | Packaging Process Tools and Packaging Methods for Semiconductor Devices - Packaging process tools and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure including a frame. The frame includes a plurality of apertures adapted to retain a plurality of integrated circuit dies therein. The frame includes at least one hollow region. | 04-11-2013 |
20130093078 | Process for Forming Package-on-Package Structures - A device includes an inter-layer dielectric, a device die under the inter-layer dielectric; and a die-attach film under the inter-layer dielectric and over the device die, wherein the die-attach film is attached to the device die. A plurality of redistribution lines includes portions level with the die-attach film. A plurality of Z-interconnects is electronically coupled to the device die and the plurality of redistribution lines. A polymer-comprising material is under the inter-layer dielectric. The device die, the die-attach film, and the plurality of Z-interconnects are disposed in the polymer-comprising material. | 04-18-2013 |
20130093097 | Package-On-Package (PoP) Structure and Method - A package-on-package (PoP) structure comprises a first package and a second package. The first package comprises a first die, a second die, and a core material. The core material has a first surface and a second surface. A first redistribution layer (RDL) is on the first surface, and a second RDL is on the second surface. The first die is disposed in the core material between the first surface and the second surface. The second die is coupled to one of the first RDL and the second RDL. The second package comprises a third die and an interposer. The interposer has a first side and a second side. The third die is coupled to the second side of the interposer. The first package is coupled to the second package by first electrical connectors coupled to the second side of the interposer and the first RDL. | 04-18-2013 |
20130095611 | Packaging Methods for Semiconductor Devices - Packaging methods for semiconductor devices are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a workpiece including a plurality of packaging substrates. A portion of the workpiece is removed between the plurality of packaging substrates. A die is attached to each of the plurality of packaging substrates. | 04-18-2013 |
20130099370 | SEMICONDUCTOR PACKAGE - A semiconductor package includes a workpiece with a conductive trace and a chip with a conductive pillar. The chip is attached to the workpiece and a solder joint region is formed between the conductive pillar and the conductive trace. The distance between the conductive pillar and the conductive trace is less than or equal to about 16 μm. | 04-25-2013 |
20130113116 | Contact and Method of Formation - A system and method for forming contacts is provided. An embodiment comprises forming the contacts on a substrate and then coining the contacts by physically shaping them using, e.g., a molding chamber. The physical shaping of the contacts may be performed using a patterned portion of the molding chamber or else by placing a patterned stencil around the contacts prior before a force is applied to physically reshape the contacts. The contacts may be reshaped into a cylindrical, oval, cuboid, or rectangular shape, for example. | 05-09-2013 |
20130119539 | Package Structures and Methods for Forming the Same - A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A solder region is disposed in the polymer region and electrically coupled to the redistribution line. The solder region includes a second flat top surface not higher than the first flat top surface. | 05-16-2013 |
20130122652 | Methods for Performing Reflow in Bonding Processes - A method includes placing a cover over a lower package component, wherein the cover comprises an opening aligned to the lower package component. An upper package component is placed over the lower package component. The upper package component is aligned to the opening, and a solder region is dispose between the upper package component and the lower package component. The cover and the upper package component are exposed to a radiation to reflow the solder region. | 05-16-2013 |
20130143361 | Packaging Process Tools and Systems, and Packaging Methods for Semiconductor Devices - Packaging process tools and systems, and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure for supporting package substrates or integrated circuit die during a packaging process for the integrated circuit die. The mechanical structure includes a low thermal conductivity material disposed thereon. | 06-06-2013 |
20130181338 | Package on Package Interconnect Structure - A structure comprises a post passivation interconnect layer formed over a semiconductor substrate, a metal bump formed over the post passivation interconnect layer and a molding compound layer formed over the semiconductor substrate. A lower portion of the metal bump is embedded in the molding compound layer and a middle portion of the metal bump is surrounded by a concave meniscus molding compound protection layer. | 07-18-2013 |
20130234317 | Packaging Methods and Packaged Semiconductor Devices - Packaging methods and packaged semiconductor devices are disclosed. In one embodiment, a packaging method includes providing a first die, partially packaging the first die, and forming a plurality of solder balls on a surface of the partially packaged first die. An epoxy flux is disposed over the plurality of solder balls. A second die is provided, and the second die is partially packaged. The plurality of solder balls is coupled to the partially packaged second die. | 09-12-2013 |
20130285238 | STUD BUMP STRUCTURE FOR SEMICONDUCTOR PACKAGE ASSEMBLIES - A semiconductor package structure comprises a substrate, a die bonded to the substrate, and one or more stud bump structures connecting the die to the substrate, wherein each of the stud bump structures having a stud bump and a solder ball encapsulating the stud bump to enhance thermal dissipation and reduce high stress concentrations in the semiconductor package structure. | 10-31-2013 |
20130295762 | CU PILLAR BUMP WITH ELECTROLYTIC METAL SIDEWALL PROTECTION - A method of forming a bump structure includes providing a semiconductor substrate and forming an under-bump-metallurgy (UBM) layer on the semiconductor substrate. The method further includes forming a mask layer on the UBM layer, wherein the mask layer has an opening exposing a portion of the UBM layer. The method further includes forming a copper layer in the opening of the mask layer and removing a portion of the mask layer to form a space between the copper layer and the mask layer. The method further includes performing an electrolytic process to fill the space with a metal layer and removing the mask layer. | 11-07-2013 |
20130307140 | PACKAGING WITH INTERPOSER FRAME - The mechanisms of using an interposer frame to package a semiconductor die enables fan-out structures and reduces form factor for the packaged semiconductor die. The mechanisms involve using a molding compound to attach the semiconductor die to the interposer frame and forming a redistribution layer on one or both sides of the semiconductor die. The redistribution layer(s) in the package enables fan-out connections and formation of external connection structures. Conductive columns in the interposer frame assist in thermal management. | 11-21-2013 |
20130309621 | METHOD AND APPARATUS FOR ADJUSTING WAFER WARPAGE - A method for adjusting the warpage of a wafer, includes providing a wafer having a center portion and edge portions and providing a holding table having a holding area thereon for holding the wafer. The wafer is placed onto the holding table with the center portion higher than the edge portions and thereafter pressed onto the holding area such that the wafer is attracted to and held onto the holding table by self-suction force. The wafer is heated at a predetermined temperature and for a predetermined time in accordance with an amount of warpage of the wafer in order to achieve a substantially flat wafer or a predetermined wafer level. | 11-21-2013 |
20130334710 | Contact and Method of Formation - A system and method for forming contacts is provided. An embodiment comprises forming the contacts on a substrate and then coining the contacts by physically shaping them using, e.g., a molding chamber. The physical shaping of the contacts may be performed using a patterned portion of the molding chamber or else by placing a patterned stencil around the contacts prior before a force is applied to physically reshape the contacts. The contacts may be reshaped into a cylindrical, oval, cuboid, or rectangular shape, for example. | 12-19-2013 |
20140008786 | BUMP-ON-TRACE PACKAGING STRUCTURE AND METHOD FOR FORMING THE SAME - A device comprises a first package component, and a first metal trace and a second metal trace on a top surface of the first package component. The device further includes a dielectric mask layer covering the top surface of the first package component, the first metal trace and the second metal trace, wherein the dielectric mask layer has an opening therein exposing the first metal trace. The device also includes a second package component and an interconnect formed on the second package component, the interconnect having a metal bump and a solder bump formed on the metal bump, wherein the solder bump contacts the first metal trace in the opening of the dielectric mask layer. | 01-09-2014 |
20140231988 | Packaging Methods and Packaged Semiconductor Devices - Packaging methods and packaged semiconductor devices are disclosed. In one embodiment, a packaging method includes providing a first die, partially packaging the first die, and forming a plurality of solder balls on a surface of the partially packaged first die. An epoxy flux is disposed over the plurality of solder balls. A second die is provided, and the second die is partially packaged. The plurality of solder balls is coupled to the partially packaged second die. | 08-21-2014 |
20140264840 | Package-on-Package Structure - A device comprises a top package mounted on a bottom package, wherein the bottom package comprises a plurality of interconnection components and the bottom package comprises a plurality of first bumps formed on a first side of the bottom package, a semiconductor die is bonded on a second side of the bottom package, wherein the semiconductor die is electrically coupled to the first bumps through the interconnection components and the semiconductor die is located between the top package and the bottom package, and an underfill layer formed between the top package and the bottom package. | 09-18-2014 |
20140264842 | Package-on-Package Structure and Method of Forming Same - A device comprises a bottom package comprising interconnect structures, first bumps on a first side and metal bumps on a second side, a semiconductor die bonded on the bottom package, wherein the semiconductor die is electrically coupled to the first bumps through the interconnect structures. The device further comprises a top package bonded on the second side of the bottom package, wherein the top package comprises second bumps, and wherein each second bump and a corresponding metal bump form a joint structure between the top package and the bottom package and an underfill layer formed between the top package and the bottom package, wherein the metal bumps are embedded in the underfill layer. | 09-18-2014 |
20140264856 | Package-on-Package Structures and Methods for Forming the Same - A package includes a package component, which further includes a top surface and a metal pad at the top surface of the package component. The package further includes a non-reflowable electrical connector over and bonded to the metal pad, and a molding material over the package component. The non-reflowable electrical connector is molded in the molding material and in contact with the molding material. The non-reflowable electrical connector has a top surface lower than a top surface of the molding compound. | 09-18-2014 |
20140264930 | Fan-Out Interconnect Structure and Method for Forming Same - A method embodiment includes forming a sacrificial film layer over a top surface of a die, the die having a contact pad at the top surface. The die is attached to a carrier, and a molding compound is formed over the die and the sacrificial film layer. The molding compound extends along sidewalls of the die. The sacrificial film layer is exposed. The contact pad is exposed by removing at least a portion of the sacrificial film layer. A first polymer layer is formed over the die, and a redistribution layer (RDL) is formed over the die and electrically connects to the contact pad. | 09-18-2014 |
20140374922 | Alignment in the Packaging of Integrated Circuits - A method includes aligning a top package to a bottom package using an alignment mark in the bottom package, and placing the top package over the bottom package, wherein the top package is aligned to the bottom package after the placing the top package over the bottom package. A reflow is then performed to bond the top package to the bottom package. | 12-25-2014 |