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Chih-Wei Lin
Chih-Wei Lin, Xinfeng Township TW
| Patent application number | Description | Published |
|---|---|---|
| 20110101527 | MECHANISMS FOR FORMING COPPER PILLAR BUMPS - The mechanism of forming a metal bump structure described above resolves the delamination issues between a conductive layer on a substrate and a metal bump connected to the conductive layer. The conductive layer can be a metal pad, a post passivation interconnect (PPI) layer, or a top metal layer. By performing an in-situ deposition of a protective conductive layer over the conductive layer (or base conductive layer), the under bump metallurgy (UBM) layer of the metal bump adheres better to the conductive layer and reduces the occurrence of interfacial delamination. In some embodiments, a copper diffusion barrier sub-layer in the UBM layer can be removed. In some other embodiments, the UBM layer is not needed if the metal bump is deposited by a non-plating process and the metal bump is not made of copper. | 05-05-2011 |
Chih-Wei Lin, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20100044732 | Light Emitting Diode Structure and Method of Forming the Same - A light emitting diode structure and a light emitting diode structure forming method are provided. The light emitting diode structure includes a base, a diode chip, and a package lens. The diode chip is mounted on the base. The package lens covers the diode chip. The surface of the package lens includes a plurality of dot structures. The steps of the method include mounting a light-emitting diode chip on a base, assembling a package lens to cover the light emitting diodes chip, and forming a plurality of dot structures on the surface of the package lens. | 02-25-2010 |
| 20110033787 | FRAME CELL FOR SHOT LAYOUT FLEXIBILITY - A method includes receiving an integrated circuit chip size and determining a frame structure segment size based on the chip size. The frame structure segment size is less than the chip size. An initial shot layout having a chip count is established in which a number of shots, each including at least one frame structure segment and at least one chip, are arranged in vertically and horizontally aligned columns and rows. At least one additional shot layout is established in which at least one of a row or column of shots is offset from an adjacent row or column of shots. The initial shot layout is compared to the at least one additional shot layout, and a final shot layout is selected based in part on the total number of shots in the shot layout and has a final chip count that is greater than or equal to the initial chip count. | 02-10-2011 |
Chih-Wei Lin, Taoyuan City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100270604 | Non-Volatile Memories and Methods of Fabrication Thereof - Non-volatile memories and methods of fabrication thereof are described. In one embodiment, a method of fabricating a semiconductor device includes forming an oxide layer over a semiconductor substrate, and exposing the oxide layer to a first nitridation step to form a first nitrogen rich region. The first nitrogen rich region is disposed adjacent an interface between the oxide layer and the semiconductor substrate. After the first nitridation step, the oxide layer is exposed to a second nitridation step to form a second nitrogen rich region. A first gate electrode is formed on the oxide layer, wherein the second nitrogen rich region is disposed adjacent an interface between the oxide layer and the first gate electrode. | 10-28-2010 |
Chih-Wei Lin, Taipei County TW
| Patent application number | Description | Published |
|---|---|---|
| 20080200041 | STORAGE DEVICE - The present disclosure relates to a storage device. The storage device comprises a frame having a hole and a printed circuit board embedded in the frame, wherein the printed circuit board has an extended part for forming a connector. The connector may pass through the hole and is exposed out the frame for interfacing the storage device with a host device. At least one memory device is mounted to the printed circuit board and electrically connected to the printed circuit board. | 08-21-2008 |
| 20100109855 | SOUNDER CONTROL CIRCUIT, SOUNDER SYSTEM AND METHOD FOR VEHICLE - A sounder control circuit is applicable to for a vehicle with a plurality of sounders, in which each sounder is used for generating a sound signal toward a different direction respectively. The sounder control circuit includes a switch module, a control module and a driving module. The switch module has a plurality of switches, and outputs an operation signal to the control module according to a status of each of the switches. Thus, the control module outputs a control signal to the driving module according to the operation signal for driving at least one of the sounders to output the sound signal. | 05-06-2010 |
Chih-Wei Lin, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20100098292 | Image Detecting Method and System Thereof - An image detecting method and a system thereof are provided. The image detecting method includes the following steps. An original image is captured. A moving-object image of the original image is created. An edge-straight-line image of the original image is created, wherein the edge-straight-line image comprises a plurality of edge-straight-lines. Whether the original image has a mechanical moving-object image is detected according to the length, the parallelism and the gap of the part of the edge-straight-lines corresponding to the moving-object image. | 04-22-2010 |
Chih-Wei Lin, Taipei TW
| Patent application number | Description | Published |
|---|---|---|
| 20090295357 | VARIABLE-FREQUENCY AND MULTI-PHASE VOLTAGE REGULATOR MODULE AND CONTROL METHOD OF THE SAME - A control method of a variable-frequency and multi-phase voltage regulator module is provided. The variable-frequency and multi-phase voltage regulator module is connected to a central processing unit and embedded on a motherboard for providing a central-processing-unit current. The control method includes steps of: detecting an intensity of a central-processing-unit current of the central processing unit; providing a power to the central processing unit via M number of phases based on a first switching frequency if the intensity of the central-processing-unit current is greater than a reference-current value; and providing a power to the central processing unit via N number of phases based on a second switching frequency if the intensity of the central-processing-unit current is less than the reference-current value. | 12-03-2009 |
| 20090327770 | POWER SUPPLY SYSTEM AND POWER SUPPLYING CONTROL METHOD - A power supply system adopting two power supplies connected in parallel includes a first power supply comprising a first voltage-output terminal; a second power supply comprising a second voltage-output terminal; a first switch circuit comprising an input terminal connected to the first voltage-output terminal; a second switch circuit comprising an input terminal connected to the second voltage-output terminal; and a plug comprising a first pin connected to both an output terminal of the first switch circuit and an output terminal of the second switch circuit; wherein the voltage outputted from the first voltage-output terminal is equal to the voltage outputted from the second voltage-output terminal. | 12-31-2009 |
| 20090327771 | POWER SUPPLY SYSTEM AND POWER SUPPLYING CONTROL METHOD - A power supplying control method of a computer system for use with a first power supply and a second power supply both providing a first specific voltage to a motherboard, including steps of: detecting whether the first power supply and the second power supply, outputting the first specific voltage, are at a stable state; outputting the first specific voltage to a first pin when the first power supply is at the stable state; outputting the first specific voltage to the first pin when the second power supply is at the stable state; and outputting the first specific voltage to the motherboard via the first pin. | 12-31-2009 |
| 20110115447 | MULTIPHASE POWER SUPPLY DEVICE AND CURRENT ADJUSTING METHOD THEREOF - A multiphase power supply device and a current adjusting method thereof are provided in the application. The multiphase power supply device outputs power sources and currents with different phases to a microprocessor, and a detection module detects present temperature values of each phase power source to adjust currents of each phase power source to achieve thermal balance. The multiphase power supply device further can automatically measure the power efficiency and display results including the detected temperature values of each phase power source and the power efficiency on a screen, and thus the user can know the operation efficiency of the power supply device conveniently. | 05-19-2011 |
Chih-Wei Lin, Chu-Nan TW
| Patent application number | Description | Published |
|---|---|---|
| 20090097249 | LIGHT EMITTING DIODE BASED LIGHT SOURCE ASSEMBLY - An LED based light source assembly ( | 04-16-2009 |
Chih-Wei Lin, Gueiren Township TW
| Patent application number | Description | Published |
|---|---|---|
| 20080229574 | Self chip redistribution apparatus and method for the same - The present invention provides an apparatus and a method for self chip redistribution. The apparatus of the present invention comprises a glass base on which a trench and a cavity formed by a layer of photo resistance. Chips are picked from a sawed wafer and placed on the glass base and moved by fluid flow to the front of index bar. The glass base and the index bar vibrate with low frequency to fill chips into chip cavities. The present invention further provides a method for self chip redistribution, comprising providing a self redistribution tool, transferring redistributed chips onto a panel forming tool, forming a chip panel and separating said chip panel from panel forming tool. | 09-25-2008 |
| 20080248614 | WAFER LEVEL PACKAGE WITH GOOD CTE PERFORMANCE - The present invention provides a structure of package comprising a substrate with a pre-formed die receiving cavity formed and/or terminal contact metal pads formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. At least one re-distribution built up layer (RDL) is formed on the dielectric layer and coupled to the die via contact pad. Connecting structure, for example, UBM is formed over the re-distribution built up layer. Terminal Conductive bumps are coupled to the UBM. | 10-09-2008 |
Chih-Wei Lin, Tainan County TW
| Patent application number | Description | Published |
|---|---|---|
| 20080237834 | CHIP PACKAGING STRUCTURE AND CHIP PACKAGING PROCESS - A chip packaging structure comprising a chip, a plurality of conductive pillars surrounding the chip, an encapsulation encapsulating the chip and the conductive pillars, and a connecting layer is provided. The encapsulation has a first side and a second side corresponding to the first side. The connecting layer is disposed at the first side of the encapsulation and electrically connected between the chip and the conductive pillars. Furthermore, a chip packaging process accompanying the chip packaging structure is also provided. The chip packaging structure is more useful and powerful and is suitable for various chip packaging applications, and the chip packaging process can reduce the manufacturing time and save the production cost. | 10-02-2008 |
Chih-Wei Lin, Tainan Hsien TW
| Patent application number | Description | Published |
|---|---|---|
| 20080197260 | COMPUTER HOUSING - A computer housing includes: a housing body; a first supporting plate mounted in the housing body; a second supporting plate mounted in the housing body and cooperating with the first supporting plate to define a mounting space therebetween; and an operating lever pivoted to the second supporting plate, formed with an engaging tongue, and rotatable relative to the second supporting plate between a first angular position, in which the engaging tongue extends into the mounting space for retaining a box-like device in the mounting space, and a second angular position, in which the engaging tongue is disposed outside of the mounting space for permitting removal of the box-like device. | 08-21-2008 |
Chih-Wei Lin, Taichung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110128481 | DISPLAY DEVICE AND METHOD OF MEASURING SURFACE STRUCTURE THEREOF - A display device and a method of measuring a surface structure of the same are provided. The display device includes first and second substrates, first and second patterned light-shielding layers, and first and second pixel units. The first patterned light-shielding layer disposed on a surface of the first substrate includes first openings. The second patterned light-shielding layer disposed on the surface of the first substrate in the first patterned light-shielding layer includes second openings. The first pixel unit includes first and second protrusions. The first protrusion correspondingly covers the first openings and a portion of the first patterned light-shielding layer. The second protrusion is disposed in the first and second patterned light-shielding layers. The second pixel unit includes a third protrusion correspondingly covering the second openings and a portion of the second patterned light-shielding layer, wherein sizes of the second openings are smaller than sizes of the first openings. | 06-02-2011 |