Patent application number | Description | Published |
20140223031 | CLOCK DOMAIN CROSSING SERIAL INTERFACE, DIRECT LATCHING, AND RESPONSE CODES - Aspects of a clock domain crossing serial interface, direct latching over the serial interface, and response codes are described. In various embodiments, a data communication command received over a serial interface is identified, and an address received over the serial interface is resolved to access a register bank. In a write operation, depending upon whether the address falls within a direct latch address range of the register bank, data may be directly latched into a direct latch register of the register bank or into a first-in-first-out register. For both read and write operations, reference may be made to a status register of the serial interface to identify or mitigate error conditions, and wait times may be relied upon to account for a clock domain crossing. After each of the read and write operations, a response code including a status indictor may be communicated. | 08-07-2014 |
20140223153 | POWER MODE REGISTER REDUCTION AND POWER RAIL BRING UP ENHANCEMENT - Aspects of power mode register reduction and power rail bring up enhancements are described. In one embodiment, an operating parameter for a first power rail is set by power management circuit according to a predetermined programmed setting. In connection with a wait time, the power rail is enabled, and a processor is released to start. In turn, at least one of a command to modify the operating parameter for the first power rail or a command to set an operating parameter for a second power rail is received from the processor over a high speed interface. By accessing a grouped operating register for a group of power rails, the processor can update or modify settings of an entire group of power rails at one time. In connection with the processor, the power management circuit can power up a plurality of power rails in a flexible and efficient manner. | 08-07-2014 |
20150186209 | CLOCK DOMAIN CROSSING SERIAL INTERFACE - A method for serial interface clock domain crossing includes identifying a data communication command received over a serial interface. An address is decoded to determine whether the address falls within a direct latch address range of a register bank. Data is communicated over the serial interface. A multiplexed output clock is generated, for writing to and reading from the register bank, based on at least one of a current system operating state and a refresh control signal from a host processor. | 07-02-2015 |
Patent application number | Description | Published |
20080317069 | Speed negotiation for multi-speed communication devices - A method includes defining a pattern of time intervals, each time interval having a respective assigned communication speed, which alternates among multiple communication speeds supported by a first communication device. Synchronization requests are transmitted over a communication medium from the first communication device to a second communication device at the respective communication speed that is assigned in each interval in accordance with the pattern. While transmitting the synchronization requests, synchronization replies sent over the communication medium in response to the synchronization requests are received only at the respective communication speed that is assigned in each interval. Responsively to receiving the synchronization replies from the second communication device, one or more common communication speeds that are supported by both the first and the second communication devices are identified. Communication is established between the first and second communication devices over the communication medium using one of the common communication speeds. | 12-25-2008 |
20140032591 | SYSTEM AND METHOD FOR IMPROVING HARDWARE UTILIZATION FOR A BIDIRECTIONAL ACCESS CONTROL LIST IN A LOW LATENCY HIGH-THROUGHPUT NETWORK - A method in an example embodiment includes creating a first search key from variable data of a message received in a network environment, creating a second search key from constant data of the message, identifying a first database entry in a first database based on the first search key, and identifying a second database entry in a second database based on the second search key. The method can also include performing an action associated with the first database entry when a correlation is identified between the first and second database entries. In specific embodiments, the variable data are modified and the constant data are not modified. The first search key can be created prior or subsequent to forwarding the message. In further embodiments, the correlation is identified when an offset of the first database entry is the same as an offset of the second database entry. | 01-30-2014 |
20140078902 | Scalable Low Latency Multi-Protocol Networking Device - A network device receives a packet that includes a plurality of sets of fields. Sets of fields of the packet are parsed and the field sets are evaluated as soon as they are available to determine whether a processing decision can be made on the packet. Additional field sets may be parsed from the packet and obtained in parallel with determining whether a processing decision can be made, but once it is determined that a processing decision can be made, the evaluating of field sets is terminated such that any further field sets of the packet are ignored for purposes of making a processing decision for the packet. | 03-20-2014 |
20140078903 | Real Time and High Resolution Buffer Occupancy Monitoring and Recording - Presented herein are techniques for detection and characterization of buffer occupancy of a buffer in a network device. Packets are received at a network device. The packets are stored in a buffer of the network device as they are processed by the network device. An occupancy level of the buffer is sampled at a sampling rate. Occupancy levels of the buffer over time are determined from the sampling, and traffic flow through the network device is characterized based on the occupancy levels. | 03-20-2014 |
20140078915 | Exporting Real Time Network Traffic Latency and Buffer Occupancy - Techniques are presented herein to facilitate the monitoring of occupancy of a buffer in a network device. Packets are received at a network device. Information is captured describing occupancy of the buffer caused by packet flow through the buffer in the network device. Analytics packets are generated containing the information. The analytics packets from the network device for retrieval of the information contained therein for analysis, replay of buffer occupancy, etc. | 03-20-2014 |
20140079062 | Ultra Low Latency Multi-Protocol Network Device - Presented herein are techniques to achieve ultra low latency determination of processing decisions for packets in a network device. A packet is received at a port of a network device. A processing decision is determined in a first processing decision path based on content of the packet and one or more network policies. A processing decision is determined in a second processing decision path, in parallel with the first processing path, by accessing a table storing processing decisions. The second processing decision path can output a processing decision faster than the first processing decision path for packets that match one or more particular packet flow parameters contained in the table. A processing decision determined by the second processing decision path, if one can be made, is used, and otherwise a processing decision determined by the first processing decision path is used. | 03-20-2014 |
20140079063 | Low Latency Networking Device Using Header Prediction - A network device receives a packet that includes a plurality of header fields. The packet is parsed to sequentially obtain the plurality of header fields. One or more header fields not yet available at the network device are predicted based on one or more header fields that are available at the network device. A network processing decision is generated for the packet based on the predicted one or more header fields and the one or more header fields that are available at the network device. | 03-20-2014 |
20140082118 | Ultra Low Latency Network Buffer Storage - Buffer designs and write/read configurations for a buffer in a network device are provided. According to one aspect, a first portion of the packet is written into a first cell of a plurality of cells of a buffer in the network device. Each of the cells has a size that is less than a minimum size of packets received by the network device. The first portion of the packet can be read from the first cell while concurrently writing a second portion of the packet to a second cell. | 03-20-2014 |
20150103669 | REAL TIME AND HIGH RESOLUTION BUFFER OCCUPANCY MONITORING AND RECORDING - Presented herein are techniques for detection and characterization of buffer occupancy of a buffer in a network device. Packets are received at a network device. The packets are stored in a buffer of the network device as they are processed by the network device. An occupancy level of the buffer is sampled at a sampling rate. Occupancy levels of the buffer over time are determined from the sampling, and traffic flow through the network device is characterized based on the occupancy levels. | 04-16-2015 |
20150188850 | Ultra Low Latency Network Buffer Storage - Buffer designs and write/read configurations for a buffer in a network device are provided. According to one aspect, a first portion of the packet is written into a first cell of a plurality of cells of a buffer in the network device. Each of the cells has a size that is less than a minimum size of packets received by the network device. The first portion of the packet can be read from the first cell while concurrently writing a second portion of the packet to a second cell. | 07-02-2015 |
20150229555 | Real Time And High Resolution Buffer Occupancy Monitoring And Recording - Presented herein are techniques for detection and characterization of buffer occupancy of a buffer in a network device. Packets are received at a network device. The packets are stored in a buffer of the network device as they are processed by the network device. An occupancy level of the buffer is sampled at a sampling rate. Occupancy levels of the buffer over time are determined from the sampling, and traffic flow through the network device is characterized based on the occupancy levels. | 08-13-2015 |
20150236933 | Timestamping Packets in a Network - Techniques are presented herein to facilitate latency measurements in a networking environment. A first network device receives a packet for transport within a network domain that comprises a plurality of network devices. The plurality of network devices have a common time reference, that is, they are time synchronized. The first network device generates timestamp information indicating time of arrival of the packet at the first network device. The first network device inserts into the packet a tag that comprises at least a first subfield and a second subfield. The first subfield comprising a type indicator to signify to other network devices in the network domain that the tag includes timestamp information, and the second subfield includes the timestamp information. The first network device sends the packet from to into the network domain to another network device. Other network devices which receive that packet can make latency measurements. | 08-20-2015 |
20150236982 | Scalable Low Latency Multi-Protocol Networking Device - A network device receives a packet that includes a plurality of sets of fields. Sets of fields of the packet are parsed and the field sets are evaluated as soon as they are available to determine whether a processing decision can be made on the packet. Additional field sets may be parsed from the packet and obtained in parallel with determining whether a processing decision can be made, but once it is determined that a processing decision can be made, the evaluating of field sets is terminated such that any further field sets of the packet are ignored for purposes of making a processing decision for the packet. | 08-20-2015 |
20150237177 | Low Latency Networking Device Using Header Prediction - A network device receives a packet that includes a plurality of header fields. The packet is parsed to sequentially obtain the plurality of header fields. One or more header fields not yet available at the network device are predicted based on one or more header fields that are available at the network device. A network processing decision is generated for the packet based on the predicted one or more header fields and the one or more header fields that are available at the network device. | 08-20-2015 |
20150244637 | Exporting Real Time Network Traffic Latency and Buffer Occupancy - Techniques are presented herein to facilitate the monitoring of occupancy of a buffer in a network device. Packets are received at a network device. Information is captured describing occupancy of the buffer caused by packet flow through the buffer in the network device. Analytics packets are generated containing the information. The analytics packets from the network device for retrieval of the information contained therein for analysis, replay of buffer occupancy, etc. | 08-27-2015 |
20150263922 | Measuring Latency within a Networking Device - Presented herein are techniques to measure latency associated with packets that are processed within a network device. A packet is received at a component of a network device comprising one or more components. A timestamp representing a time of arrival of the packet at a first point in the network device is associated with the packet. The timestamp is generated with respect to a clock of the network device. A latency value for the packet is computed based on at least one of the timestamp and current time of arrival at a second point in the network device. One or more latency statistics are updated based on the latency value. | 09-17-2015 |
20150334020 | Parallel Processing for Low Latency Network Address Translation - A packet is received at an ingress port of a networking device and a forwarding result that identifies an egress port for the packet is generated. In parallel with the generation of the forwarding result, a network address translation (NAT) result that identifies one or more NAT rules for possible application to the packet is generated. The forwarding result and the NAT result are then used to generate a routing decision result. | 11-19-2015 |
Patent application number | Description | Published |
20160049118 | GAMMA VOLTAGE GENERATING MODULE AND LIQUID CRYSTAL PANEL - A Gamma voltage generating module for supplying a liquid crystal panel having a plurality of pixel units, each including comprising a main pixel region M and a sub pixel region S. The Gamma voltage generating modules have a reference voltage unit source to a first divider resistance string for dividing the reference voltages to form Gamma voltages corresponding to 0-255 gray scales, and supplying the Gamma voltages to the main pixel region M; and a second divider resistance string, coupled to the reference voltage unit, for forming Gamma voltages corresponding to 0-255 gray scales, and supplying the Gamma voltages to the sub pixel region S. The first divider resistance string and the second divider resistance string, the Gamma voltage generating points at least at gray scales of 0, Gx, Gx+1 and 255 connect with the reference voltages. Also discloses a liquid crystal panel comprising the above Gamma voltage generating module. | 02-18-2016 |
20160124264 | COMPENSATION STRUCTURE FOR LIQUID CRYSTAL PANELS AND THE LIQUID CRYSTAL DISPLAYS - A compensation structure of liquid crystal panels is disclosed. The compensation structure includes a liquid crystal panel and a first polarizing film and a second polarizing film arranged on two opposite surfaces of the liquid crystal panel. The liquid crystal panel comprises a liquid crystal layer having a plurality of liquid crystal molecules. An anisotropy reflective index of the liquid crystal layer is Δn, the thickness of the liquid crystal layer is d, and a pretilt angle of the liquid crystal molecules is θ. The first compensation film is a biaxial compensation film, and an in-plane retardation value and a thickness retardation value of the first compensation film are respectively Ro1 and Rth1. The second compensation film is the single-axial compensation film, and the thickness retardation value of the second compensation film is Rth2, wherein: 324.3 nm≦Δn×d≦342.7 nm; 85°≦θ<90°; 55 nm≦Ro1≦78 nm; 208 nm≦Rth1≦293 nm; Y1 nm≦Rth2≦Y2 nm; Y1=0.001897×(Rth1) | 05-05-2016 |
Patent application number | Description | Published |
20130135784 | Electrostatic Chuck Robotic System - A workpiece transfer system has a plurality of joints having a bearing and a primary and secondary transformer coil, wherein power provided to the primary transformer coil and secondary transformer coil of each joint produces mutual inductance between the primary and secondary transformer coil of the respective joint. A first pair of arms are rotatably coupled to a blade by a first pair of the joints, wherein the primary transformer coil of each of the first pair of joints is operably coupled to the first pair of arms, and the secondary transformer coil of each of the first pair of joints is operably coupled to the blade and an electrode beneath a dielectric workpiece retaining surface of the blade. The electrode is contactlessly energized through the transformer coils of the joint and the blade can chuck and de-chuck a workpiece by reversing current directions and by voltage adjustment. | 05-30-2013 |
20130136873 | APPARATUS AND METHOD WITH DEPOSITION CHAMBER HAVING MULTIPLE TARGETS AND MAGNETS - A thin film deposition system and method provide for multiple target assemblies that may be separately powered. Each target assembly includes a target and associated magnet or set of magnets. The disclosure provides a tunable film profile produced by multiple power sources that separately power the target arrangements. The relative amounts of power supplied to the target arrangements may be customized to provide a desired film and may be varied in time to produce a film with varied characteristics. | 05-30-2013 |
20130147046 | Integrated Technology for Partial Air Gap Low K Deposition - A semiconductor device includes a semiconductor body and a low K dielectric layer overlying the semiconductor body. A first portion of the low K dielectric layer comprises a dielectric material, and a second portion of the low K dielectric layer comprise an air gap, wherein the first portion and the second portion are laterally disposed with respect to one another. A method for forming a low K dielectric layer is also disclosed and includes forming a dielectric layer over a semiconductor body, forming a plurality of air gaps laterally disposed from one another in the dielectric layer, and forming a capping layer over the dielectric layer and air gaps. | 06-13-2013 |
20130149871 | CHEMICAL VAPOR DEPOSITION FILM PROFILE UNIFORMITY CONTROL - The present disclosure provides for methods and systems for controlling profile uniformity of a chemical vapor deposition (CVD) film. A method includes depositing a first layer on a substrate by CVD with a first shower head, the first layer having a first profile, and depositing a second layer over the first layer by CVD with a second shower head, the second layer having a second profile. The combined first layer and second layer have a third profile, and the first profile, the second profile, and the third profile are different from one another. | 06-13-2013 |
20130189851 | CVD Conformal Vacuum/Pumping Guiding Design - The present disclosure relates to a guiding element for guiding gas flow within a chamber. The guiding element includes a structure, one or more inlets, an outlet, and a transportation region. The one or more inlets are formed on a first side of the structure. The inlets have inlet sizes selected according to a removal rate and to mitigate gas flow variations within the chamber. The outlet is on a second side of the structure, opposite the first side of the structure. The outlet has an outlet size selected according to the removal rate. The transportation region is within the structure and couples or connects the inlets to the outlet. | 07-25-2013 |
20130201596 | Electrostatic Chuck with Multi-Zone Control - An electrostatic chuck for clamping a warped workpiece has a clamping surface comprising a dielectric layer. The dielectric layer has a field and one or more zones formed of differing dielectric materials. One or more electrodes are coupled to a power supply, and a controller controls a clamping voltage supplied to the one or more electrodes via the power supply. An electrostatic attraction force associated with each of the field and one or more zones of the dielectric layer of the electrostatic chuck is induced, wherein the electrostatic attraction force varies based on the dielectric material of each of the field and one or more zones. The electrostatic attraction force is greater in the one or more zones than in the field, therein attracting warped regions of the workpiece to the clamping surface and clamping the warped workpiece to the clamping surface across a surface of the warped workpiece. | 08-08-2013 |
20130239889 | VALVE PURGE ASSEMBLY FOR SEMICONDUCTOR MANUFACTURING TOOLS - A semiconductor manufacturing tool and method for operating the tool are provided. The semiconductor manufacturing tool includes a process chamber in which plasma operations or ion etching operations are carried out and a valve assembly for opening and closing a valve that provides for loading and unloading substrates into and out of, the semiconductor manufacturing tool. While a processing operation is being carried out in the chamber, a valve assembly purge operation also takes place. The valve assembly purge operation involves inert gases being directed to the valve assembly area to prevent the buildup of particles and contaminating films in the valve assembly. Because the valve assembly is maintained in a clean condition, particle contamination is reduced or eliminated. | 09-19-2013 |
20130267045 | SHOWER HEAD APPARATUS AND METHOD FOR CONTROLLIGN PLASMA OR GAS DISTRIBUTION - An apparatus comprises: a shower head having a supply plenum for supplying the gas to the chamber and a vacuum manifold fluidly coupled to the supply plenum; and at least one vacuum system fluidly coupled to the vacuum manifold of the shower head. | 10-10-2013 |
20130295297 | SEMICONDUCTOR FILM FORMATION APPARATUS AND PROCESS - An apparatus and method are disclosed for forming thin films on a semiconductor substrate. The apparatus in one embodiment includes a process chamber configured for supporting the substrate, a gas excitation power source, and first and second gas distribution showerheads fluidly coupled to a reactive process gas supply containing film precursors. The showerheads dispense the gas into two different zones above the substrate, which is excited to generate an inner plasma field and an outer plasma field over the wafer. The apparatus deposits a material on the substrate in a manner that promotes the formation of a film having a substantially uniform thickness across the substrate. In one embodiment, the substrate is a wafer. Various embodiments include first and second independently controllable power sources connected to the first and second showerheads to vary the power level and plasma intensity in each zone. | 11-07-2013 |
20140030866 | METHOD AND APPARATUS FOR PREPARING POLYSILAZANE ON A SEMICONDUCTOR WAFER - A method for depositing a polysilazane on a semiconductor wafer is provided. The method includes steps of disposing a silazane onto the semiconductor wafer, and heating the silazane to form the polysilazane on the semiconductor wafer. An apparatus for preparing a polysilazane on a semiconductor wafer is also provided. | 01-30-2014 |
20140162534 | POLISHING SYSTEM AND POLISHING METHOD - A polishing system for polishing a semiconductor wafer includes a wafer support for holding the semiconductor wafer, and a first polishing pad for polishing a region of the semiconductor wafer. The semiconductor wafer has a first diameter, and the first polishing pad has a second diameter shorter than the first diameter. | 06-12-2014 |
20150016011 | Electrostatic Check with Multi-Zone Control - An electrostatic chuck for clamping a warped workpiece has a clamping surface comprising a dielectric layer. The dielectric layer has a field and one or more zones formed of differing dielectric materials. One or more electrodes are coupled to a power supply, and a controller controls a clamping voltage supplied to the one or more electrodes via the power supply. An electrostatic attraction force associated with each of the field and one or more zones of the dielectric layer of the electrostatic chuck is induced, wherein the electrostatic attraction force varies based on the dielectric material of each of the field and one or more zones. The electrostatic attraction force is greater in the one or more zones than in the field, therein attracting warped regions of the workpiece to the clamping surface and clamping the warped workpiece to the clamping surface across a surface of the warped workpiece. | 01-15-2015 |
20150132913 | MECHANISMS FOR FORMING SEMICONDUCTOR DEVICE HAVING STABLE DISLOCATION PROFILE - Embodiments that relate to mechanisms for providing a stable dislocation profile are provided. A semiconductor substrate having a gate stack is provided. An opening is formed adjacent to a side of the gate stack. A first part of an epitaxial growth structure is formed in the opening. A second part of the epitaxial growth structure is formed in the opening. The first part and the second part of the epitaxial growth structure are formed along different directions. | 05-14-2015 |
20150279632 | DEVICE AND METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE - A device includes a pedestal. The pedestal includes a ground electrode, a central portion, and a peripheral portion. The ground electrode includes a top surface from which the peripheral portion is projected, thereby having a height difference between the central portion and the peripheral portion. | 10-01-2015 |
Patent application number | Description | Published |
20140054653 | TWO-STEP SHALLOW TRENCH ISOLATION (STI) PROCESS - An integrated circuit device and a process for making the integrated circuit device. The integrated circuit device including a substrate having a trench formed therein, a first layer of isolation material occupying the trench, a second layer of isolation material formed over the first layer of isolation material, an epitaxially-grown silicon layer on the substrate and horizontally adjacent the second layer of isolation material, and a gate structure formed on the epitaxially-grown silicon, the gate structure defining a channel. | 02-27-2014 |
20140179071 | TWO-STEP SHALLOW TRENCH ISOLATION (STI) PROCESS - Methods of making an integrated circuit are disclosed. An embodiment method includes etching a trench in a silicon substrate, depositing a first layer of isolation material in the trench, the first layer of isolation material projecting above surface of the silicon substrate, capping the first layer of isolation material by depositing a second layer of isolation material, the second layer of isolation material extending along at least a portion of sidewalls of the first layer of isolation material, epitaxially-growing a silicon layer upon the silicon substrate, the silicon layer horizontally adjacent to the second layer of isolation material, and forming a gate structure on the silicon layer, the gate structure defining a channel. | 06-26-2014 |
20150179502 | Two-Step Shallow Trench Isolation (STI) Process - Methods of making an integrated circuit are disclosed. An embodiment method includes etching a trench in a silicon substrate, depositing a first layer of isolation material in the trench, the first layer of isolation material projecting above surface of the silicon substrate, capping the first layer of isolation material by depositing a second layer of isolation material, the second layer of isolation material extending along at least a portion of sidewalls of the first layer of isolation material, epitaxially-growing a silicon layer upon the silicon substrate, the silicon layer horizontally adjacent to the second layer of isolation material, and forming a gate structure on the silicon layer, the gate structure defining a channel. | 06-25-2015 |