Patent application number | Description | Published |
20100118617 | MEMORIES WITH IMPROVED WRITE CURRENT - A memory with improved write current is provided, including a bit line, a write switch and a control circuit. The write switch is coupled between a voltage source and the bit line, and has a control terminal. Based on a bit line select signal, the control circuit controls the electric conductance of the write switch and discharges/charges the parasitic capacitors of the write switch. The voltage source is turned on after the control terminal of the write switch reaches a pre-determined voltage level. | 05-13-2010 |
20100153043 | MONITORING METHOD FOR THROUGH-SILICON VIAS OF THREE-DIMENSIONAL INTERGRATED CIRCUIT (3D IC) AND APPARATUS USING THE SAME - A monitoring method for Through-Silicon Vias (TSVs) of a three-dimensional integrated circuit (3D IC) is provided, wherein the 3D IC includes a plurality of TSVs, and the method includes: providing a plurality of inverters; connecting the inverters with the TSVs as a circuit; enabling the circuit to oscillate; measuring an output signal on an output end of one of the inverters; and determining the characteristic of TSVs of the 3D IC based on the output signal. | 06-17-2010 |
20100176413 | LIGHT-EMITTING DIODE DEVICE INCLUDING A MULTI-FUNCTIONAL LAYER - A light-emitting diode device includes: a substrate; a light-emitting layered structure formed on the substrate; a multi-functional layer having a first main portion and formed on the light-emitting layered structure for spreading current laterally and for reflecting light emitted from the light-emitting layered structure; and first and second electrodes electrically coupled to the light-emitting layered structure. The first electrode is formed on the light-emitting layered structure and has a first electrode main part. The first main portion of the multi-functional layer is aligned below and is provided with a size larger than that of the first electrode main part. | 07-15-2010 |
20100178616 | METHOD OF MAKING A ROUGH SUBSTRATE - A method of making a rough substrate includes: (a) forming a first oxide layer; (b) coating a photoresist layer; (c) exposing and developing the photoresist layer; (d) etching parts of the first oxide layer such that parts of the first oxide layer are formed into a plurality of sacrificial protrusions; (e) removing the photoresist regions; (f) depositing on the substrate layer and the sacrificial protrusions a second oxide layer; (g) etching the second oxide layer so as to leave portions of the second oxide layer; and (h) etching additionally the sacrificial protrusions, the substrate layer, and the portions of the second oxide layer, thereby producing a plurality of flat recess bottom faces, and substrate protrusions. | 07-15-2010 |
20100237386 | ELECTROSTATIC DISCHARGE STRUCTURE FOR 3-DIMENSIONAL INTEGRATED CIRCUIT THROUGH-SILICON VIA DEVICE - An electrostatic discharge (ESD) structure for a 3-dimensional (3D) integrated circuit (IC) through-silicon via (TSV) device is provided. The ESD structure includes a substrate, a TSV device which is formed through the substrate and is equivalent to a resistance-inductance-capacitance (RLC) device, and at least one ESD device which is disposed in the substrate and electrically connected to one end of the TSV device. The ESD structure can protect the 3D IC TSV device. | 09-23-2010 |
20100320478 | LIGHT-EMITTING DIODE DEVICE INCLUDING A CURRENT BLOCKING REGION AND METHOD OF MAKING THE SAME - A light-emitting diode device includes: a substrate; a light-emitting layered structure disposed on the substrate and including a first cladding layer, an active layer, and a second cladding layer; a first electrode; a second electrode disposed on the light-emitting layered structure; and a current blocking region provided in the light-emitting layered structure below the second electrode, and having a main portion that is aligned below and is as large as the second electrode, and an extension portion extending from the main portion and protruding beyond the second electrode to a distance ranging from 3 μm to 20 μm. | 12-23-2010 |
20100320498 | LIGHT-EMITTING DIODE DEVICE - A light-emitting diode device includes: a substrate; and a semiconductor layered structure including an n-type semiconductor layer that has an exposed region, and a p-type semiconductor layer that is disposed over the n-type semiconductor layer without extending over the exposed region. An electrode unit is electrically coupled to the semiconductor layered structure, and includes a first electrode and a second electrode. The second electrode has an electrode pad, an end node, and a connecting strip. The electrode pad is larger than the end node. The connecting strip is narrower than the end node. | 12-23-2010 |
20110278600 | LIGHT EMITTING DIODE MODULE AND METHOD OF MAKING THE SAME - A light emitting diode module includes a substrate, at least two spaced apart light emitting diodes formed on the substrate, an insulating layer, and an electrically conductive layer. Each of the light emitting diodes includes a light emitting unit, an n-electrode, and a p-electrode. The light emitting unit has first and second portions. The first portion has an n-type top face and a first stepped side. The second portion has a p-type top face and a second stepped side. The insulating layer is formed on the n-type top face and the first stepped side of the first portion of one of the light emitting diodes, and the second stepped side and the p-type top face of the second portion of the other one of the light emitting diodes. The electrically conductive layer is formed on the insulating layer. A method of making the light emitting diode module is also disclosed. | 11-17-2011 |
20120018723 | STRUCTURE AND METHOD FOR TESTING THROUGH-SILICON VIA (TSV) - A test structure including at least one ground pad, an input pad, at least one first through-silicon via (TSV), at least one second TSV and an output pad is disclosed. The ground pad receives a ground signal during a test mode. The input pad receives a test signal during the test mode. The first TSV is coupled to the input pad. The output pad is coupled to the second TSV. No connection line occurs between the first and the second TSVs. During the test mode, a test result is obtained according to the signal of at least one of the first and the second TSVs, and structural characteristics can be obtained according to the test result. | 01-26-2012 |
20120139092 | MULTI-CHIP STACK STRUCTURE - A multi-chip stack structure including a first chip, a second chip, a shielding layer, and a plurality of conductive bumps is provided. The second chip is stacked on the first chip. The second chip has a plurality of through silicon via (TSV) structures to conduct a reference voltage. The shielding layer and the plurality of conductive bumps are disposed between the first chip and the second chip, and are electrically connected to the plurality of TSV structures. The shielding layer can isolate noises and improve signal coupling between two adjacent chips. | 06-07-2012 |
20120249178 | MONITORING METHOD FOR THREE-DIMENSIONAL INTERGRATED CIRCUIT (3D IC) AND APPARATUS USING THE SAME - A monitoring method of a three-dimensional integrated circuit (3D IC) is provided, wherein the method includes: providing a plurality of TSVs, providing a plurality of inverters; connecting the inverters with the plurality of TSVs as a circuit loop; enabling the circuit loop to oscillate; measuring an output signal on an output end of one of the plurality of inverters; and determining the manufacturing state of the plurality of TSVs of the 3D IC based on the output signal and apparatus using the same. | 10-04-2012 |
Patent application number | Description | Published |
20120068177 | MEASURING APPARATUS - A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface. The first heater comprises a plurality of first switches connected in series to generate heat. | 03-22-2012 |
20130093454 | TESTING AND REPAIRING APPARATUS OF THROUGH SILICON VIA IN STACKED-CHIP - A testing and repairing apparatus of through silicon via (TSV) disposed between a first and a second chips is provided. First terminals of a first and a second switches are coupled to a first terminal of the TSV. First terminals of a third and a fourth switches are coupled to a second terminal of the TSV. A first terminal of a first resister is coupled to a first voltage. A first selector is coupled between second terminals of the second switch and the first resister. A second selector is coupled between a second terminal of the fourth switch and a second voltage. A first control circuit detects the second terminal of the second switch, and controls the first switch, the second switch and the first selector. A second control circuit controls the third switch, the fourth switch and the second selector. | 04-18-2013 |
20140175606 | VARACTOR - A varactor is provided. A substrate includes a first surface, a second surface and a first opening and a second opening in the substrate. A conductive material is filling the first and second openings, to form a first through-wafer via (TWV) and a second through-wafer via. A first capacitor is coupled between the first through-wafer via and a first terminal. A second capacitor is coupled between the second through-wafer via and a second terminal. A capacitance of a depletion-region capacitor between the first through-wafer via and the second through-wafer via is determined by a bias voltage applied to the first through-wafer via and the second through-wafer via. | 06-26-2014 |
20140184346 | Voltage-Controlled Oscillator Circuit Structure - A voltage-controlled oscillator (VCO) is provided. The VCO includes an oscillator unit disposed on a substrate, and a varactor unit. The varactor unit is coupled to the oscillator unit to form a VCO loop. The varactor unit includes a varactor and at least one control terminal. The varactor is disposed in the substrate, and includes at least two through-silicon via (TSV) structures. The at least one control terminal renders the varactor unit to be biased to change a capacitance value of the varactor. | 07-03-2014 |
20140340113 | THROUGH SILICON VIA REPAIR CIRCUIT OF SEMICONDUCTOR DEVICE - TSV repair circuit of a semiconductor device includes a first chip, a second chip, at least two TSV, at least two data path circuits and an output logic circuit. Each data path circuit comprises an input driving circuit, a TSV detection circuit, a memory device, a protection circuit and a power control circuit. The TSV detection circuit detects a TSV status, the memory device keeps the TSV status, the protection circuit determines whether to pull a first end of the TSV to a ground voltage according to the TSV status, and the power control circuit prevents a leakage current of a power voltage from flowing through a substrate. | 11-20-2014 |