| Patent application number | Description | Published |
|---|
| 20090008135 | CIRCUIT SUBSTRATE - A surface treatment process for a substrate is provided. There are a plurality of first conductive patterns on a top surface of the substrate and a plurality of second conductive patterns on a bottom surface of the substrate and a plurality of inner circuits electrically connected with the first conductive patterns and the second conductive patterns. The process includes the following steps. First, a conductive layer is formed on the second conductive patterns. Next, an insulating layer is formed on the conductive layer. After the insulating layer is formed, an anti-oxidizing layer is electroplated on the first conductive patterns using the conductive layer. Next, the insulating layer and the conductive layer are removed in sequence. The surface treatment process of the present invention has the advantage of low fabrication cost and does not need a plating bar to perform the electroplating process or a photolithographic process. | 01-08-2009 |
| 20090288858 | CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF - A manufacturing method of a circuit structure is provided as follows. Firstly, a base conductive layer is formed on the carrier board and a first patterned plating-resistant layer having at least one trench for exposing a part of the base conductive layer is formed on the base conductive layer. A first patterned conductive layer is then formed in the trench and a second patterned plating-resistant layer is formed which covers a part of the first patterned conductive layer and a part of the first patterned plating-resistant layer. A second patterned conductive layer is formed on the exposed first patterned conductive layer. The first and the second patterned plating-resistant layers and the base conductive layer exposed by the first patterned conductive layer are removed. Then, a patterned solder mask is formed for covering a part of the first patterned conductive layer. | 11-26-2009 |
| 20100013068 | CHIP PACKAGE CARRIER AND FABRICATION METHOD THEREOF - A chip package carrier is disclosed, which includes a first circuit layer, a second circuit layer, a core layer, a third circuit layer, a first dielectric layer between the first and third circuit layers, a fourth conductive layer including at least a solder ball pad, a second dielectric layer between the second and fourth circuit layers and at least a capacitor device, wherein the core layer has at least a first through-hole; the third circuit layer is disposed above the first circuit layer and includes at least a die pad; the capacitor device is disposed in the first through-hole. The capacitor device herein includes a first pillar electrode covering the wall of the first through-hole, a cylindrical capacitor material disposed in the first pillar electrode and having a first blind hole, and a second pillar electrode disposed in the first blind hole and connected to the die pad. | 01-21-2010 |
| 20100215927 | COMPOSITE CIRCUIT SUBSTRATE STRUCTURE - A composite circuit substrate structure includes a first dielectric layer, a second dielectric layer, a glass fiber structure, and a patterned circuit. The first dielectric layer has a first surface and a second surface opposite to each other. The second dielectric layer is disposed on the first dielectric layer and entirely connected to the first surface. The glass fiber structure is distributed in the second dielectric layer. The patterned circuit is embedded in the first dielectric layer from the second surface, and the patterned circuit is not contacted with the glass fiber structure. | 08-26-2010 |
| 20100294553 | PACKAGE SUBSTRATE HAVING EMBEDDED CAPACITOR - A package substrate having embedded capacitor is provided. The package substrate includes a core circuit board, at least one embedded capacitor, at least one dielectric layer and at least one wiring layer. The core circuit board has at least one metal layer, and the core circuit board has at least one conductive through hole connected to the metal layer. At least one embedded capacitor is embedded in the core circuit board and connected to the metal layer. At least one dielectric layer covers the core circuit board, and the dielectric layer has an embedded hole. At least one wiring layer covers the dielectric layer and connected to the embedded hole. | 11-25-2010 |
| 20100319970 | PACKAGE SUBSTRATE HAVING EMBEDDED CAPACITOR - A package substrate having embedded capacitor is provided. The package substrate includes a core circuit board, at least one dielectric layer, at least one embedded capacitor, and at least one metal layer. The core circuit board has at least one wiring layer, and the core circuit board has at least one conductive through hole connected to the wiring layer. At least one dielectric layer covers the wiring layer, and the dielectric layer has at least one conductive through hole. At least one embedded capacitor is embedded in the dielectric layer. At least one metal layer covers the dielectric layer and connected to the embedded capacitor, wherein the metal layer is connected to the wiring layer through the conductive through hole. | 12-23-2010 |
| 20100319973 | PACKAGE SUBSTRATE HAVING EMBEDDED CAPACITOR - A package substrate having embedded capacitor is provided. The package substrate includes a first core circuit board, at least one embedded capacitor, a second core circuit board and a dielectric layer. The first core circuit board has at least one metal layer, and the first core circuit board has at least one first conductive through hole connected to the metal layer. At least one embedded capacitor is embedded in the first core circuit board and connected to the metal layer. The second core circuit board has at least one wiring layer, and the second core circuit board has at least one second conductive through hole connected to the wiring layer. The dielectric layer is laminated between the first core circuit board and the second core circuit board. | 12-23-2010 |
