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| 20080272378 | METHOD FOR FORMING A NITRIDE SEMICONDUCTOR LAYER AND METHOD FOR SEPARATING THE NITRIDE SEMICONDUCTOR LAYER FROM THE SUBSTRATE - There is provided a method of forming a nitride semiconductor layer, including the steps of firstly providing a substrate on which a patterned epitaxy layer with a pier structure is formed. A protective layer is then formed on the patterned epitaxy layer, exposing a top surface of the pier structure. Next, a nitride semiconductor layer is formed over the patterned epitaxy layer connected to the nitride semiconductor layer through the pier structure, wherein the nitride semiconductor layer, the pier structure, and the patterned epitaxy layer together form a space exposing a bottom surface of the nitride semiconductor layer. Thereafter, a weakening process is performed to remove a portion of the bottom surface of the nitride semiconductor layer and to weaken a connection point between the top surface of the pier structure and the nitride semiconductor layer. Finally, the substrate is separated from the nitride semiconductor layer through the connection point. | 11-06-2008 |
| 20080305571 | METHOD OF FABRICATING SEMICONDUCTOR LIGHT EMITTING DEVICE SUBSTRATE - A method of fabricating a substrate for semiconductor light emitting devices is provided. The method includes forming a nanocrystal structure on a surface of the substrate which is a single crystal material, wherein the nanocrystal structure has an etched region and an unetched region. Next, a nitride semiconductor material is grown on the surface of the single crystal material with an epitaxial process, so as to form a substrate. Due to the periodicity of the nanocrystal structure, the semiconductor material grown on the substrate has fewer defects, and the material stress is reduced. Besides, the nanocrystal structure is capable of diffracting an electromagnetic wave, such that a higher light emitting efficiency and a higher output power may be obtained accordingly. | 12-11-2008 |
| 20090135593 | ASSEMBLY OF LIGHTING PANEL MODULES AND MANUFACTURING METHOD THEREOF - An assembly of lighting panel modules comprises a plurality of lighting panel modules and adhesive compound between the plurality of lighting panel modules. Each of the lighting panel modules comprises a light guide plate and at least one light emitting component. The light emitted from the light emitting component enters the light guide plate and exits from the surface of the light guide plate. The adhesive compound combines the light guide plates of the lighting panel modules. The adhesive compound can transmit the light within the light guide plates. | 05-28-2009 |
| 20100013054 | COMPOSITE MATERIAL SUBSTRATE - A composite material substrate having patterned structure includes a substrate, a first dielectric layer, a second dielectric layer, and a nitride semiconductor material. Herein, the first dielectric layer is stacked on the substrate, the second dielectric layer is stacked on the first dielectric layer, and the nitride semiconductor material is stacked on the second dielectric layer and is characterized by a plurality of patterns thereon. | 01-21-2010 |
| 20100041216 | METHOD OF MANUFACTURING NITRIDE SEMICONDUCTOR SUBSTRATE - The present invention relates to a method of forming a nitride semiconductor substrate. This method includes steps of providing a substrate and then forming an epitaxy layer on the substrate. A patterned mask layer is formed on the epitaxy layer, wherein the patterned mask layer exposes a portion of the epitaxy layer. Next, an oxidation process is performed to oxidize the exposed epitaxy layer so as to form a plurality of dislocation blocking structures. The patterned mask layer is then removed. Further, a nitride semiconductor layer is formed on the epitaxy layer having the dislocation blocking structures. | 02-18-2010 |
| 20100181577 | NITRIDE SEMICONDUCTOR SUBSTRATE - There is provided a nitride semiconductor substrate. The nitride semiconductor substrate comprises a substrate, a patterned epitaxy layer, a protective layer and a gallium nitride semiconductor layer. The patterned epitaxy layer is disposed on the substrate, wherein the patterned epitaxy layer comprises a pier structure and the patterned epitaxy layer has an upper surface and a lower surface opposite to the upper surface and the lower surface faces to the substrate. The protective layer covers a portion of the upper surface of the patterned epitaxy layer to expose a top surface of the pier structure. The gallium nitride (GaN) semiconductor layer extends substantially across an entire area above the patterned epitaxy layer and connected to the exposed top surface of the pier structure. | 07-22-2010 |
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| 20090068773 | METHOD FOR FABRICATING PIXEL STRUCTURE OF ACTIVE MATRIX ORGANIC LIGHT-EMITTING DIODE - A method for fabricating an AMOLED pixel includes forming a transparent semiconductor layer on a substrate and forming a first channel layer of the switch TFT, a lower electrode of a storage capacitor and a second channel layer of a driving TFT. A first dielectric layer is formed over the substrate. A first opaque metal gate of the switch TFT, a second opaque metal gate of the driving TFT and a scan line are formed on the first dielectric layer. A first source and a first drain of the switch TFT are formed in the first channel layer and a second source and a second drain of the switch TFT are formed in the second channel layer. A patterned transparent metal layer is formed on the first dielectric layer. A data line is formed over the substrate. An OLED is formed over the substrate. | 03-12-2009 |
| 20100127254 | PHOTO SENSING ELEMENT ARRAY SUBSTRAT - A photo sensing element array substrate is provided. The photo sensing element array substrate includes a flexible substrate and a plurality of photo sensing elements. The photo sensing elements are disposed in array on the flexible substrate. Each of the photo sensing elements includes a photo sensing thin film transistor (TFT), an oxide semiconductor TFT and a capacitor. The photo sensing TFT is disposed on the flexible substrate. The oxide semiconductor TFT is disposed on the flexible substrate. The oxide semiconductor TFT is electrically connected to the photo sensing TFT. The capacitor is disposed on the flexible substrate and electrically connected between the photo sensing TFT and the oxide semiconductor TFT. When the photo sensing element array substrate is bent, it remains unaffected from normal operation. | 05-27-2010 |
| 20100148168 | INTEGRATED CIRCUIT STRUCTURE - An integrated circuit structure including a substrate, an insulating layer, a first transistor and a second transistor is provided. The insulating layer, the first transistor and the second transistor are disposed on the substrate. The first transistor includes a first gate, a first oxide semiconductor layer, a first source and a first drain. A portion of the first source and the first drain directly contacting the first oxide semiconductor layer is composed of a Ti-containing metal. The second transistor includes a second gate, a second oxide semiconductor layer, a second source and a second drain. A portion of the second source and the second drain directly contacting the second oxide semiconductor layer is composed of a none-Ti-containing metal. In addition, the first oxide semiconductor layer and the second oxide semiconductor layer may have different thickness or different carrier concentrations. | 06-17-2010 |
| 20120164766 | METHOD OF FABRICATING AN ACTIVE DEVICE ARRAY AND FABRICATING AN ORGANIC LIGHT EMITTING DIODE ARRAY - Methods of fabricating active device array and organic light emitting diode array are provided. A first pattern metal layer is formed over a substrate. An oxide semiconductor layer is formed entirely over the substrate. A first insulation layer covering the first patterned metal layer and the oxide semiconductor layer is formed entirely on the substrate. A second patterned metal layer is formed on the first insulation layer. The oxide semiconductor layer and the first insulation layer is patterned by using the second patterned metal layer as a mask to form a first patterned oxide semiconductor layer and a first patterned insulation layer. A second insulation layer is entirely formed on the substrate. A second patterned oxide semiconductor layer is formed over the second insulation layer. A third patterned metal layer is formed over the second insulation layer. | 06-28-2012 |
| 20120171792 | METHOD OF FABRICATING A PIXEL ARRAY - A method of fabricating a pixel array is provided. A first metal layer is formed over a substrate. The metal layer is patterned to form a plurality of data lines and a plurality of drain patterns adjacent to each data line. The data lines and the drain patterns are separated from each other. An oxide semiconductor layer and a first insulation layer covering the oxide semiconductor layer are formed over the substrate. A second metal layer is formed on the first insulation layer and patterned to form a plurality of scan lines intersected with the data lines and the drain patterns. By using the scan lines as a mask, the oxide semiconductor layer and the first insulation layer are patterned to form a plurality of oxide semiconductor channels located under each scan line. Each oxide semiconductor channel is located between one data line and one drain pattern. | 07-05-2012 |
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| 20100103626 | CIRCUIT BOARD MODULE AND CONNECTION PORT THEREOF - A connection port and a circuit board module employing such a connection port are provided. The circuit board module includes a circuit board, a plurality of electronic components, a switch, a control unit connected to the switch, and a connection port. The electronic components, the switch, the control unit and the connection port are disposed on the circuit board. The connection port is adapted for connecting with a connector. The connection port includes a body, a plurality of first connection terminals for connecting with the connector, and a detection terminal. Each of the first connection terminals has one end connected to the control unit via the switch. The detection terminal has one end connected with the switch of the circuit board module. When another end of the detection terminal gets in contact with the connector, the switch electrically conducts the first connection terminals with the control unit. | 04-29-2010 |
| 20100105228 | Circuit board module and connector protecting cover thereof - A connector protecting cover and a circuit board module using the same are provided. The circuit board module includes a circuit board, a plurality of electronic devices, a connector, and a connector protecting cover. The electronic devices are disposed on the circuit board. The connector is disposed on the circuit board and includes a plurality of connecting terminals connected to the circuit board. The connector protecting cover includes a top wall, a circular side wall connected to the top wall, and a partition. The partition is connected to the circular side wall. The top wall, the circular side wall, and the partition define a plurality of accommodation spaces. The partition and the circular side wall are together used for clipping the connecting terminals, such that the connecting terminals are located in the accommodation spaces. | 04-29-2010 |
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| 20090222785 | METHOD FOR SHAPE AND TIMING EQUIVALENT DIMENSION EXTRACTION - An integrated circuit (IC) design method includes providing an IC layout contour based on an IC design layout of an IC device and IC manufacturing data; generating an effective rectangle layout to represent the IC layout contour; and simulating the IC device using the effective rectangular layout. | 09-03-2009 |
| 20100095253 | TABLE-BASED DFM FOR ACCURATE POST-LAYOUT ANALYSIS - Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data. | 04-15-2010 |
| 20110124193 | CUSTOMIZED PATTERNING MODULATION AND OPTIMIZATION - The present disclosure provides one embodiment of an integrated circuit (IC) design method. The method includes providing an IC design layout of a circuit; applying an electrical patterning (ePatterning) modification to the IC design layout according to an electrical parameter of the circuit and an optical parameter of IC design layout; and thereafter fabricating a mask according to the IC design layout. | 05-26-2011 |
| 20110230998 | MODEL IMPORT FOR ELECTRONIC DESIGN AUTOMATION - Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility. | 09-22-2011 |
| 20110231804 | MODEL IMPORT FOR ELECTRONIC DESIGN AUTOMATION - Methods and systems for providing processing parameters in a secure format are disclosed. In one aspect, a method for providing semiconductor fabrication processing parameters to a design facility is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a model from the set of processing parameters; converting the model into a corresponding set of kernels; converting the set of kernels into a corresponding set of matrices; and communicating the set of matrices to the design facility. In another aspect, a method for providing semiconductor fabrication processing parameters is disclosed. The method comprises providing a set of processing parameters of a fabrication facility; creating a processing model from the set of processing parameters; encrypting the processing model into a format for use with a plurality of EDA tools; and communicating the encrypted processing model format to a design facility. | 09-22-2011 |
| 20110243424 | METHOD AND APPARATUS FOR MONITORING MASK PROCESS IMPACT ON LITHOGRAPHY PERFORMANCE - The present disclosure is directed generally to a method and apparatus for monitoring mask process impact on lithography performance. A method including receiving a physical wafer pattern according to a mask, extracting a mask contour from the mask, and extracting a deconvolution pattern based on the mask contour. A lithography process is simulated to create a virtual wafer pattern based on the deconvolution pattern. The virtual wafer pattern is then compared to the physical wafer pattern. | 10-06-2011 |
| 20110289466 | Table-Based DFM for Accurate Post-Layout Analysis - Disclosed is a system and method for integrated circuit designs and post layout analysis. The integrated circuit design method includes providing a plurality of IC devices with various design dimensions; collecting electrical performance data of the IC devices; extracting equivalent dimensions of the IC devices; generating a shape related model to relate the equivalent dimensions to the electrical performance data of the IC devices; and creating a data refinement table using the equivalent dimensions and the electrical performance data. | 11-24-2011 |
