| Patent application number | Description | Published |
|---|
| 20080224225 | MOS transistors with selectively strained channels - The channels of first and second CMOS transistors can be selectively stressed. A gate structure of the first transistor includes a stressor that produces stress in the channel of the first transistor. A gate structure of the second transistor is disposed in contact with a layer of material that produces stress in the channel of the second transistor. | 09-18-2008 |
| 20080224227 | BiCMOS performance enhancement by mechanical uniaxial strain and methods of manufacture - A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT. | 09-18-2008 |
| 20080277735 | MOS devices having elevated source/drain regions - A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a deep source/drain region adjacent the gate electrode; a silicide region over the deep source/drain region; and an elevated metallized source/drain region between the silicide region and the gate electrode. The elevated metallized source/drain region adjoins the silicide region. | 11-13-2008 |
| 20090117695 | BiCMOS Performance Enhancement by Mechanical Uniaxial Strain and Methods of Manufacture - A BiCMOS device with enhanced performance by mechanical uniaxial strain is provided. A first embodiment of the present invention includes an NMOS transistor, a PMOS transistor, and a bipolar transistor formed on different areas of the substrate. A first contact etch stop layer with tensile stress is formed over the NMOS transistor, and a second contact etch stop layer with compressive stress is formed over the PMOS transistor and the bipolar transistor, allowing for an enhancement of each device. Another embodiment has, in addition to the stressed contact etch stop layers, strained channel regions in the PMOS transistor and the NMOS transistor, and a strained base in the BJT. | 05-07-2009 |
| 20100213512 | High-Mobility Channel Devices on Dislocation-Blocking Layers - A method of forming an integrated circuit structure includes forming a first recess in the semiconductor substrate; and forming a dislocation-blocking layer in the first recess. The dislocation-blocking layer includes a semiconductor material. Shallow trench isolation (STI) regions are formed, wherein inner portions of the STI regions are directly over portions of the dislocation-blocking layer, and wherein inner sidewalls of the STI regions contact the dislocation-blocking layer. A second recess is formed by removing a portion of the dislocation-blocking layer between two of the inner sidewalls of the STI regions, with the two inner sidewalls facing each other. A semiconductor region is epitaxially grown in the second recess. | 08-26-2010 |
| 20100252816 | High-Mobility Multiple-Gate Transistor with Improved On-to-Off Current Ratio - A multi-gate transistor includes a semiconductor fin over a substrate. The semiconductor fin includes a central fin formed of a first semiconductor material; and a semiconductor layer having a first portion and a second portion on opposite sidewalls of the central fin. The semiconductor layer includes a second semiconductor material different from the first semiconductor material. The multi-gate transistor further includes a gate electrode wrapping around sidewalls of the semiconductor fin; and a source region and a drain region on opposite ends of the semiconductor fin. Each of the central fin and the semiconductor layer extends from the source region to the drain region. | 10-07-2010 |
| 20100252862 | Source/Drain Engineering of Devices with High-Mobility Channels - An integrated circuit structure includes a substrate, and a channel over the substrate. The channel includes a first III-V compound semiconductor material formed of group III and group V elements. A gate structure is over the channel. A source/drain region is adjacent the channel and includes a group-IV region formed of a doped group-IV semiconductor material selected from the group consisting essentially of silicon, germanium, and combinations thereof. | 10-07-2010 |
| 20100276668 | Reducing Source/Drain Resistance of III-V Based Transistors - An integrated circuit structure includes a substrate; a channel layer over the substrate, wherein the channel layer is formed of a first III-V compound semiconductor material; a highly doped semiconductor layer over the channel layer; a gate dielectric penetrating through and contacting a sidewall of the highly doped semiconductor layer; and a gate electrode on a bottom portion of the gate dielectric. The gate dielectric includes a sidewall portion on a sidewall of the gate electrode. | 11-04-2010 |
| 20100301390 | Gradient Ternary or Quaternary Multiple-Gate Transistor - An integrated circuit structure includes a semiconductor substrate; insulation regions over the semiconductor substrate; and an epitaxy region over the semiconductor substrate and having at least a portion in a space between the insulation regions. The epitaxy region includes a III-V compound semiconductor material. The epitaxy region also includes a lower portion and an upper portion over the lower portion. The lower portion and the semiconductor substrate have a first lattice mismatch. The upper portion and the semiconductor substrate have a second lattice mismatch different from the first lattice mismatch. | 12-02-2010 |
| 20100301392 | Source/Drain Re-Growth for Manufacturing III-V Based Transistors - A method of forming an integrated circuit structure includes providing a substrate, and epitaxially growing a first semiconductor layer over the substrate. The first semiconductor layer includes a first III-V compound semiconductor material formed of group III and group V elements. The method further includes forming a gate structure on the first semiconductor layer, and forming a gate spacer on at least one sidewall of the gate structure. After the step of forming the gate structure, a second semiconductor layer including a second III-V compound semiconductor material is epitaxially grown on the first semiconductor layer. | 12-02-2010 |
| 20100308379 | METHODS FOR FORMING A TRANSISTOR WITH A STRAINED CHANNEL - A semiconductor device and method for fabricating a semiconductor device providing reduced short channel effects is disclosed. The method comprises providing a substrate comprising a first material; forming at least one gate stack over the substrate; forming one or more recesses in the substrate, wherein the one or more recesses define at least one source region and at least one drain region; and forming a pocket, a first layer comprising a second material, and a second layer comprising a third material in the one or more recesses, the pocket being disposed between the first layer and the substrate. | 12-09-2010 |
| 20110024794 | FIN STRUCTURE FOR HIGH MOBILITY MULTIPLE-GATE TRANSISTOR - A vertical fin structure for a semiconductor transistor includes a semiconductor substrate, a fin layer on top of the substrate, a capping layer overlaying the fin layer, wherein the substrate comprises group IV semiconductor material, the fin layer comprises group IV semiconductor material, the capping layer comprises semiconductor compound from group III-V. The fin layer can comprise Ge, SiGe, SiC, or any combinations thereof. The semiconductor substrate can comprise Si, Ge, SiGe, or SiC. The capping layer can comprise GaAs, InGaAs, InAs, InSb, GaSb, GaN, InP, or any combinations thereof. The capping layer can provide more than a 4 percent lattice mismatch with the semiconductor substrate. The fin layer can be located in between shallow trench insulation (STI) layers that provide isolation from adjacent devices. The vertical fin structure can further include a high-k dielectric layer overlaying the capping layer and a metal gate layer overlaying the high-k dielectric layer. | 02-03-2011 |
| 20110031538 | CMOS STRUCTURE WITH MULTIPLE SPACERS - A semiconductor device includes a substrate having shallow trench isolation and source/drain regions located therein, a gate stack located on the substrate between the source/drain regions, a first gate spacer on the sidewall of the gate stack, and a second gate spacer on the sidewall of the first gate spacer. | 02-10-2011 |
| 20110062492 | High-Quality Hetero-Epitaxy by Using Nano-Scale Epitaxy Technology - An integrated circuit structure includes a semiconductor substrate formed of a first semiconductor material; two insulators in the semiconductor substrate; and a semiconductor region between and adjoining sidewalls of the two insulators. The semiconductor region is formed of a second semiconductor material different from the first semiconductor material, and has a width less than about 50 nm. | 03-17-2011 |
| 20110086491 | Growing a III-V Layer on Silicon using Aligned Nano-Scale Patterns - A method of forming an integrated circuit structure includes providing a wafer having a silicon substrate; forming a plurality of shallow trench isolation (STI) regions in the silicon substrate; and forming recesses by removing top portions of the silicon substrate between opposite sidewalls of the plurality of STI regions. Substantially all long sides of all recesses in the silicon substrate extend in a same direction. A III-V compound semiconductor material is then epitaxially grown in the recesses. | 04-14-2011 |
| 20110117730 | Growing III-V Compound Semiconductors from Trenches Filled with Intermediate Layers - A method of forming an integrated circuit structure includes forming an insulation layer over at least a portion of a substrate; forming a plurality of semiconductor pillars over a top surface of the insulation layer. The plurality of semiconductor pillars is horizontally spaced apart by portions of the insulation layer. The plurality of semiconductor pillars is allocated in a periodic pattern. The method further includes epitaxially growing a III-V compound semiconductor film from top surfaces and sidewalls of the semiconductor pillars. | 05-19-2011 |
