| Patent application number | Description | Published |
|---|
| 20080303498 | Current Generator - A current generator is provided, including a bandgap circuit, an operational amplifier, and an output resistor. The bandgap circuit is used to output a bandgap reference voltage insensitive to environment temperature and supply voltages. The operational amplifier has a positive input receiving the bandgap reference voltage, a negative input, and an output connected to the negative input to obtain an output voltage substantially equal to the bandgap reference voltage. The output resistor is connected to the output of the operational amplifier serially to generate an output current flowing through the output resistor. Thus, the output current generated by the current generator is insensitive to environment temperature and supply voltages, and therefore more accurate and stable. | 12-11-2008 |
| 20090058528 | Pre-Amplifier for a Receiver and a Method therefor - A pre-amplifier for a receiver is provided. The pre-amplifier includes a first and a second input operational amplifiers, an output module, a first and a second feedback circuits. The first and the second input operational amplifiers amplify an input differential voltage pair to output a first and a second differential voltage pairs. The output module includes a first and a second output operational amplifiers and an inverter. The first and the second output operational amplifiers amplify the first and the second differential voltage pairs to output a first and a second output amplified voltages. The inverter pulls an output voltage high or low based on the first and the second output amplified voltages. The first and second feedback circuits are respectively for pulling up the first differential voltage pair or pulling down the second differential voltage pair, such that the first and the second output operational amplifiers are not disabled. | 03-05-2009 |
| 20090091356 | Current-mode differential transmitter and receiver - A current-mode differential transmitter, receiving a single-end input voltage signal and accordingly generating a differential output current signal, is provided. The transmitter includes a first switch, a second switch and a current mirror. The first switch is coupled in a first current path and controlled by the single-end input voltage signal. The second switch is coupled in a second current path and controlled by an inverted signal of the single-end input voltage signal. The current mirror mirrors a reference current to the first current path when the first switch is turned on, and mirrors the reference current to the second current path when the second switch is turned on. The differential output current signal is derived from the currents on the first and second current paths. | 04-09-2009 |
| 20090096498 | Receiver system and method for automatic skew-tuning - A receiver system is provided. The receiver system includes a control unit for outputting a control signal and a selective signal, a PLL unit for generates PLL clock signals based on an initial clock signal, a phase select unit for selecting one of the PLL clock signals as a base clock signal according to the selective signal, a DLL unit for generating DLL clock signals based on the base clock signal, a sampling clock unit for generating left and right clock signals based on the DLL clock signals and a data latch unit for sampling bit data according to the left, DLL, and right clock signals to obtain left, middle and right data, which are feedback to the control unit for outputting the control signal and the selective signal to adjust the left, DLL and right clock signals or select the base clock signal for next bit data. | 04-16-2009 |
| 20090112499 | DEVICE FOR JITTER MEASUREMENT AND METHOD THEREOF - The device for jitter measurement and a method thereof are provided. The device for jitter measure includes a signal retrieving module, a signal amplifying module, an edge detecting module, and a time-to-digital converting module. The signal retrieving module receives a signal-under-test, and retrieves a first pulse signal having a pulse width equal to a period of the signal-under-test. The signal amplifying module amplifies the pulse width of the first pulse signal and thereby generates a second pulse signal. The edge detecting module detects a rising edge and a falling edge of the second pulse signal, and generates a first indication signal and a second indication signal according to the respective detected results. The time-to-digital converting module converts the pulse width of the second pulse signal existed in time domain to a digital signal according to the first indication signal and the second indication signal. | 04-30-2009 |
| 20090134914 | LOW OFFSET COMPARATOR AND OFFSET CANCELLATION METHOD THEREOF - A low offset comparator includes a preamplifier and a latch. The preamplifier includes a first output offset storage stage, a cascade of input offset storage stages and a second output offset storage stage. The first output offset storage stage receives an input voltage. The cascade of input offset storage stages is connected to follow the first output offset storage stage. The second output offset storage stage is connected to follow the input offset storage stages. The latch is connected to follow the preamplifier. The low offset comparator is characterized in that the cascade of input offset storage stages, the second output offset storage stage and the first output offset storage stage are configured to sequentially leave an offset cancellation mode, and the input offset storage stages, when leaving the offset cancellation mode, are to open their unity-gain feedback loops before disconnecting their input offset storages from a ground voltage. | 05-28-2009 |
| 20090212864 | PREAMPLIFIER FOR RECEIVER AND METHOD THEREOF - A preamplifier used in a receiver is provided. The preamplifier comprises an input circuit and an output circuit. The input circuit receives an input differential voltage pair, pulls it down when the common voltage of the input differential voltage pair is higher than a reference voltage. The output circuit receives the input differential voltage pair outputted from the input circuit to pull high or low an output voltage accordingly. | 08-27-2009 |
| 20100283641 | ANALOG TO DIGITAL CONVERTER - An analog to digital converter is provided. The converter comprises a dither gain generator, a first stage, an adder, a second stage, and a digital error correction logic. The dither gain generator generates a dither gain. The first stage receives a first voltage to generate a first digital code and a second voltage. The adder is coupled to the first stage and adds the dither voltage to the second voltage to generate a third voltage. The second stage receives the third voltage to generate a second digital code. The digital error correction logic receives and corrects the first digital code and the second digital code to generate a digital code corresponding to the first voltage. | 11-11-2010 |
| 20100283646 | ANALOG TO DIGITAL CONVERTER - An analog to digital converter is provided. The converter comprises a dither gain generator, a first stage, a multiplier, a second stage and a digital error correction logic. The dither gain generator generates a dither gain. The first stage receives a first voltage to generate a first digital code and a second voltage. The multiplier is coupled to the first stage and multiplies the second voltage with the dither gain to generate a third voltage. The second stage receives the third voltage to generate a second digital code. The digital error correction logic receives and corrects the first digital code and the second digital code to generate a digital code corresponding to the first voltage. | 11-11-2010 |
| 20100309038 | ANALOG TO DIGITAL CONVERTER - An analog to digital converter is provided. The converter comprises a first stage, an adjustment unit and a digital error correction logic. The first stage has a first sensing range and receives a first voltage to generate a first digital code. The adjustment unit adjusts the first sensing range of the first stage. The digital error correction logic receives and corrects the first digital code to generate a digital code corresponding to the first voltage. | 12-09-2010 |
| 20110058692 | AUDIO OUTPUT DEVICES - An audio output device is provided and includes a power source, a controller, a signal generating circuit, and a first amplifier. The power source provides a supply voltage signal. The controller receives the supply voltage signal. The controller further compares the supply voltage signal with a threshold voltage signal and generates a control signal according to the comparison result. The signal generating circuit generates a first analog signal. The first amplifier receives the first analog signal and generates a first amplified signal according to the control signal. | 03-10-2011 |
| 20110060431 | AUDIO OUTPUT DEVICES - An audio output device is provided and includes a signal source, a detector, a plurality of digital-to-analog converters, and a plurality of amplifiers. The signal source generates a plurality of digital signals. The detector receives the digital signals and detects states of the digital signals to generate a plurality of control signals according to the detection results respectively. The digital-to-analog converters receive the digital signals and convert the digital signals to a plurality of analog signals, respectively. The amplifiers receive the analog signals and generate a plurality of amplified signals according to the control signals, respectively. | 03-10-2011 |
| 20110140939 | SAMPLE HOLD CIRCUIT AND METHOD FOR SAMPLING AND HOLDING SIGNAL - A sample hold circuit and a method for sampling and holding a signal are provided. The sample hold circuit includes a sample unit, a direct current (DC) voltage elimination unit, and a hold unit. When the sample hold circuit is in a first state, the sample unit samples an input signal, and the DC voltage elimination unit lowers a predetermined percentage of the DC voltage in the input signal sampled by the sample unit. When the sample hold circuit is in a second state, the DC voltage elimination unit eliminates the residual percentage of the DC voltage, and the hold unit outputs the alternating current (AC) signal in the input signal sampled by the sample unit. | 06-16-2011 |
| 20110140947 | ANALOG-TO-DIGITAL CONVERSION UNIT AND ANALOG-TO-DIGITAL CONVERTING METHOD THEREOF - An analog-to-digital conversion unit (ADC unit) and an analog-to-digital converting method (ADC method) are provided. The ADC unit has a plurality of sub analog-to-digital converters and an encoding unit. Each of the employed sub analog-to-digital converters is coupled to two threshold voltages non-successive in terms of levels arrangement, compares the input voltage with the two threshold voltages and outputs two bits according to the comparison results. In this way, the difference between the two threshold voltages coupled by each of the sub analog-to-digital converters can be larger, which is advantageous in advancing the analog-to-digital converting accuracy. | 06-16-2011 |
| 20110148500 | SAMPLE HOLD CIRCUIT AND METHOD THEREOF FOR ELIMINATING OFFSET VOLTAGE OF ANALOG SIGNAL - A sample hold circuit and a method for eliminating the offset voltage of the analog signal are provided. The sample hold circuit includes a sample unit, a plurality of capacitors, a control unit and a hold unit. When the sample hold circuit is in a first state, the sample unit samples an analog signal. When the sample hold circuit is in a second state, the capacitors eliminate a DC offset voltage of the analog signal sampled by the sample unit, and the hold unit outputs an AC signal of the analog signal sampled by the sample unit. The control unit adjusts a number of the capacitances coupled to a common voltage according to a magnitude of the DC offset voltage, thus to determine the capacitance for eliminating the DC offset voltage. | 06-23-2011 |
