Patent application number | Description | Published |
20090146704 | DELAY LOCKED LOOP CIRCUIT AND METHOD FOR ELIMINATING JITTER AND OFFSET THEREIN - A delay locked loop (DLL) circuit is provided. The DLL circuit includes a divider, a shift register, a digital-to-analog converter and a voltage controlled delay line. The divider divides an input clock signal to output a reference clock signal. The shift register is triggered by the reference clock signal and outputs a digital signal corresponding to the reference clock signal in accordance with a phase difference between the input clock signal and a feedback clock signal. The digital-to-analog converter transfers the digital signal output from the shift register into a control voltage. The voltage controlled delay line outputs the feedback clock signal in accordance with the control voltage transferred by the digital-to-analog converter. A method for eliminating jitter and offset between an input clock signal and an output clock signal in a delay locked loop circuit is also disclosed. | 06-11-2009 |
20090146705 | DELAY LOCKED LOOP CIRCUIT AND METHOD FOR ELIMINATING JITTER AND OFFSET THEREIN - A delay locked loop circuit (DLL) is provided. The delay locked loop circuit includes a shift register, a digital-to-analog converter and a voltage controlled delay line. The shift register outputs a digital signal in accordance with a phase difference between an input signal and a feedback signal. The digital-to-analog converter transfers the digital signal output from the shift register into a control voltage. The voltage controlled delay line outputs the feedback signal in accordance with the control voltage transferred by the digital-to-analog converter. A method for eliminating jitter and offset between an input signal and an output signal in a delay locked loop circuit is also disclosed. | 06-11-2009 |
20090189656 | Delay-locked loop and a stabilizing method thereof - A delay-locked loop includes a phase detector, a shift register, a digital low pass filter, a digital to analog converter, a bias circuit, and a delay circuit. The phase detector generates a lagging signal and a leading signal corresponding to a phase difference between an input clock signal and a feedback clock signal. The shift register outputs a digital data according to the lagging signal and the leading signal. The digital low pass filter generates a selecting signal according to the digital data. The bias circuit generates a first control voltage and a second control voltage in response to the bias voltage converted from the selecting signal. The delay circuit generates the feedback clock signal corresponding to the first control voltage and the second control voltage. | 07-30-2009 |
20090189657 | Delay locked loop circuit and method for eliminating jitter and offset therein - A delay locked loop circuit includes a phase-frequency detector, a sampler, a charge pump, a bias generator and a voltage-controlled element. The phase-frequency detector outputs at least one difference signal by detecting a phase difference between an input clock signal and a feedback clock signal. The sampler outputs at least one sampled signal by delaying the difference signal in accordance with the input clock signal. The charge pump generates a control voltage in accordance with the sampled signal. The bias generator generates at least one bias voltage in accordance with the control voltage. The voltage-controlled element is controlled with the bias voltage to output the feedback clock signal to the phase-frequency detector in accordance with the input clock signal. A method for eliminating jitter and offset between an input clock signal and an output clock signal in a delay locked loop circuit is also disclosed. | 07-30-2009 |
20090273395 | PREAMPLIFIER AND METHOD FOR CALIBRATING OFFSET VOLTAGES THEREIN - A preamplifier includes cascade-connected amplifying circuits, and at least one of the cascade-connected amplifying circuits includes a differential switch pair circuit, a comparator and current sources. The differential switch pair circuit has a pair of differential inputs and a pair of differential outputs. The comparator outputs a comparison signal by comparing the differential outputs. The current sources are respectively and selectively coupled to one of the differential outputs based on the comparison signal to adjust voltages of the differential outputs. A method for calibrating offset voltages in a preamplifier is also disclosed herein. | 11-05-2009 |
20090274319 | AUDIO AMPLIFIER - An audio amplifier includes an amplifying circuit, a bias control circuit, and a decoupling device. The amplifying circuit amplifies an audio signal. The bias control circuit provides at least one bias voltage for the amplifying circuit according to a power down signal, in which the power down signal represents that the audio amplifier is powered on or powered down. The decoupling device reduces the damping phenomenon of the bias voltage caused by powering on or powering down the audio amplifier. | 11-05-2009 |
20090278601 | Preamplifier and method for calibrating offsets therein - A preamplifier includes cascade-connected amplifying circuits, and at least one of the cascade-connected amplifying circuits includes a differential switch pair circuit, a comparator and energy storing elements. The differential switch pair circuit has a pair of differential inputs and a pair of differential outputs. The comparator -outputs a comparison signal by comparing the differential outputs. The energy storing elements are respectively and selectively coupled to one of the differential outputs based on the comparison signal to adjust potential of the differential outputs. A method for calibrating offsets in a preamplifier is also disclosed herein. | 11-12-2009 |
20090284313 | AUDIO AMPLIFIER - An audio amplifier, amplifying the audio signal, includes a first filtering circuit, and a second filtering circuit. The first filtering circuit generates an inverting driving voltage to drive a load according to the audio signal. The second filtering circuit generates a non-inverting driving voltage to drive the load according to the inverting driving voltage. The first filtering circuit and the second filtering circuit filter out signals with frequencies greater than a pre-determined frequency. | 11-19-2009 |
20090284314 | AUDIO AMPLIFIER - An audio amplifier includes a timing control circuit, an amplifying circuit, and a bias control circuit. The timing control circuit generates a first power down signal and a second power down signal, in which the first power down signal is asserted before the second power down signal is asserted. The amplifying circuit receives a bias voltage to amplify an audio signal and is deactivated when the first power down signal is asserted. The bias control circuit provides the bias voltage for the amplifying circuit and is deactivated when the second power down signal is asserted. | 11-19-2009 |
20100201553 | A/D Converter and Method for Enhancing Resolution of Digital Signal - A method for enhancing resolution of digital signals converted from analog signals is provided. The method includes the steps of: converting an analog input signal into N-bit digital outputs, where N is a positive integer; interpolating the N-bit digital outputs to add one or more least significant bit orders for the N-bit digital outputs; generating one or more dither values as least significant bits corresponding to the least significant bit orders; and superimposing the dither values on the interpolation of the N-bit digital outputs. An A/D converter is also disclosed herein. | 08-12-2010 |
20120281857 | AUDIO AMPLIFIER - An audio amplifier includes a timing control circuit, an amplifying circuit, and a bias control circuit. The timing control circuit generates a first power down signal and a second power down signal, in which the first power down signal is asserted before the second power down signal is asserted. The amplifying circuit receives a bias voltage to amplify an audio signal and is deactivated when the first power down signal is asserted. The bias control circuit provides the bias voltage for the amplifying circuit and is deactivated when the second power down signal is asserted. | 11-08-2012 |