Patent application number | Description | Published |
20080248638 | PROCESS FOR MANUFACTURING VOLTAGE-CONTROLLED TRANSISTOR - The present invention provides a self-driven LDMOS which utilizes a parasitic resistor between a drain terminal and an auxiliary region. The parasitic resistor is formed between two depletion boundaries in a quasi-linked deep N-type well. When the two depletion boundaries pinch off, a gate-voltage potential at a gate terminal is clipped at a drain-voltage potential at said drain terminal. Since the gate-voltage potential is designed to be equal to or higher than a start-threshold voltage, the LDMOS is turned on accordingly. Besides, no additional die space and masking process are needed to manufacture the parasitic resistor. Furthermore, the parasitic resistor of the present invention does not lower the breakdown voltage and the operating speed of the LDMOS. In addition, when the two depletion boundaries pinch off, the gate-voltage potential does not vary in response to an increment of the drain-voltage potential. | 10-09-2008 |
20090050962 | MOSFET WITH ISOLATION STRUCTURE FOR MONOLITHIC INTEGRATION AND FABRICATION METHOD THEREOF - A MOSFET device with an isolation structure for a monolithic integration is provided. A P-type MOSFET includes a first N-well disposed in a P-type substrate, a first P-type region disposed in the first N-well, a P+ drain region disposed in the first P-type region, a first source electrode formed with a P+ source region and an N+ contact region. The first N-well surrounds the P+ source region and the N+ contact region. An N-type MOSFET includes a second N-well disposed in a P-type substrate, a second P-type region disposed in the second N-well, an N+drain region disposed in the second N-well, a second source electrode formed with an N+ source region and a P+ contact region. The second P-type region surrounds the N+ source region and the P+ contact region. A plurality of separated P-type regions is disposed in the P-type substrate to provide isolation for transistors. | 02-26-2009 |
20110069420 | PROTECTION TO A POWER CONVERTER BY USING A HIGH-VOLTAGE START-UP DEVICE IN A CONTROLLER CHIP OF THE POWER CONVERTER - A controller chip provides protection to a power converter by using a high-voltage start-up device in the controller chip, without additional pins or external elements of the controller chip. A JFET is used as the high-voltage start-up device connected between a high-voltage pin and a power input pin of the controller chip, to charge a power capacitor connected to the power input pin at power on. The controller chip monitors the voltage at the power input pin and turns off the JFET once the voltage at the power input pin increases to reach a threshold. Thereafter, the source voltage of the JFET will reflect the voltage at the high-voltage pin, and a protection circuit monitors the source voltage of the JFET to trigger a protection signal. | 03-24-2011 |
20120106209 | METHOD FOR GENERATING A CURRENT LIMIT SIGNAL FOR A POWER CONVERTER WITHOUT SENSING AN INPUT VOLTAGE OF THE POWER CONVERTER - A method for generating a current limit signal for a power converter without sensing an input voltage of the power converter detects a current of a power switch of the power converter to obtain a current sense signal, counts a time for the current sense signal to increase from a first level to a second level, and according to the time, determines a current limit signal for limiting a maximum value of the current of the power switch for the power converter to have a constant maximum output power. | 05-03-2012 |
20120313616 | AC DISCHARGE CIRCUIT FOR AN AC-TO-DC SWITCHING POWER CONVERTER - An AC discharge circuit is disclosed to eliminate the need of bleeding resistors for an AC-to-DC switching power converter. The AC-to-DC switching power converter has two AC power input terminals to be connected to an AC power source, and an AC input capacitor connected between the two AC power input terminals. The AC discharge circuit has a rectifier circuit to rectify a first voltage across the AC input capacitor to be a second voltage applied to an input terminal of a JFET, and a power removal detector to monitor a third voltage at an output terminal of the JFET to trigger a power removal signal to discharge the AC input capacitor when the third voltage has been remained larger than a threshold for a de-bounce time. | 12-13-2012 |
20130271041 | DRIVER CIRCUIT FOR IMPROVING UTILIZATION RATE OF LED DEVICE AND RELATED CONSTANT CURRENT REGULATOR - A driver circuit for driving an LED array is disclosed. The LED array includes a first, a second, a third, a fourth LED device and a diode device. The second LED device is connected to the first LED device. The fourth LED device is connected to the third LED device. The diode device is connected between the second LED device and the third LED device. The driver circuit includes a first constant current regulator for coupling between the first and the second LED device; a second constant current regulator for coupling between the second and the third LED device; a third constant current regulator for coupling between the third and the fourth LED device; a fourth constant current regulator for coupling between the fourth LED device and a fixed-voltage terminal; and a control circuit coupled with the first, the second, the third, and the fourth constant current regulators. | 10-17-2013 |
20140354163 | LED DRIVING DEVICE - An LED driving device includes: a rectifying circuit for outputting a DC voltage to a string of M LED units; (M−1) first switching circuits each coupled between a corresponding one of first to (M−1) | 12-04-2014 |
20140355320 | CONTROL CIRCUIT FOR AC-DC POWER CONVERTER - A control circuit for an AC-DC power converter includes a junction field effect transistor (JFET), a first resistor, a second resistor, and a third resistor. The JFET includes a substrate, a drain, a source, a gate, a first oxide layer, and a second oxide layer. The first oxide layer is attached to a region located between the drain and the gate of the JFET, and the second oxide layer is not attached to a region located between the drain and the gate of the JFET. The first resistor is positioned on the first oxide layer, and the second resistor and the third resistor are positioned on the second oxide layer. When the JFET and the first resistor receive an input power signal, the first, the second, and the third resistors divide the input power signal, and prevent from the breakdown of the first oxide layer and the second oxide layer. | 12-04-2014 |