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| 20080277728 | Semiconductor structure for protecting an internal integrated circuit and method for manufacturing the same - A semiconductor structure for protecting an internal integrated circuit comprises a substrate; a plurality of first doping regions formed in the substrate and disposed substantially within an N-well; a plurality of second doping regions, formed in the substrate and disposed within an P-well; a N+ section, formed in the substrate and enclosing the N-well and the P-well; a pad, formed above the substrate and electrically connected to at least one of the first doping regions; and a first ground and a second ground respectively disposed to positions corresponding to outside and inside of the N+ section. Also, the second doping regions are isolated from the first doping regions. The first and second doping regions located within the N+ section are isolated from the substrate by the N+ section. Furthermore, the second ground is electrically connected to at least one of the second doping regions. | 11-13-2008 |
| 20080278279 | Semiconductor structure with high breakdown voltage and resistance and method for manufacturing the same - A semiconductor structure with high breakdown voltage and high resistance and method for manufacturing the same. The semiconductor structure at least comprises a substrate having a first conductive type; a deep well having a second conductive type formed in the substrate; two first wells having the first conductive type and formed within the deep well; a second well having the first conductive type and formed between two first wells within the deep well, and a implant dosage of the second well lighter than a implant dosage of the first well; and two first doping regions having the first conductive type and respectively formed within the first wells. | 11-13-2008 |
| 20100295092 | INTEGRATED PMOS TRANSISTOR AND SCHOTTKY DIODE - The present invention discloses an integrated PMOS transistor and Schottky diode, comprising a PMOS transistor which includes a gate, a source, a drain and a channel region between the source and drain, wherein the source, drain and channel region are formed in a substrate, and a parasitic diode is formed between the drain and the channel region; and a Schottky diode formed in the substrate and connected in reverse series with the parasitic diode, the Schottky diode having one end connected with the parasitic diode and the other end connected with the source. | 11-25-2010 |
| 20110068365 | Isolated SCR ESD device - The present invention discloses an isolated SCR ESD device, comprising: a substrate; a first well located in the substrate, which is floating and has a first conductivity type; a first high density doped region located in the first well and having a second conductivity type; a second well nearby the first well and having the second conductivity type; a second high density doped region located in the second well and having the second conductivity type; and a third high density doped region located in the second well and having the first conductivity type, wherein the first high density doped region is for electrical connection with a pad, and wherein the first well is not provided with a high density doped region having the first conductivity type for connection with the pad. | 03-24-2011 |
| 20110068366 | Bi-directional SCR ESD device - The present invention discloses a bi-directional SCR ESD device, comprising: a substrate; a first well located in the substrate, which is floating and has a first conductivity type; a second well and a third well both located in the first well and both having a second conductivity type, the second well and the third well being separated from each other; a first high density doped region of the first conductivity type and a second high density doped region of the second conductivity type located in the second well; and a third high density doped region of the first conductivity type and a fourth high density doped region of the second conductivity type located in the third well. | 03-24-2011 |
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| 20080248638 | PROCESS FOR MANUFACTURING VOLTAGE-CONTROLLED TRANSISTOR - The present invention provides a self-driven LDMOS which utilizes a parasitic resistor between a drain terminal and an auxiliary region. The parasitic resistor is formed between two depletion boundaries in a quasi-linked deep N-type well. When the two depletion boundaries pinch off, a gate-voltage potential at a gate terminal is clipped at a drain-voltage potential at said drain terminal. Since the gate-voltage potential is designed to be equal to or higher than a start-threshold voltage, the LDMOS is turned on accordingly. Besides, no additional die space and masking process are needed to manufacture the parasitic resistor. Furthermore, the parasitic resistor of the present invention does not lower the breakdown voltage and the operating speed of the LDMOS. In addition, when the two depletion boundaries pinch off, the gate-voltage potential does not vary in response to an increment of the drain-voltage potential. | 10-09-2008 |
| 20090050962 | MOSFET WITH ISOLATION STRUCTURE FOR MONOLITHIC INTEGRATION AND FABRICATION METHOD THEREOF - A MOSFET device with an isolation structure for a monolithic integration is provided. A P-type MOSFET includes a first N-well disposed in a P-type substrate, a first P-type region disposed in the first N-well, a P+ drain region disposed in the first P-type region, a first source electrode formed with a P+ source region and an N+ contact region. The first N-well surrounds the P+ source region and the N+ contact region. An N-type MOSFET includes a second N-well disposed in a P-type substrate, a second P-type region disposed in the second N-well, an N+drain region disposed in the second N-well, a second source electrode formed with an N+ source region and a P+ contact region. The second P-type region surrounds the N+ source region and the P+ contact region. A plurality of separated P-type regions is disposed in the P-type substrate to provide isolation for transistors. | 02-26-2009 |
| 20110069420 | PROTECTION TO A POWER CONVERTER BY USING A HIGH-VOLTAGE START-UP DEVICE IN A CONTROLLER CHIP OF THE POWER CONVERTER - A controller chip provides protection to a power converter by using a high-voltage start-up device in the controller chip, without additional pins or external elements of the controller chip. A JFET is used as the high-voltage start-up device connected between a high-voltage pin and a power input pin of the controller chip, to charge a power capacitor connected to the power input pin at power on. The controller chip monitors the voltage at the power input pin and turns off the JFET once the voltage at the power input pin increases to reach a threshold. Thereafter, the source voltage of the JFET will reflect the voltage at the high-voltage pin, and a protection circuit monitors the source voltage of the JFET to trigger a protection signal. | 03-24-2011 |
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| 20100163934 | METHOD FOR FABRICATING A JUNCTION FIELD EFFECT TRANSISTOR AND THE JUNCTION FIELD EFFECT TRANSISTOR ITSELF - A method for fabricating a junction field effect transistor includes the steps of the type I semiconductor at the base thereof being doped with the type II semiconductor to form a type II well with a hole; then, a drive-in process of the type II semiconductor is performed to allow the implant dosage of the type II well getting less gradually from the surroundings of the hole toward the center of the hole; and finally, the gate, the source and the drain of the junction field effect transistor being formed successively on the type II well. The implant dosage at the hole, which is acted as a channel, is determined in accordance with the preset size of the hole during the type II well being formed such that it is capable being compatible with the output voltages of different junction field effect transistors to achieve the purpose of the adjustment of the pinch-off voltage of the junction field effect transistor without the need of the mask and the manufacturing process. | 07-01-2010 |
| 20100165685 | POWER TRANSISTOR CHIP WITH BUILT-IN JUNCTION FIELD EFFECT TRANSISTOR AND APPLICATION CIRCUIT THEREOF - A power transistor chip and an application circuit thereof has a junction field effect transistor to act as a start-up circuit of an AC/DC voltage converter. The start-up circuit can be turned off after the PWM circuit of the AC/DC voltage converter operates normally to conserve the consumption of the power. Besides, the junction field effect transistor is built in the power transistor chip. Because the junction field effect transistor is fabricated with the same manufacturing process as the power transistor, it is capable of simplifying the entire process and lowering the production cost due to no additional mask and manufacturing process. | 07-01-2010 |
| 20100177542 | POWER TRANSISTOR CHIP WITH BUILT-IN START-UP TRANSISTOR AND APPLICATION CIRCUIYT THEREOF - A power transistor chip with a built-in start-up transistor and an application circuit thereof provides a junction field effect transistor in association with a metal oxide semiconductor field effect transistor to act as a start-up circuit of an AC/DC voltage converter. The start-up circuit can be turned off after the PWM circuit of the AC/DC voltage converter operates normally to conserve the consumption of the power. Besides, the junction field effect transistor and the metal oxide semiconductor field effect transistor are built in the power transistor chip. Because the junction field effect transistor and the metal oxide semiconductor field effect are fabricated with the same manufacturing process as the power transistor, it is capable of simplifying the entire process and lowering the production cost due to no additional mask and manufacturing process. | 07-15-2010 |
| 20100271850 | POWER TRANSISTOR CHIP WITH BUILT-IN ENHANCEMENT MODE METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR AND APPLICATION CIRCUIT THEREOF - A power transistor chip with built-in enhancement mode metal oxide semiconductor field effect transistor and application circuit thereof provides an enhancement mode metal oxide semiconductor field effect transistor in association with two series connected resistors to act as a start-up circuit for the AC/DC voltage converter. The start-up circuit can be shut off after the pulse width modulation circuit of the AC/DC voltage converter circuit works normally and still capable of offering a function of brown out detection for the pulse width modulation circuit as well. Besides, the enhancement mode metal oxide semiconductor field effect transistor is built in the power transistor chip without additional masks and processes during the power transistor chip being fabricated such that the entire manufacturing process is simplified substantively with the economical production cost. | 10-28-2010 |
| 20100295515 | Integrated PMOS Transistor and Schottky Diode and Charging Switch Circuit Employing The Integrated Device - The present invention discloses an integrated PMOS transistor and Schottky diode, comprising a PMOS transistor which includes a gate, a source, a drain and a channel region between the source and drain, wherein the source, drain and channel region are formed in a substrate, and a parasitic diode is formed between the drain and the channel region; and a Schottky diode formed in the substrate and connected in reverse series with the parasitic diode, the Schottky diode having one end connected with the parasitic diode and the other end connected with the source. | 11-25-2010 |
