Patent application number | Description | Published |
20100320472 | PIXEL ELECTRODE STRUCTURE WITH HIGH DISPLAY QUALITY - A pixel electrode structure includes a transparent substrate, a data line, a common line, a first array pixel, and a second array pixel disposed on the transparent substrate. The first/second array pixels respectively include a thin film transistor, a pixel electrode, and a gate line, and the common line is disposed at a lateral side of the gate line. A first via hole and a second via hole are respectively disposed on common line and in contact with an extending portion of the first thin film transistor and an extending portion of the second thin film transistor. A dummy line is disposed at a side of the data line, and a third via hole is disposed both on the dummy line and on the common line. The present invention can not only increase the aperture ratio of the pixel, but have a better stability of the common voltage signal. | 12-23-2010 |
20100321602 | DISPLAY PANEL - The present invention provides a display panel including a plurality of dual-gate pixel units connected to each other through data lines, gate lines and common lines. Each dual-gate pixel unit includes a first pixel and a second pixel respectively connected to a first gate line and a second gate line, and shares a common line and a data line. The first pixel and the second pixel are respectively disposed at two opposite sides of the common line, and they are also respectively disposed at two opposite sides of the first data line and the second gate line. The data lines transfer data signals into pixels, and the gate lines control the pixels to receive the data signals. The present invention raises an aperture ratio of each pixel of the display panel, and reduces the probability of the gate line and the common line being short-circuited. | 12-23-2010 |
20110115691 | PIXEL ARRAY - A pixel array includes scan lines extended along a row direction in a zigzag manner, data lines extended along a column direction, and pixels connected the scan lines and the data lines. Each pixel arranged in n | 05-19-2011 |
20110133194 | PIXEL STRUCTURE - A pixel structure includes a scan line, a data line, a gate electrode electrically connected to the scan line, a semiconductor layer disposed on the gate electrode, a drain electrode, an extending electrode, and a pixel electrode. The scan line and the data line cross each other, and are insulated. The drain electrode includes a contact part disposed outside the gate electrode, an electrode part disposed on the semiconductor pattern and a connecting part extending from the contact part along a direction to connect the electrode part, and partially overlapping the gate electrode. The pixel electrode is connected to the contact part. The extending electrode is connected to the scan line. A first end of the extending electrode points to the semiconductor layer along the direction, and overlaps the drain electrode. A first width of the connecting part is equal to the second width of the extending electrode. | 06-09-2011 |
20120092606 | ARRAY SUBSTRATE OF FRINGE FIELD SWITCHING MODE LIQUID CRYSTAL DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME - An array substrate of a fringe field switching (FFS) mode liquid crystal display (LCD) panel and manufacturing method thereof are provided. The gate electrodes and the common electrode of the FFS mode LCD panel are formed on the array substrate by the same photolithographic process, and the common electrode, the gate lines and the gate electrodes are disposed on the same layer. | 04-19-2012 |
20130083280 | ARRAY SUBSTRATE OF FRINGE FIELD SWITCHING MODE LIQUID CRYSTAL DISPLAY PANEL AND METHOD OF MANUFACTURING THE SAME - An array substrate of a fringe field switching (FFS) mode liquid crystal display (LCD) panel and manufacturing method thereof are provided. The gate electrodes and the common electrode of the FFS mode LCD panel are formed on the array substrate by the same photolithographic process, and the common electrode, the gate lines and the gate electrodes are disposed on the same layer. The passivation layer of the FFS mode LCD panel is formed on the pixel electrodes. The passivation layer has a plurality of first openings, and each of the first openings at least partially exposes the pixel electrodes. | 04-04-2013 |
20130155537 | COLOR FILTER SUBSTRATE - A color filter substrate includes a transparent substrate, a patterned light-shielding layer, a plurality of color filter units, and a plurality of dummy color filter units. The transparent substrate has a display region and a peripheral region surrounding the display region. The patterned light-shielding layer is disposed on the transparent substrate, and the patterned light-shielding layer includes a first light-shielding pattern disposed on the display region and a second light-shielding pattern disposed on the peripheral region. The first light-shielding pattern defines a plurality of sub-pixel regions. The color filter units are disposed on the display region. The dummy color filter units are disposed on the peripheral region. Spacing between two adjacent dummy color filter units or spacing between the color filter unit and the adjacent dummy color filter unit is wider than spacing between two adjacent color filter units. | 06-20-2013 |
Patent application number | Description | Published |
20080303966 | PIXEL STRUCTURE - A pixel structure including a substrate, a scan line, a data line, a first and a second switching device, a first and a second pixel electrode, a first and a second bended pixel electrode, a first and a second connecting conductive layer, and a first and a second common line is provided. The scan line and data line demarcate a first and a second areas on the substrate, and the scan line is located between the two areas. The first and second switching devices are electrically connected to the scan line and the data line and are also electrically connected to the first and second pixel electrodes on the first and second areas respectively. The first and second bended pixel electrodes on the second and first areas are electrically connected to the first and second pixel electrodes through the first and second connecting conductive layers on the scan line respectively. | 12-11-2008 |
20080303970 | PIXEL STRUCTURE - A pixel structure includes a gate, a source, a first drain, a second drain, a third drain, a first pixel electrode, a second pixel electrode, a scan line and a data line. The gate, the source and the first drain form a first thin film transistor. The gate, the source and the second drain form a second thin film transistor. The gate, the second drain and the third drain form a sub-thin film transistor (sub-TFT). Additionally, the first pixel electrode is electrically connected to the first drain, and the second drain extends to a portion between the second pixel electrode and the substrate such that a capacitor-coupling electrode is formed. Moreover, the second pixel electrode is electrically connected to the third drain of the sub-TFT. The scan line is disposed on the substrate and electrically connected to the gate, and the data line is electrically connected to the source. | 12-11-2008 |
20100237350 | PIXEL STRUCTURE - A pixel structure suitable for being disposed on a substrate includes a thin film transistor (TFT), a first pixel electrode, a second pixel electrode, a scan line and a data line. The TFT disposed on the substrate includes a gate, a source, a first drain and a second drain. A main TFT is formed by the gate, the source and the first drain. A sub-thin film transistor (sub-TFT) is formed by the gate, the first drain and the second drain. The first pixel electrode is electrically connected to the first drain, and a portion of the first drain extends between the second pixel electrode and the substrate to form capacitor-coupling electrode. The second pixel electrode is electrically connected to the second drain of the sub-TFT. The scan line is disposed on the substrate and electrically connected to the gate, and the data line is electrically connected to the source. | 09-23-2010 |