Patent application number | Description | Published |
20100060339 | VOLTAGE LEVEL SHIFTER WITH VOLTAGE BOOST MECHANISM - A voltage level shifter with voltage boost mechanism is disclosed for interfacing two circuit units having different operating voltage swings. The voltage level shifter includes a first inverter, a second inverter, a first capacitor, a second capacitor and a plurality of transistors. The input and power ends of the first inverter function to receive an input voltage and a first voltage respectively. The output end of the second inverter functions to provide an output voltage. When the input voltage is a ground voltage, the output voltage is also a ground voltage; meanwhile, the switches are controlled for charging the first and second capacitors to a second voltage and a third voltage respectively. When the input voltage is the first voltage, a sum voltage of the first, second, and third voltages is furnished to the power end of the second inverter for providing the sum voltage as the output voltage. | 03-11-2010 |
20100109559 | METHOD AND CIRCUIT OF CONTROLLING AN LED CHARGE PUMP DRIVING CIRCUIT - An LED charge pump driving circuit includes a charge pump, a control circuit, a driver, and an LED. The charge pump generates an output voltage according to an input voltage. The driver drives the LED according to the output voltage so as to generate a load voltage. When the load voltage is greater than a first predetermined voltage, the charge pump is turned on. When the load voltage is smaller than a second predetermined voltage over a predetermined duration, the charge pump is turned off. When the load voltage is greater than a third predetermined voltage, the driver is locked. | 05-06-2010 |
20100111137 | TEMPERATURE SENSING CIRCUIT USING CMOS SWITCH-CAPACITOR - A temperature sensing circuit using CMOS switch-capacitor includes a PNP BJT, a hysteresis comparator, a transconductance amplifier, two current sources, two capacitors, and six switches. A voltage complementary to the absolute temperature (CTAT) is generated according to the PNP BJT, and a voltage proportional to the absolute temperature (PTAT) is generated according to two capacitors and the transconductance amplifier. When the voltage proportional to absolute temperature is greater than the voltage complementary to absolute temperature as the temperature rising, the hysteresis comparator outputs a high level signal. | 05-06-2010 |
20100264894 | SWITCH DRIVING CIRCUIT - A switch driving circuit includes a buffer module, a capacitor module, a first switch module, a second switch module, and a control module. The buffer module generates a driving voltage according to a control voltage. The first switch module is turned on when the control voltage is at a low voltage level to provide a supply voltage to the buffer module and charge the capacitor module by the supply voltage to generate a compensation voltage. The second switch module is turned on when the control voltage is at a high voltage level to provide the compensation voltage to the buffer module. When the supply voltage is higher than a reference voltage, the control module turns on the first switch module and turns off the second module to provide the supply voltage to the buffer module. | 10-21-2010 |
20100283396 | LIGHT SOURCE SYSTEM AND LIGHT SOURCE DRIVING CIRCUIT - A light source driving circuit includes a plurality of light-emitting loads, an operational amplifier, a plurality of transistors, an isolation circuit, and a reference circuit. The first ends of each transistor are electrically connected to the plurality of light-emitting loads respectively. The second end of each transistor is electrically connected to a current mirror. The control end of each transistor is electrically connected to the output end of the operational amplifier. The isolation circuit is electrically connected between the negative input end of the operational amplifier and the plurality of transistors. | 11-11-2010 |
20120176186 | Bandgap Reference Apparatus and Methods - Structure and methods for a compensated bandgap reference circuit. A first integrated circuit die having a first bandgap reference circuit with a non-zero temperature coefficient; and having a first output reference signal is provided, a second integrated circuit die having a second bandgap reference circuit with a non-zero temperature coefficient that is of opposite polarity from the temperature coefficient of the first bandgap reference circuit, and having a second output reference signal is provided; an adder circuit disposed on at least one of the first and second integrated circuit dies combines the first and second output reference signals, and outputs a combined reference signal; and connectors for connecting the first and second output signals to the adder circuit are provided. Methods are disclosed for pairing integrated circuit dies with bandgap reference circuits and coupling the dies to form temperature compensated signals. | 07-12-2012 |
20120176189 | REDUCED SWING SIGNAL - A circuit includes an inverter. The inverter inverts an input signal having an input low voltage level and an input high voltage level to form an output signal having an output high voltage level and an output low voltage level. Compared to the input high voltage level, the output high voltage level is lowered. Alternatively or additionally, compared to the input low voltage level, the output low voltage level is raised. | 07-12-2012 |
20120286814 | 3D IC Testing Apparatus - A three dimensional (3D) integrated circuit (IC) testing apparatus comprises a plurality of connection devices. When a device under test (DUT) such as an interposer or a 3D IC formed by a plurality of 3D dies operates in a testing mode, the 3D IC testing apparatus is coupled to the DUT via a variety of interface channels such as probes. The connection devices and a variety of through silicon vias (TSVs) in the DUT form a TSV chain so that a electrical characteristic test of the variety of TSVs can be tested all at once. | 11-15-2012 |
20130007692 | TOOL AND METHOD FOR MODELING INTERPOSER RC COUPLINGS - A method comprises analyzing front side conductive patterns and back side conductive patterns on a semiconductor interposer using a machine implemented RC extraction tool, and outputting data representing a plurality of respective RC nodes from the RC extraction tool to a tangible persistent machine readable storage medium. A substrate mesh model of the semiconductor interposer is generated, having a plurality of substrate mesh nodes. Each substrate mesh node is connected to adjacent ones of the plurality of substrate mesh nodes by respective substrate impedance elements. A set of inputs to a timing analysis tool is formed. The plurality of RC nodes are connected to ones of the plurality of substrate mesh nodes of the substrate mesh model. The set of inputs is stored in a tangible machine readable storage medium. | 01-03-2013 |
20130193981 | SWITCHED CAPACITOR COMPARATOR CIRCUIT - A circuit including a first switch receiving an input reference voltage, a second switch receiving an input testing voltage, the first switch and the second switch are electrically connected in parallel. The circuit further includes a first capacitor electrically connected in series with the first switch and the second switch. The circuit further includes a feedback stage comprising a feedback inverter electrically connected in parallel with a feedback switch, where the feedback stage is electrically connected in series with the first capacitor. The circuit further includes a first inverter electrically connected in series to the feedback stage, and a third switch electrically connected in series with the first inverter. The circuit further includes a second inverter electrically connected in parallel to a third inverter, the second inverter and the third inverter are electrically connected in series to the third switch, and the third inverter outputs a first output signal. | 08-01-2013 |
20150087089 | 3D IC Testing Apparatus - A method comprises connecting a testing setup having a plurality of probes to a device under test having a plurality of vias, wherein a probe is aligned with a corresponding via of the device under test and conducting a plurality of via electrical characteristic tests through a conductive path comprising the vias, the probes and a plurality of conductive devices, each of which connects two adjacent probes, wherein the conductive devices are in the testing setup. | 03-26-2015 |
Patent application number | Description | Published |
20080297713 | Circuit Signal Connection Interface, a Manufacture Method Thereof, and an Electronic Device Using the Same - A circuit signal connection interface, a manufacturing method thereof, and an electronic device using the same are provided. The circuit signal connection interface includes a first signal line and a second signal line juxtaposed to each other, an insulation layer, and a first conductive pad. The first conductive pad electrically connects to the first signal line, and crosses the second signal line. The insulation layer is disposed between the second signal line and the first conductive pad. The electronic device further includes a circuit device including a first conducting bump and a second conducting bump connected to each other in a parallel manner. The first conducting bump electrically connects to a first portion of the first conductive pad while the second conducting bump electrically connects to a second portion of the first conductive pad. | 12-04-2008 |
20110165773 | Circuit Signal Connection Interface - A circuit signal connection interface, a manufacturing method thereof, and an electronic device using the same are provided. The circuit signal connection interface includes a first signal line and a second signal line juxtaposed to each other, an insulation layer, and a first conductive pad. The first conductive pad electrically connects to the first signal line, and crosses the second signal line. The insulation layer is disposed between the second signal line and the first conductive pad. The electronic device further includes a circuit device including a first conducting bump and a second conducting bump connected to each other in a parallel manner. The first conducting bump electrically connects to a first portion of the first conductive pad while the second conducting bump electrically connects to a second portion of the first conductive pad. | 07-07-2011 |