| Patent application number | Description | Published |
|---|
| 20080197499 | STRUCTURE FOR METAL CAP APPLICATIONS - An interconnect structure is provided in which the conductive features embedded within a dielectric material are capped with a metallic capping layer, yet no metallic residue is present on the surface of the dielectric material in the final structure. The inventive interconnect structure has improved dielectric breakdown strength as compared to prior art interconnect structures. Moreover, the inventive interconnect structure has better reliability and technology extendibility for the semiconductor industry. The inventive interconnect structure includes a dielectric material having at least one metallic capped conductive feature embedded therein, wherein a top portion of said at least one metallic capped conductive feature extends above an upper surface of the dielectric material. A dielectric capping layer is located on the dielectric material and it encapsulates the top portion of said at least one metallic capped conductive feature that extends above the upper surface of dielectric material. | 08-21-2008 |
| 20080203570 | STRUCTURE INCLUDING VIA HAVING REFRACTORY METAL COLLAR AT COPPER WIRE AND DIELECTRIC LAYER LINER-LESS INTERFACE AND RELATED METHOD - Structures including a refractory metal collar at a copper wire and dielectric layer liner-less interface, and a related method, are disclosed. In one embodiment, a structure includes a copper wire having a liner-less interface with a dielectric layer thereabove; a via extending upwardly from the copper wire through the dielectric layer; and a refractory metal collar extending from a side of the via and partially along the liner-less interface. Refractory metal collar prevents electromigration induced slit voiding by improving the interface around the via, and prevents void nucleation from occurring near the via. Also, the refractory metal collar provides electrical redundancy in the presence of voids around the via and dielectric layer liner-less interface. | 08-28-2008 |
| 20080230848 | STRUCTURE HAVING DUAL SILICIDE REGION AND RELATED METHOD - A structure including a dual silicide region and a related method are disclosed. The structure may include a doped silicon, and a dual silicide region in the doped silicon, the dual silicide region including a first silicide region including a mid band gap metal, and a second silicide region including a near band gap metal, wherein the second silicide region is immediately adjacent to the doped silicon. The method may include forming a first silicide portion in a doped silicon by depositing a first metal over the doped silicon, annealing and removing unreacted first metal; ion implanting a second metal into the doped silicon; and annealing to form a second silicide portion from the second metal, wherein the first metal is different than the second metal. | 09-25-2008 |
| 20080230906 | CONTACT STRUCTURE HAVING DIELECTRIC SPACER AND METHOD - A contact structure and method of forming same are disclosed. The contact structure may include a metal body surrounded by a dielectric spacer, the metal body and the dielectric spacer positioned within an interlevel dielectric layer, wherein the metal body is electrically coupled to a silicide region below a lowermost portion of the metal body. | 09-25-2008 |
| 20080237867 | LOW CONTACT RESISTANCE METAL CONTACT - A semiconductor structure and methods of making the same. The semiconductor structure includes a substrate having a suicide region disposed above a doped region, and a metal contact extending through the silicide region and being in direct contact with the doped region. | 10-02-2008 |
| 20080239784 | HIGH DENSITY PLANAR MAGNETIC DOMAIN WALL MEMORY APPARATUS - A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures. | 10-02-2008 |
| 20080239785 | HIGH DENSITY PLANAR MAGNETIC DOMAIN WALL MEMORY APPARATUS - A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a write wire having a constriction therein, the constriction located at a point corresponding to the location of the plurality of discontinuities in the associated shift register structure. | 10-02-2008 |
| 20080243972 | HIGH DENSITY PLANAR MAGNETIC DOMAIN WALL MEMORY APPARATUS AND METHOD OF FORMING THE SAME - A magnetic domain wall memory apparatus with write/read capability includes a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location; a magnetic read element associated with each of the shift register structures; and a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a single write wire having a longitudinal axis substantially orthogonal to a longitudinal axis of each of the coplanar shift register structures. | 10-02-2008 |
| 20080254624 | METAL CAP FOR INTERCONNECT STRUCTURES - A structure and method of forming an improved metal cap for interconnect structures is described. The method includes forming an interconnect feature in an upper portion of a first insulating layer; deposing a dielectric capping layer over the interconnect feature and the first insulating layer; depositing a second insulating layer over the dielectric capping layer; etching a portion of the second insulating layer to form a via opening, wherein the via opening exposes a portion of the interconnect feature; bombarding the portion of the interconnect feature for defining a gauging feature in a portion of the interconnect feature; etching the via gauging feature for forming an undercut area adjacent to the interconnect feature and the dielectric capping layer; depositing a noble metal layer, the noble metal layer filling the undercut area of the via gauging feature to form a metal cap; and depositing a metal layer over the metal cap. | 10-16-2008 |
| 20080290519 | DUAL LINER CAPPING LAYER INTERCONNECT STRUCTURE - A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress. | 11-27-2008 |
| 20080293257 | DUAL LINER CAPPING LAYER INTERCONNECT STRUCTURE - A high tensile stress capping layer on Cu interconnects in order to reduce Cu transport and atomic voiding at the Cu/dielectric interface. The high tensile dielectric film is formed by depositing multiple layers of a thin dielectric material, each layer being under approximately 50 angstroms in thickness. Each dielectric layer is plasma treated prior to depositing each succeeding dielectric layer such that the dielectric cap has an internal tensile stress. | 11-27-2008 |
| 20080296728 | SEMICONDUCTOR STRUCTURE FOR FUSE AND ANTI-FUSE APPLICATIONS - A fuse/anti-fuse structure is provided in which programming of the anti-fuse is caused by an electromigation induced hillock that is formed adjacent to the fuse element. The hillock ruptures a thin diffusion barrier located on the sidewalls of the fuse element and the conductive material within the fuse element diffuses into the adjacent dielectric material. The fuse element includes a conductive material located within a line opening which includes a first diffusion barrier having a first thickness located on sidewalls and a bottom wall of the line opening. The anti-fuse element includes the conductive material located within a combined via and line opening which includes the first diffusion barrier located on sidewalls and a bottom wall of the combined via and line opening and a second diffusion barrier having a second thickness that is greater than the first thickness located on the first diffusion barrier. | 12-04-2008 |
| 20080308801 | STRUCTURE FOR STOCHASTIC INTEGRATED CIRCUIT PERSONALIZATION - A method of forming a stochastically based integrated circuit encryption structure includes forming a lower conductive layer over a substrate, forming a short prevention layer over the lower conductive layer, forming an intermediate layer over the short prevention layer, wherein the intermediate layer is characterized by randomly structured nanopore features. An upper conductive layer is formed over the random nanopore structured intermediate layer. The upper conductive layer is patterned into an array of individual cells, wherein a measurable electrical parameter of the individual cells has a random distribution from cell to cell with respect to a reference value of the electrical parameter. | 12-18-2008 |
| 20080315347 | PROVIDING GAPS IN CAPPING LAYER TO REDUCE TENSILE STRESS FOR BEOL FABRICATION OF INTEGRATED CIRCUITS - Fabricating an integrated circuit using a cap layer that includes one or more gaps or voids. The gaps or voids are provided prior to performing deposition and cure for an inter-layer dielectric (ILD) layer adjoining the cap layer. The gaps or voids reduce and prevent tensile stress buildup by allowing for stress relaxation, hence preventing catastrophic failure of the integrated circuit. | 12-25-2008 |
| 20080315426 | METAL CAP WITH ULTRA-LOW k DIELECTRIC MATERIAL FOR CIRCUIT INTERCONNECT APPLICATIONS - An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of about 3.0 or less. The dielectric material has at least one conductive material embedded therein. A noble metal cap is located directly on an upper surface of the at least one conductive region. The noble metal cap does not substantially extend onto an upper surface of the dielectric material that is adjacent to the at least one conductive region, and the noble cap material does not be deposited on the dielectric surface. A method fabricating such an interconnect structure utilizing a low temperature (about 300° C. or less) chemical deposition process is also provided. | 12-25-2008 |
| 20080315429 | METHOD FOR IMPROVING THE SELECTIVITY OF A CVD PROCESS - A method of forming a noble metal cap on a conductive material embedded in a dielectric material in an interconnect structure. The method includes the step of contacting (i) a conductive material having a bare upper surface partially embedded in a dielectric material and (ii) vapor of a noble metal containing compound, in the presence of carbon monoxide and a carrier gas. The contacting step is carried out at a temperature, pressure and for a length of time sufficient to produce a noble metal cap disposed directly on the upper surface of the conductive material without substantially extending into upper surface of the dielectric material or leaving a noble metal residue onto the dielectric material. | 12-25-2008 |
| 20090007037 | Hybrid Fully-Silicided (FUSI)/Partially-Silicided (PASI) Structures - Embodiments of the invention generally relate to methods, systems and design structures for semiconductor devices and more specifically to forming partially silicided and fully silicided structures. Fabricating the partially silicided and fully silicided structures may involve creating one or more gate stacks. A polysilicon layer of a first gate stack may be exposed and a first metal layer may be deposited thereon to create a partially silicided structure. Thereafter, a polysilicon layer of a second gate stack may be exposed and a second metal layer may be deposited thereon to form a fully silicided structure. In some embodiments, the polysilicon layers of one or more gate stacks may not be exposed, and resistors may be formed with the unsilicided polysilicon layers. | 01-01-2009 |
| 20090035954 | INTERCONNECT STRUCTURE WITH GRAIN GROWTH PROMOTION LAYER AND METHOD FOR FORMING THE SAME - In general, the present invention provides an interconnect structure and method for forming the same. This present invention discloses an interconnect structure includes a Cu seeding layer embedded between a diffusion barrier layer and a grain growth promotion layer. Specifically, under the present invention, a diffusion barrier layer is formed on a patterned inter-level dielectric layer. A (Cu) seeding layer is then formed on the diffusion barrier layer, and a grain growth promotion layer is formed on the seeding layer. Once the grain growth promotion layer is formed, post-processing steps (e.g., electroplating and chemical-mechanical polishing) are performed. | 02-05-2009 |
| 20090039512 | ELECTROMIGRATION RESISTANT INTERCONNECT STRUCTURE - A line trench is formed in a dielectric layer that may contain an interlayer dielectric material. A metal liner is formed on the sidewalls and the bottom surface of the line trench. A conductive metal is deposited within a remaining portion of the line trench at least up to a top surface of the dielectric layer and planarized to form a metal line in the line trench. The metal line is recessed by a recess etch below the top surface of the dielectric layer. A dielectric line cap or a metallic line cap is formed by deposition of a dielectric cap layer or a metallic cap layer, followed by planarization of the dielectric or metallic cap layer. The dielectric line cap or the metallic line cap applies a highly compressive stress on the underlying metal line, which increases electromigration resistance of the metal line. | 02-12-2009 |
| 20090057818 | METHODS AND SYSTEMS INVOLVING ELECTRICALLY PROGRAMMABLE FUSES - An electrically programmable fuse comprising a cathode member, an anode member, and a link member, wherein the cathode member, the anode member, and the link member each comprise one of a plurality of materials operative to localize induced electromigration in the programmable fuse. | 03-05-2009 |
| 20090072406 | INTERCONNECT STRUCTURE WITH IMPROVED ELECTROMIGRATION RESISTANCE AND METHOD OF FABRICATING SAME - An interconnect structure in which the electromigration resistance thereof is improved without introducing a gouging feature within the interconnect structure is provided. The interconnect structure includes a metallic interfacial layer that is at least horizontally present at the bottom of an opening located within a second dielectric material that is located atop a first dielectric material that includes a first conductive material embedded therein. The metallic interfacial layer does not form an alloy with an underlying conductive material that is embedded within the first dielectric material. In some embodiments of the present invention, the metallic interfacial layer is also present on exposed sidewalls of the second dielectric material that is located atop the first dielectric material. Atop the metallic interfacial layer there is present a diffusion barrier liner. In some embodiments, the diffusion barrier liner includes a lower layer of a metallic nitride and an upper layer of a metal. In accordance with the present invention, the metallic interfacial layer also does not form an alloy with any portion of the diffusion barrier liner. | 03-19-2009 |
| 20090079077 | INTERCONNECT STRUCTURE WITH A VIA GOUGING FEATURE ABSENT PROFILE DAMAGE TO THE INTERCONNECT DIELECTRIC AND METHOD OF FABRICATING SAME - An interconnect structure including a gouging feature at the bottom of the via openings and a method of forming the same, which does not introduce either damages caused by Ar sputtering into the dielectric material that includes the via and line openings, nor plating voids into the structure are provided. The method includes the uses of at least one infusion process that forms an infused surface region within a conductive material of a lower interconnect level. The infused surface region has a different etch rate as compared with the conductive material and thus in a subsequent etching process, the infused surface region can be selectively removed forming a gouging feature within the structure. | 03-26-2009 |
| 20090096108 | STRUCTURE AND METHODS OF FORMING CONTACT STRUCTURES - Methods and a structure. A method of forming contact structure includes depositing a silicide layer onto a substrate; depositing an electrically insulating layer over a first surface of the silicide layer; forming a via through the insulating layer extending to the first surface; depositing an electrically conductive layer covering a bottom and at least one vertical wall of the via; removing the conductive layer from the bottom; and filling the via with aluminum directly contacting the silicide layer. A structure includes: a silicide layer disposed on a substrate; an electrically insulating layer disposed over the silicide layer; an aluminum plug extending through the insulating layer and directly contacting the silicide layer; and an electrically conductive layer disposed between the plug and the insulating layer. Also included is a method where an aluminum layer grows selectively from a silicide layer and at least one sidewall of a trench. | 04-16-2009 |
| 20090108450 | INTERCONNECT STRUCTURE AND METHOD OF MAKING SAME - An interconnect structure and method of fabricating the same is provided. The interconnect structure is a highly reliable copper interconnect structure. The interconnect structure includes a planarized lower dielectric layer and a lower cap layer on the planarized lower dielectric layer. A copper material is formed in a trench of the planarized lower dielectric layer, below the lower cap layer. A lower liner extends into a pattern of the lower cap layer and contacts the copper layer. An upper dielectric layer is on the lower cap layer and a copper layer contacts the lower liner and is formed in a via of at least the lower cap layer. An upper liner is formed over the copper layer, sandwiching the copper layer between the lower liner and the upper liner. An upper copper layer is formed over the upper liner. | 04-30-2009 |
| 20090117360 | SELF-ASSEMBLED MATERIAL PATTERN TRANSFER CONTRAST ENHANCEMENT - A non-photosensitive polymeric resist containing at least two immiscible polymeric block components is deposited on the planar surface. The non-photosensitive polymeric resist is annealed to allow phase separation of immiscible components and developed to remove at least one of the at least two polymeric block components. Nanoscale features, i.e., features of nanometer scale, including at least one recessed region having a nanoscale dimension is formed in the polymeric resist. The top surface of the polymeric resist is modified for enhanced etch resistance by an exposure to an energetic beam, which allows the top surface of the patterned polymeric resist to become more resistant to etching processes and chemistries. The enhanced ratio of etch resistance between the two types of surfaces provides improved image contrast and fidelity between areas having the top surface and the at least one recessed region. | 05-07-2009 |
| 20090140428 | AIR GAP STRUCTURE HAVING PROTECTIVE METAL SILICIDE PADS ON A METAL FEATURE - A hard mask is formed on an interconnect structure comprising a low-k material layer and a metal feature embedded therein. A block polymer is applied to the hard mask layer, self-assembled, and patterned to form a polymeric matrix of a polymeric block component and containing cylindrical holes. The hard mask and the low-k material layer therebelow are etched to form cavities. A conductive material is plated on exposed metallic surfaces including portions of top surfaces of the metal feature to form metal pads. Metal silicide pads are formed by exposure of the metal pads to a silicon containing gas. An etch is performed to enlarge and merge the cavities in the low-k material layer. The metal feature is protected from the etch by the metal silicide pads. An interconnect structure having an air gap and free of defects to surfaces of the metal feature is formed. | 06-04-2009 |
| 20090148677 | HIGH ASPECT RATIO ELECTROPLATED METAL FEATURE AND METHOD - Disclosed are embodiments of an improved high aspect ratio electroplated metal structure (e.g., a copper or copper alloy interconnect, such as a back end of the line (BEOL) or middle of the line (MOL) contact) in which the electroplated metal fill material is free from seams and/or voids. Also, disclosed are embodiments of a method of forming such an electroplated metal structure by lining a high aspect ratio opening (e.g., a high aspect ratio via or trench) with a metal-plating seed layer and, then, forming a protective layer over the portion of the metal-plating seed layer adjacent to the opening sidewalls so that subsequent electroplating occurs only from the bottom surface of the opening up. | 06-11-2009 |
| 20090174075 | SIMULTANEOUS GRAIN MODULATION FOR BEOL APPLICATIONS - The invention is directed to an improved semiconductor structure, such that within the same insulating layer, Cu interconnects embedded within the same insulating level layer have a different Cu grain size than other Cu interconnects embedded within the same insulating level layer. | 07-09-2009 |
| 20090184400 | VIA GOUGING METHODS AND RELATED SEMICONDUCTOR STRUCTURE - Methods for via gouging and a related semiconductor structure are disclosed. In one embodiment, the method includes forming a via opening in a dielectric material, the via opening aligned with a conductor; forming a protective coating over the dielectric material and in the via opening; performing via gouging; and removing the protective coating over horizontal surfaces of the dielectric material. A semiconductor structure may include a via having an interface with a conductor, the interface including a three-dimensionally shaped region extending into and past a surface of the conductor, wherein an outer edge of the three-dimensionally shaped region is distanced from an outermost surface of the via. | 07-23-2009 |
| 20090189287 | NOBLE METAL CAP FOR INTERCONNECT STRUCTURES - An interconnect structure that includes a dielectric material having a dielectric constant of about 3.0 or less is provided. This low k dielectric material has at least one conductive material having an upper surface embedded therein. The dielectric material also has a surface layer that is made hydrophobic prior to the formation of the noble metal cap. The noble metal cap is located directly on the upper surface of the at least one conductive material. Because of the presence of the hydrophobic surface layer on the dielectric material, the noble metal cap does not substantially extend onto the hydrophobic surface layer of the dielectric material that is adjacent to the at least one conductive material and no metal residues from the noble metal cap deposition form on this hydrophobic dielectric surface. | 07-30-2009 |
| 20090194875 | HIGH PURITY Cu STRUCTURE FOR INTERCONNECT APPLICATIONS - A structure and method of forming a high purity copper structure for interconnect applications is described. The structure includes a patterned dielectric material and at least one Cu-containing conductive material having an upper surface embedded within the dielectric material; and a diffusion barrier and a noble metal liner separating the patterned dielectric material from the at least one Cu-containing conductive material; where the Cu-containing conductive material having high purity, C<10 ppm, Cl<10 ppm, S<10 ppm, and uniform impurity. A method of fabricating the interconnect structure is also described. The method includes providing an initial interconnect structure that includes a dielectric having at least one opening; forming a diffusion barrier layer on all exposed surfaces; forming a noble metal layer on the diffusion barrier layer; forming a Cu containing layer on the noble metal layer; and completely filling the at least one opening with the Cu containing layer. | 08-06-2009 |
| 20090194876 | INTERCONNECT STRUCTURE AND METHOD FOR Cu/ULTRA LOW k INTEGRATION - A semiconductor structure is provided that includes a lower interconnect level including a first dielectric material having at least one conductive feature embedded therein; a dielectric capping layer located on the first dielectric material and some, but not all, portions of the at least one conductive feature; and an upper interconnect level including a second dielectric material having at least one conductively filled via and an overlying conductively filled line disposed therein, wherein the conductively filled via is in contact with an exposed surface of the at least one conductive feature of the first interconnect level by an anchoring area. Moreover, the conductively filled via and conductively filled line of the inventive structure are separated from the second dielectric material by a single continuous diffusion barrier layer. As such, the second dielectric material includes no damaged regions in areas adjacent to the conductively filled line. A method of forming such an interconnect structure is also provided. | 08-06-2009 |
| 20090200668 | INTERCONNECT STRUCTURE WITH HIGH LEAKAGE RESISTANCE - An interconnect structure is provided in which the conductive feature (i.e., conductive material) is not coplanar with the upper surface of the dielectric material, but instead the conductive material is recessed below an upper surface of the dielectric material. In addition to being recessed below the upper surface of the dielectric material, the conductive material of the interconnect structure is surrounded on all sides (i.e., sidewall surfaces, upper surface and bottom surface) by a diffusion barrier material. Unlike prior art interconnect structures, the barrier material located on the upper surface of the recessed conductive material is located with an opening including the recessed conductive material. | 08-13-2009 |
| 20090212433 | STRUCTURE AND PROCESS FOR METALLIZATION IN HIGH ASPECT RATIO FEATURES - A high aspect ratio metallization structure is provided in which a noble metal-containing material is present at least within a lower portion of a contact opening located in a dielectric material and is in direct contact with a metal semiconductor alloy located on an upper surface of a material stack of at least one semiconductor device. In one embodiment, the noble metal-containing material is plug located within the lower region of the contact opening and an upper region of the contact opening includes a conductive metal-containing material. The conductive metal-containing material is separated from plug of noble metal-containing material by a bottom walled portion of a U-shaped diffusion barrier. In another embodiment, the noble metal-containing material is present throughout the entire contact opening. | 08-27-2009 |
| 20090218691 | BILAYER METAL CAPPING LAYER FOR INTERCONNECT APPLICATIONS - The invention provides semiconductor interconnect structures that have improved reliability and technology extendibility. In the present invention, a second metallic capping layer is located on a surface of a first metallic cap layer which is, in turn, located on a surface of the conductive feature embedded within a first dielectric material. Both the first and second metallic capping layers are located beneath an opening, e.g., a via opening, the is present within an overlying second dielectric material. The second metallic capping layer protects the first dielectric capping layer from being removed (either completely or partially) during subsequent processing steps. Interconnect structures including via gouging features as well as non-via gouging features are disclosed. The present invention provides methods of fabricating such semiconductor interconnect structures. | 09-03-2009 |
| 20090218695 | LOW CONTACT RESISTANCE METAL CONTACT - A semiconductor structure and methods of making the same. The semiconductor structure includes a substrate having a silicide region disposed above a doped region, and a metal contact extending through the silicide region and being in direct contact with the doped region. | 09-03-2009 |
| 20090250815 | SURFACE TREATMENT FOR SELECTIVE METAL CAP APPLICATIONS - Interconnect structures in which a noble metal-containing cap layer is present directly on a non-recessed surface of a conductive material which is embedded within a low k dielectric material are provided. It has been determined that by forming a hydrophobic surface on a low k dielectric material prior to metal cap formation provides a means for controlling the selective formation of the metal cap directly on the non-recessed surface of a conductive material. That is, the selective formation of the metal cap directly on the non-recessed surface of a conductive material is enhanced since the formation rate of the metal cap on the non-recessed surface of a conductive material is greater than on the hydrophobic surface of the low k dielectric material. It is observed that the hydrophobic surface may be a result of treating a damaged surface of the dielectric material with a silylating agent prior to the selective formation of the noble metal cap or, as a result of forming a hydrophobic polymeric layer on the surface of the dielectric material prior to the selective deposition of the noble metal cap. The hydrophobic polymeric layer typically includes atoms of Si, C and O. | 10-08-2009 |
| 20090269929 | NON-PLASMA CAPPING LAYER FOR INTERCONNECT APPLICATIONS - The present invention provides an interconnect structure which has a high leakage resistance and substantially no metallic residues and no physical damage present at an interface between the interconnect dielectric and an overlying dielectric capping layer. The interconnect structure of the invention also has an interface between each conductive feature and the overlying dielectric capping layer that is substantially defect-free. The interconnect structure of the invention includes a non-plasma deposited dielectric capping layer which is formed utilizing a process including a thermal and chemical-only pretreatment step that removes surface oxide from atop each of the conductive features as well as metallic residues from atop the interconnect dielectric material. Following this pretreatment step, the dielectric capping layer is deposited. | 10-29-2009 |
| 20090278228 | DESIGN STRUCTURE FOR INTERCONNECT STRUCTURE CONTAINING VARIOUS CAPPING MATERIALS FOR ELECTRICAL FUSE AND OTHER RELATED APPLICATIONS - A design structure is provided for interconnect structures containing various capping materials for electrical fuses and other related applications. The structure includes a first interconnect structure having a first interfacial structure and a second interconnect structure adjacent to the first structure. The second interconnect structure has second interfacial structure different from the first interfacial structure. | 11-12-2009 |
| 20090278229 | EFFICIENT INTERCONNECT STRUCTURE FOR ELECTRICAL FUSE APPLICATIONS - A semiconductor structure is provided that includes an interconnect structure and a fuse structure located in different areas, yet within the same interconnect level. The interconnect structure has high electromigration resistance, while the fuse structure has a lower electromigration resistance as compared with the interconnect structure. The fuse structure includes a conductive material embedded within an interconnect dielectric in which the upper surface of the conductive material has a high concentration of oxygen present therein. A dielectric capping layer is located atop the dielectric material and the conductive material. The presence of the surface oxide layer at the interface between the conductive material and the dielectric capping layer degrades the adhesion between the conductive material and the dielectric capping layer. As such, when current is provided to the fuse structure electromigration of the conductive material occurs and over time an opening is formed in the conductive material blowing the fuse element. | 11-12-2009 |
| 20090278258 | INTERCONNECT STRUCTURE WITH A MUSHROOM-SHAPED OXIDE CAPPING LAYER AND METHOD FOR FABRICATING SAME - An interconnect structure is provided that includes a dielectric material | 11-12-2009 |
| 20090278260 | REDUNDANCY DESIGN WITH ELECTRO-MIGRATION IMMUNITY AND METHOD OF MANUFACTURE - An IC interconnect for high direct current (DC) that is substantially immune to electro-migration (EM) damage, a design structure of the IC interconnect and a method of manufacture of the IC interconnect is provided. The structure has electro-migration immunity and redundancy of design, which includes a plurality of wires laid out in parallel and each of which are coated with a liner material. Two adjacent of the wires are physically contacted to each other. | 11-12-2009 |
| 20090280636 | METHODS OF FABRICATING INTERCONNECT STRUCTURES CONTAINING VARIOUS CAPPING MATERIALS FOR ELECTRICAL FUSE AND OTHER RELATED APPLICATIONS - Methods are provided for fabricating interconnect structures containing various capping materials for electrical fuses and other related applications. The method includes forming a first interconnect structure having a first interfacial structure and forming a second interconnect structure adjacent to the first structure. The second interconnect structure is formed with a second interfacial structure different from the first interfacial structure of the first interconnect structure. | 11-12-2009 |
| 20090289365 | STRUCTURE AND PROCESS FOR CONDUCTIVE CONTACT INTEGRATION - A semiconductor structure including a highly reliable high aspect ratio contact structure in which key-hole seam formation is eliminated is provided. The key-hole seam formation is eliminated in the present invention by providing a densified noble metal-containing liner within a high aspect ratio contact opening that is present in a dielectric material. The densified noble metal-containing liner is located atop a diffusion barrier and both those elements separate the conductive material of the inventive contact structure from a conductive material of an underlying semiconductor structure. The densified noble metal-containing liner of the present invention is formed by deposition of a noble metal-containing material having a first resistivity and subjecting the deposited noble metal-containing material to a densification treatment process (either thermal or plasma) that decreases the resistivity of the deposited noble metal-containing material to a lower resistivity. | 11-26-2009 |
| 20090297759 | Stress Locking Layer for Reliable Metallization - Recrystallization and grain growth of metal, such as Cu, is achieved at higher anneal temperatures of 150° C. to 400° C., for example, for short anneal times of five to sixty minutes by forming a metal stress locking layer on the Cu before anneal and chemical-mechanical polishing. The stress locking layer extends the elastic region of the Cu by suppressing atom diffusion to the free surface, resulting in near zero tensile stress at room temperature after anneal. Stress voiding, which creates reliability problems, is thereby avoided. Improved grain size and texture are also achieved. The stress locking layer is removed after anneal by chemical-mechanical polishing leaving the Cu interconnect with low stress and improved grain size and texture. | 12-03-2009 |
| 20090298281 | INTERCONNECT STRUCTURE WITH HIGH LEAKAGE RESISTANCE - An interconnect structure is provided in which the conductive feature (i.e., conductive material) is not coplanar with the upper surface of the dielectric material, but instead the conductive material is recessed below an upper surface of the dielectric material. In addition to being recessed below the upper surface of the dielectric material, the conductive material of the interconnect structure is surrounded on all sides (i.e., sidewall surfaces, upper surface and bottom surface) by a diffusion barrier material. Unlike prior art interconnect structures, the barrier material located on the upper surface of the recessed conductive material is located with an opening including the recessed conductive material. | 12-03-2009 |
| 20090309226 | Interconnect Structure for Electromigration Enhancement - An interconnect structure having enhanced electromigration resistance is provided in which a lower portion of a via opening includes a multi-layered liner. The multi-layered liner includes, from a patterned surface of a dielectric material outwards, a diffusion barrier, a multi-material layer and a metal-containing hard mask. The multi-material layer includes a first material layer comprised of residue from an underlying dielectric capping layer, and a second material layer comprised of residue from an underlying metallic capping layer. The present invention also provides a method of fabricating such an interconnect structure which includes the multi-layered liner within a lower portion of a via opening formed within a dielectric material. | 12-17-2009 |
| 20090321933 | Structure to Facilitate Plating Into High Aspect Ratio Vias - Improved high aspect ratio vias and techniques for the formation thereof are provided. In one aspect, a method of fabricating a copper plated high aspect ratio via is provided. The method comprises the following steps. A high aspect ratio via is etched in a dielectric layer. A diffusion barrier layer is deposited into the high aspect ratio via and over one or more surfaces of the dielectric layer. A copper layer is deposited over the diffusion barrier layer. A ruthenium layer is deposited over the copper layer. The high aspect ratio via is filled with copper plated onto the ruthenium layer. A copper plated high aspect ratio via formed by this method is also provided. | 12-31-2009 |
| 20100012950 | CRACKSTOP STRUCTURES AND METHODS OF MAKING SAME - An integrated circuit chip and a method of fabricating an integrated circuit chip. The integrated circuit chip includes: a set of wiring levels stacked from a first wiring level to a last wiring level; and a respective void in each wiring level of two or more wiring levels of the set wiring levels, each respective void extending in a continuous ring parallel and proximate to a perimeter of the integrated circuit chip, a void of a higher wiring level stacked directly over but not contacting a void of a lower wiring level, the respective voids forming a crack stop. | 01-21-2010 |
| 20100013043 | CRACKSTOP STRUCTURES AND METHODS OF MAKING SAME - An integrated circuit chip and a method of fabricating an integrated circuit chip. The integrated circuit chip includes: a continuous first stress ring proximate to a perimeter of the integrated circuit chip, respective edges of the first stress ring parallel to respective edges of the integrated circuit chip; a continuous second stress ring between the first stress ring and the perimeter of the integrated circuit chip, respective edges the second stress ring parallel to respective edges of the integrated circuit chip, the first and second stress rings having opposite internal stresses; a continuous gap between the first stress ring and the second stress ring; and a set of wiring levels from a first wiring level to a last wiring level on the substrate. | 01-21-2010 |
| 20100038782 | NITROGEN-CONTAINING METAL CAP FOR INTERCONNECT STRUCTURES - An interconnect structure is provided that has enhanced electromigration reliability without degrading circuit short yield, and improved technology extendibility. The inventive interconnect structure includes a dielectric material having a dielectric constant of about 3.0 or less. The dielectric material has at least one conductive material embedded therein. A nitrogen-containing noble metal cap is located predominately (i.e., essentially) on an upper surface of the at least one conductive region. The nitrogen-containing noble metal cap does not extend onto an upper surface of the dielectric material. In some embodiments, the nitrogen-containing noble metal cap is self-aligned to the embedded conductive material, while in other embodiments some portion of the nitrogen-containing noble metal cap extends onto an upper surface of a diffusion barrier that separates the at least one conductive material from the dielectric material. A method of fabricating such an interconnect structure utilizing a low temperature (about 200° C. or less) chemical deposition process is also provided. | 02-18-2010 |
| 20100038783 | METAL CAP FOR BACK END OF LINE (BEOL) INTERCONNECTS, DESIGN STRUCTURE AND METHOD OF MANUFACTURE - A structure is provided with a metal cap for back end of line (BEOL) interconnects that substantially eliminates electro-migration (EM) damage, a design structure and a method of manufacturing the IC. The structure includes a metal interconnect formed in a dielectric material and a metal cap selective to the metal interconnect. The metal cap includes RuX, where X is at Boron, Phosphorous or a combination of Boron and Phosphorous. | 02-18-2010 |
| 20100038784 | REDUNDANT BARRIER STRUCTURE FOR INTERCONNECT AND WIRING APPLICATIONS, DESIGN STRUCTURE AND METHOD OF MANUFACTURE - A redundant diffusion barrier structure and method of fabricated is provided for interconnect and wiring applications. The structure can also be a design structure. The structure includes a first liner lining at least one of a trench and a via and a second liner deposited over the first liner. The second liner comprises RuX. X is at least one of Boron and Phosphorous. The structure comprises a metal deposited on the second liner in the at least one trench and via to form a metal interconnect or wiring. | 02-18-2010 |
| 20100084766 | SURFACE REPAIR STRUCTURE AND PROCESS FOR INTERCONNECT APPLICATIONS - Semiconductor interconnect structures including a surface-repair material, e.g., a noble metal or noble metal alloy, that fills hollow-metal related defects located within a conductive material are provided. The filling of the hollow-metal related defects with the surface repair material improves the electromigration (EM) reliability of the structure as well as decreasing in-line defect related yield loss. | 04-08-2010 |
| 20100084767 | DISCONTINUOUS/NON-UNIFORM METAL CAP STRUCTURE AND PROCESS FOR INTERCONNECT INTEGRATION - An interconnect structure including a noble metal-containing cap that is present at least on some portion of an upper surface of at least one conductive material that is embedded within an interconnect dielectric material is provided. In one embodiment, the noble metal-containing cap is discontinuous, e.g., exists as nuclei or islands on the surface of the at least one conductive material. In another embodiment, the noble metal-containing cap has a non-uniform thickness across the surface of the at least one conductive material. | 04-08-2010 |
| 20100143649 | HIGH ASPECT RATIO ELECTROPLATED METAL FEATURE AND METHOD - Disclosed are embodiments of an improved high aspect ratio electroplated metal structure (e.g., a copper or copper alloy interconnect, such as a back end of the line (BEOL) or middle of the line (MOL) contact) in which the electroplated metal fill material is free from seams and/or voids. Also, disclosed are embodiments of a method of forming such an electroplated metal structure by lining a high aspect ratio opening (e.g., a high aspect ratio via or trench) with a metal-plating seed layer and, then, forming a protective layer over the portion of the metal-plating seed layer adjacent to the opening sidewalls so that subsequent electroplating occurs only from the bottom surface of the opening up. | 06-10-2010 |
| 20100176512 | STRUCTURE AND METHOD FOR BACK END OF THE LINE INTEGRATION - An improved semiconductor structure consists of interconnects in an upper interconnect level connected to interconnects in a lower interconnect level through use of a conductive protrusion located at the bottom of a via opening in an upper interconnect level, the conductive protrusion extends upward from bottom of the via opening and into the via opening. The improved interconnect structure with the conductive protrusion between the upper and lower interconnects enhances overall interconnect reliability. | 07-15-2010 |
| 20100176514 | INTERCONNECT WITH RECESSED DIELECTRIC ADJACENT A NOBLE METAL CAP - The invention comprises a copper interconnect structure that includes a noble metal cap with dielectric immediately adjacent the copper/noble metal cap interface recessed from the noble metal cap. | 07-15-2010 |
| 20100237460 | METHODS AND SYSTEMS INVOLVING ELECTRICALLY PROGRAMMABLE FUSES - An electrically programmable fuse comprising a cathode member, an anode member, and a link member, wherein the cathode member, the anode member, and the link member each comprise one of a plurality of materials operative to localize induced electromigration in the programmable fuse. | 09-23-2010 |
| 20100264543 | INTERCONNECT STRUCTURE - An interconnect structure and methods for forming semiconductor interconnect structures are disclosed. In one embodiment, the interconnect structure includes: a substrate including a first liner layer and a first metal layer thereover; a dielectric barrier layer over the first metal layer and the substrate; an inter-level dielectric layer over the dielectric barrier layer; a via extending between the inter-level dielectric layer, the dielectric barrier layer, and the first metal layer, the via including a second liner layer and a second metal layer thereover; and a diffusion barrier layer located between the second liner layer and the first metal layer, wherein a portion of the diffusion barrier layer is located under the dielectric barrier layer. | 10-21-2010 |
| 20100295181 | REDUNDANT METAL BARRIER STRUCTURE FOR INTERCONNECT APPLICATIONS - A redundant metal diffusion barrier is provided for an interconnect structure which improves the reliability and extendibility of the interconnect structure. The redundant metal diffusion barrier layer is located within an opening that is located within a dielectric material and it is between a diffusion barrier layer and a conductive material which are also present within the opening. The redundant diffusion barrier includes a single layered or multilayered structure comprising Ru and a Co-containing material including pure Co or a Co alloy including at least one of N, B and P. | 11-25-2010 |
| 20110024909 | BILAYER METAL CAPPING LAYER FOR INTERCONNECT APPLICATIONS - The invention provides semiconductor interconnect structures that have improved reliability and technology extendibility. In the present invention, a second metallic capping layer is located on a surface of a first metallic cap layer which is, in turn, located on a surface of the conductive feature embedded within a first dielectric material. Both the first and second metallic capping layers are located beneath an opening, e.g., a via opening, the is present within an overlying second dielectric material. The second metallic capping layer protects the first dielectric capping layer from being removed (either completely or partially) during subsequent processing steps. Interconnect structures including via gouging features as well as non-via gouging features are disclosed. The present invention provides methods of fabricating such semiconductor interconnect structures. | 02-03-2011 |
| 20110031623 | INTERCONNECT STRUCTURE AND METHOD FOR Cu/ULTRA LOW k INTEGRATION - A semiconductor structure is provided that includes a lower interconnect level including a first dielectric material having at least one conductive feature embedded therein; a dielectric capping layer located on the first dielectric material and some, but not all, portions of the at least one conductive feature; and an upper interconnect level including a second dielectric material having at least one conductively filled via and an overlying conductively filled line disposed therein, wherein the conductively filled via is in contact with an exposed surface of the at least one conductive feature of the first interconnect level by an anchoring area. Moreover, the conductively filled via and conductively filled line of the inventive structure are separated from the second dielectric material by a single continuous diffusion barrier layer. As such, the second dielectric material includes no damaged regions in areas adjacent to the conductively filled line. A method of forming such an interconnect structure is also provided. | 02-10-2011 |
| 20110092031 | EFFICIENT INTERCONNECT STRUCTURE FOR ELECTRICAL FUSE APPLICATIONS - A semiconductor structure is provided that includes an interconnect structure and a fuse structure located in different areas, yet within the same interconnect level. The interconnect structure has high electromigration resistance, while the fuse structure has a lower electromigration resistance as compared with the interconnect structure. The fuse structure includes a conductive material embedded within an interconnect dielectric in which the upper surface of the conductive material has a high concentration of oxygen present therein. A dielectric capping layer is located atop the dielectric material and the conductive material. The presence of the surface oxide layer at the interface between the conductive material and the dielectric capping layer degrades the adhesion between the conductive material and the dielectric capping layer. As such, when current is provided to the fuse structure electromigration of the conductive material occurs and over time an opening is formed in the conductive material blowing the fuse element. | 04-21-2011 |
| 20110092067 | AIR GAP STRUCTURE HAVING PROTECTIVE METAL SILICIDE PADS ON A METAL FEATURE - A hard mask is formed on an interconnect structure comprising a low-k material layer and a metal feature embedded therein. A block polymer is applied to the hard mask layer, self-assembled, and patterned to form a polymeric matrix of a polymeric block component and containing cylindrical holes. The hard mask and the low-k material layer therebelow are etched to form cavities. A conductive material is plated on exposed metallic surfaces including portions of top surfaces of the metal feature to form metal pads. Metal silicide pads are formed by exposure of the metal pads to a silicon containing gas. An etch is performed to enlarge and merge the cavities in the low-k material layer. The metal feature is protected from the etch by the metal silicide pads. An interconnect structure having an air gap and free of defects to surfaces of the metal feature is formed. | 04-21-2011 |
