Chih-Chang
Chih-Chang Chang, Hsinchu TW
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20090046488 | INVERTER CIRCUIT - An inverter circuit ( | 02-19-2009 |
Chih-Chang Cheng, Taipei City TW
Patent application number | Description | Published |
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20100002542 | ULTRASONIC DISTANCE-MEASURING SENSOR ASSEMBLY AND ULTRASONIC DISTANCE-MEASURING SENSOR THEREOF - An ultrasonic distance-measuring sensor assembly and an ultrasonic distance-measuring sensor thereof are disclosed. The ultrasonic distance-measuring sensor includes at least two piezoelectric actuators and a member. The member includes a side wall, at least two vibration generating/receiving surfaces and a partition. The vibration generating/receiving surfaces accommodate the piezoelectric actuators as sources. The side wall surrounds the vibration generating/receiving surfaces. The partition is disposed between the vibration generating/receiving surfaces and includes a gap. The gap is disposed between the vibration sending/receiving surfaces. | 01-07-2010 |
Chih-Chang Cheng, Hsinchu City TW
Patent application number | Description | Published |
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20110241114 | HIGH VOLTAGE MOS TRANSISTOR - A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS) and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. One portion of the second well surrounds the source and the other portion of the second well extends laterally from the first portion in the first well. | 10-06-2011 |
20120091529 | HIGH VOLTAGE RESISTOR - Provided is a semiconductor device. The semiconductor device includes a resistor and a voltage protection device. The resistor has a spiral shape. The resistor has a first portion and a second portion. The voltage protection device includes a first doped region that is electrically coupled to the first portion of the resistor. The voltage protection device includes a second doped region that is electrically coupled to the second portion of the resistor. The first and second doped regions have opposite doping polarities. | 04-19-2012 |
20120119265 | SOURCE TIP OPTIMIZATION FOR HIGH VOLTAGE TRANSISTOR DEVICES - The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region. | 05-17-2012 |
20120126334 | BREAKDOWN VOLTAGE IMPROVEMENT WITH A FLOATING SUBSTRATE - The present disclosure provides a semiconductor device that includes a substrate having a resistor element region and a transistor region, a floating substrate in the resistor element region of the substrate, an epitaxial layer disposed over the floating substrate, and an active region defined in the epitaxial layer, the active region surrounded by isolation structures. The device further includes a resistor block disposed over an isolation structure, and a dielectric layer disposed over the resistor block, the isolation structures, and the active region. A method of fabricating such semiconductor devices is also provided. | 05-24-2012 |
20120132995 | STACKED AND TUNABLE POWER FUSE - The present disclosure provides a semiconductor device that includes a transistor including a substrate, a source, a drain, and a gate, and a fuse stacked over the transistor. The fuse includes an anode contact coupled to the drain of the transistor, a cathode contact, and a resistor coupled to the cathode contact and the anode contact via a first Schottky diode and a second Schottky diode, respectively. A method of fabricating such semiconductor devices is also provided. | 05-31-2012 |
20120139041 | HIGH SIDE GATE DRIVER DEVICE - The present disclosure provides a semiconductor device. The semiconductor device includes: a drift region having a first doping polarity formed in a substrate; a doped extension region formed in the drift region and having a second doping polarity opposite the first doping polarity, the doped extension region including a laterally-extending component; a dielectric structure formed over the drift region, the dielectric structure being separated from the doped extension region by a portion of the drift region; a gate structure formed over a portion of the dielectric structure and a portion of the doped extension region; and a doped isolation region having the second doping polarity, the doped isolation region at least partially surrounding the drift region and the doped extension region. | 06-07-2012 |
20120280361 | HIGH VOLTAGE RESISTOR WITH BIASED-WELL - Provided is a high voltage semiconductor device. The semiconductor device includes a doped well located in a substrate that is oppositely doped. The semiconductor device includes a dielectric structure located on the doped well. A portion of the doped well adjacent the dielectric structure has a higher doping concentration than a remaining portion of the doped well. The semiconductor device includes an elongate polysilicon structure located on the dielectric structure. The elongate polysilicon structure has a length L. The portion of the doped well adjacent the dielectric structure is electrically coupled to a segment of the elongate polysilicon structure that is located away from a midpoint of the elongate polysilicon structure by a predetermined distance that is measured along the elongate polysilicon structure. The predetermined distance is in a range from about 0*L to about 0.1*L. | 11-08-2012 |
20120299096 | HIGH VOLTAGE AND ULTRA-HIGH VOLTAGE SEMICONDUCTOR DEVICES WITH INCREASED BREAKDOWN VOLTAGES - A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages. | 11-29-2012 |
20130161689 | INSULATED GATE BIPOLAR TRANSISTOR STRUCTURE HAVING LOW SUBSTRATE LEAKAGE - A high voltage laterally diffused metal-oxide-semiconductor (HV LDMOS) device, particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate having at least one highly doped buried portion, a first doped well grown over the substrate, a gate structure formed on the first well, a source and a drain formed on either side of the gate structure, and a second doped well having a U-shaped cross section formed in the first well. A portion of the drain is formed over the first well outside of the second well. | 06-27-2013 |
20130207187 | INSULATED GATE BIPOLAR TRANSISTOR STRUCTURE HAVING LOW SUBSTRATE LEAKAGE - A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate. | 08-15-2013 |
20130240984 | TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A manufacture includes a doped layer, a body structure over the doped layer, a trench defined in the doped layer, an insulator partially filling the trench, and a first conductive feature buried in, and separated from the doped layer and the body structure by, the insulator. The doped layer has a first type doping. The body structure has an upper surface and includes a body region. The body region has a second type doping different from the first type doping. The trench has a bottom surface. The first conductive feature extends from a position substantially leveled with the upper surface of the body structure toward the bottom surface of the trench. The first conductive feature overlaps the doped layer for an overlapping distance, and the overlapping distance ranging from 0 to 2 μm. | 09-19-2013 |
20130256833 | TRIPLE WELL ISOLATED DIODE AND METHOD OF MAKING - A triple well isolate diode including a substrate having a first conductivity type and a buried layer formed in the substrate, where the buried layer has a second conductivity type. The triple well isolated diode including an epi-layer formed over the substrate and the buried layer, where the epi-layer has the first conductivity type. The triple well isolated diode including a first well formed in the epi-layer, where the first well has the second conductivity type, a second well formed in the epi-layer, where the second well has the first conductivity type and surrounds the first well, a third well formed in the epi-layer, where the third well has the second conductivity type and surrounds the second well. The triple well isolated diode including a deep well formed in the epi-layer, where the deep well has the first conductivity type and extends beneath the first well. | 10-03-2013 |
20140035035 | INSULATED GATE BIPOLAR TRANSISTOR STRUCTURE HAVING LOW SUBSTRATE LEAKAGE - A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate. | 02-06-2014 |
20140054695 | High Side Gate Driver Device - The present disclosure provides a semiconductor device. The semiconductor device includes: a drift region having a first doping polarity formed in a substrate; a doped extension region formed in the drift region and having a second doping polarity opposite the first doping polarity, the doped extension region including a laterally-extending component; a dielectric structure formed over the drift region, the dielectric structure being separated from the doped extension region by a portion of the drift region; a gate structure formed over a portion of the dielectric structure and a portion of the doped extension region; and a doped isolation region having the second doping polarity, the doped isolation region at least partially surrounding the drift region and the doped extension region. | 02-27-2014 |
20140057407 | High Voltage Resistor - Provided is a semiconductor device. The semiconductor device includes a resistor and a voltage protection device. The resistor has a spiral shape. The resistor has a first portion and a second portion. The voltage protection device includes a first doped region that is electrically coupled to the first portion of the resistor. The voltage protection device includes a second doped region that is electrically coupled to the second portion of the resistor. The first and second doped regions have opposite doping polarities. | 02-27-2014 |
20140235028 | High Voltage Resistor with Pin Diode Isolation - Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions. | 08-21-2014 |
20140312414 | TRANSISTOR AND METHOD OF MANUFACTURING THE SAME - A method of forming a manufacture includes forming a trench in a doped layer. The trench has an upper portion and a lower portion, and a width of the upper portion is greater than that of the lower portion. A first insulating layer is formed along sidewalls of the lower portion of the trench and a bottom surface of the trench. A gate dielectric layer is formed along sidewalls of the upper portion of the trench. A first conductive feature is formed along sidewalls of the gate dielectric layer. A second insulating layer covering the first conductive feature and the first insulating layer is formed, and a second conductive feature is formed along sidewalls of the second insulating layer and a bottom surface of the second insulating layer. | 10-23-2014 |
20140322889 | HIGH VOLTAGE RESISTOR WITH BIASED-WELL - Provided is a high voltage semiconductor device. The semiconductor device includes a doped well located in a substrate that is oppositely doped. The semiconductor device includes a dielectric structure located on the doped well. A portion of the doped well adjacent the dielectric structure has a higher doping concentration than a remaining portion of the doped well. The semiconductor device includes an elongate polysilicon structure located on the dielectric structure. The elongate polysilicon structure has a length L. The portion of the doped well adjacent the dielectric structure is electrically coupled to a segment of the elongate polysilicon structure that is located away from a midpoint of the elongate polysilicon structure by a predetermined distance that is measured along the elongate polysilicon structure. The predetermined distance is in a range from about 0*L to about 0.1*L. | 10-30-2014 |
20140327075 | HIGH VOLTAGE AND ULTRA-HIGH VOLTAGE SEMICONDUCTOR DEVICES WITH INCREASED BREAKDOWN VOLTAGES - A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages. | 11-06-2014 |
20150061011 | MOS TRANSISTOR - A novel MOS transistor including a well region, a gate dielectric layer, a gate electrode, a source region and a drain region is provided. The well region of a first conductivity type extends into a semiconductor substrate. The gate dielectric layer is located over the well region. The gate electrode is located over the gate dielectric layer. The source region of a second conductivity type opposite to the first conductivity type and a drain region of the second conductivity type are located in the well region and on opposite sides of the gate electrode. The gate dielectric layer has a first portion and a second portion respectively closest to the source region and the drain region. The thickness of the second portion is greater than that of the first portion, so as to raise breakdown voltage and to maintain current simultaneously. | 03-05-2015 |
20150069507 | MOS TRANSISTOR AND METHOD FOR MANUFACTURING MOS TRANSISTOR - A novel MOS transistor, which includes a source region, a drain region, a channel region, an isolation region, a drift region, a gate dielectric layer, a gate electrode and a field plate, is provided. The gate electrode has a first portion and a second portion. The first portion of a first conductivity type is located over the channel region and has a width equal to or greater than a distance of the gate electrode overlapped with the channel region. The second portion is un-doped and located over the isolation region. Accordingly, the MOS transistor allows higher process freedom saves production cost, as well as improves reliability. | 03-12-2015 |
20150072496 | METHOD OF MAKING AN INSULATED GATE BIPOLAR TRANSISTOR STRUCTURE - A method for fabricating a high voltage semiconductor transistor includes growing a first well region over a substrate having a first conductivity type, the first well region having a second type of conductivity. First, second and third portions of a second well region having the first type of conductivity are doped into the first well region. A first insulating layer is grown in and over the first well portion within the second well region. A second insulating layer is grown on the substrate over the third portion of the second well region. An anti-punch through region is doped into the first well region. A gate structure is formed on the substrate. A source region is formed in the first portion of the second well region on an opposite side of the gate structure from the first insulating layer. A drain region is formed in the first well region. | 03-12-2015 |
20150076565 | ULTRAHIGH-VOLTAGE SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The disclosure provides an ultrahigh-voltage (UHV) semiconductor structure including a first electrical portion, a second electrical portion and a bridged conductive layer. In which, the first electrical portion and the second electrical portion are isolated, and directly connected to each other through the bridged conductive layer. Thus, there is no current leakage occurring in the UHV semiconductor structure disclosed in this disclosure. And a method for manufacturing the UHV semiconductor structure also provides herein. | 03-19-2015 |
20150187936 | QUASI-VERTICAL STRUCTURE HAVING A SIDEWALL IMPLANTATION FOR HIGH VOLTAGE MOS DEVICE - A semiconductor device includes a buried layer in a substrate, the buried layer having a first dopant type. The semiconductor device further includes a first layer over the buried layer, the first layer having the first dopant type. The semiconductor device further includes at least one first well in the first layer, the at least one first well having a second dopant type. The semiconductor device further includes an implantation region in a sidewall of the first layer, the implantation region having the second dopant type, wherein the implantation region is below the at least one first well. The semiconductor device further includes a metal electrode extending from the buried layer to a drain contact, wherein the metal electrode is insulated from the first layer and the at least one first well by an insulation layer. | 07-02-2015 |
20150263164 | HIGH VOLTAGE AND ULTRA-HIGH VOLTAGE SEMICONDUCTOR DEVICES WITH INCREASED BREAWKDOWN VOLTAGES - A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages. | 09-17-2015 |
Chih-Chang Cheng, Hsinchu TW
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20100219463 | QUASI-VERTICAL STRUCTURE FOR HIGH VOLTAGE MOS DEVICE - A semiconductor device provides a high breakdown voltage and a low turn-on resistance. The device includes: a substrate; a buried n+ layer disposed in the substrate; an n-epi layer disposed over the buried n+ layer; a p-well disposed in the n-epi layer; a source n+ region disposed in the p-well and connected to a source contact on one side; a first insulation layer disposed on top of the p-well and the n-epi layer; a gate disposed on top of the first insulation layer; and a metal electrode extending from the buried n+ layer to a drain contact, wherein the metal electrode is insulated from the n-epi layer and the p-well using by a second insulation layer. | 09-02-2010 |
20110163376 | HIGH VOLTAGE DEVICES AND METHODS OF FORMING THE HIGH VOLTAGE DEVICES - A high voltage (HV) device includes a well region of a first dopant type disposed in a substrate. A first well region of a second dopant type is disposed in the well region of the first dopant type. An isolation structure is at least partially disposed in the well region of the first dopant type. A first gate electrode is disposed over the isolation structure and the first well region of the second dopant type. A second well region of the second dopant type is disposed in the well region of the first dopant type. The second well region of the second dopant type is spaced from the first well region of the second dopant type. A second gate electrode is disposed between and over the first well region of the second dopant type and the second well region of the second dopant type. | 07-07-2011 |
20130240982 | QUASI-VERTICAL STRUCTURE FOR HIGH VOLTAGE MOS DEVICE - A semiconductor device which includes a buried layer having a first dopant type disposed in a substrate. The semiconductor device further includes a second layer having the first dopant type over the buried layer, wherein a dopant concentration of the buried layer is higher than a dopant concentration of the second layer. The semiconductor device further includes a first well of a second dopant type disposed in the second layer and a first source region of the first dopant type disposed in the first well and connected to a source contact on one side. The semiconductor device further includes a gate disposed on top of the well and the second layer and a metal electrode extending from the buried layer to a drain contact, wherein the metal electrode is insulated from the second layer and the first well by an insulation layer. | 09-19-2013 |
20140054708 | Stacked and Tunable Power Fuse - The present disclosure provides a semiconductor device that includes a transistor including a substrate, a source, a drain, and a gate, and a fuse stacked over the transistor. The fuse includes an anode contact coupled to the drain of the transistor, a cathode contact, and a resistor coupled to the cathode contact and the anode contact via a first Schottky diode and a second Schottky diode, respectively. A method of fabricating such semiconductor devices is also provided. | 02-27-2014 |
20140197488 | METHOD OF FORMING HIGH VOLTAGE DEVICE - A method of forming a device includes forming a buried well region of a first dopant type in a substrate. A well region of the first dopant type is formed over the buried well region. A first well region of a second dopant type is formed between the well region of the first dopant type and the buried well region of the first dopant type. A second well region of the second dopant type is formed in the well region of the first dopant type. An isolation structure is formed at least partially in the well region of the first dopant type. A first gate electrode is formed over the isolation structure and the second well region of the second dopant type. | 07-17-2014 |
20140284706 | QUASI-VERTICAL STRUCTURE HAVING A SIDEWALL IMPLANTATION FOR HIGH VOLTAGE MOS DEVICE - A semiconductor device includes a buried layer having a first dopant type in a substrate. The semiconductor device includes a first layer having the first dopant type over the buried layer. The semiconductor device includes at least one first well of a second dopant type disposed in the first layer. The semiconductor device includes an implantation region of the second dopant type in a sidewall of the first layer, wherein the implantation region is below the at least one first well. The semiconductor device includes a first source region disposed in the at least one first well; and at least one gate disposed on top of the first well and the first layer. The semiconductor device includes a metal electrode extending from the buried layer to a drain contact, wherein the metal electrode is insulated from the first layer and the at least one first well by an insulation layer. | 09-25-2014 |
Chih-Chang Chou, Taipei TW
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20080230430 | WATERPROOF PART - A waterproof part including a top case, a bottom case and at least one pin is provided. The top case has at least one first through hole. The bottom case has at least one second through hole that corresponds to the first through hole. The pin includes a conductive bolt, a pad, and an elastic conductive component. The conductive bolt is disposed in the second through hole and fastened to the bottom case. The pad is disposed in the first through hole and has at least one first fastening element. The pad is fastened to the top case by the first fastening element. The elastic conductive component is tightly disposed between the conductive bolt and the pad so as to connect to the conductive bolt and the pad electrically. | 09-25-2008 |
20090083622 | HANDWRITING RECORDING APPARATUS - A handwriting recording apparatus is provided. The handwriting recording apparatus includes a pen-shaped housing, a timer unit, a compass, a microprocessing unit, and a storage unit. The compass is equipped to the pen-shaped housing for detecting a moving direction of a motion of the pen-shaped housing. The timer unit is equipped inside the pen-shaped housing for recording a time data related to the motion of the pen-shaped housing. The microprocessing unit is equipped inside the pen-shaped housing for obtaining a motion vector of the pen-shaped housing according to the moving direction and the time data, and comparing the motion vector with a word data to generate a text file. The storage unit is equipped inside the pen-shaped housing for storing the text file so as to provide the text file for an external computer system to process or use. | 03-26-2009 |
Chih-Chang Hsieh, Hsinchu TW
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20130343130 | NAND FLASH BIASING OPERATION - A charge storage memory is configured in a NAND array, and includes NAND strings coupled to bit lines via string select switches and includes word lines. A controller is configured to produce a bias for performing an operation on a selected cell of the NAND array. The bias includes charging the bit line while the string select switches are closed, such as to not introduce noise into the strings caused by such bit line charging. The semiconductor body regions in memory cells that are on both sides of the memory cells in the NAND strings that are coupled to a selected word line are coupled to reference voltages such that they are pre-charged while the word lines of the strings in the array are transitioned to various voltages during the operation. | 12-26-2013 |
20140198570 | PROGRAMMING MULTIBIT MEMORY CELLS - A multiple bits per cell memory is operated by applying a one-pass, multiple-level programming, using a single pulse sequence one time (or in one-pass), such as an incremental pulse program sequence, with program verify steps for multiple target program levels, to program multiple bits per cell in a plurality of memory cells. Using these techniques, the number of program pulses required, and the time required for programming the data can be reduced. As a result, an improvement in programming throughput and a reduction in disturbance conditions are achieved. Variants of the one-pass, multiple-level programming operation can be adopted for a variety of memory cell types, memory architectures, programming speeds, and data storage densities. | 07-17-2014 |
20140198576 | PROGRAMMING TECHNIQUE FOR REDUCING PROGRAM DISTURB IN STACKED MEMORY STRUCTURES - A programming bias technique is described for programming a stacked memory structure with a plurality of layers of memory cells. The technique includes the controller circuitry responsive to a program instruction to program data in target cells in a stack of cells at a particular multibit address. The circuitry is configured to use an assignment of cells in the stack of cells to a plurality of sets of cells, and to iteratively execute a set program operation selecting each of the plurality of sets in sequence. Each iteration includes applying inhibit voltages to all of the cells in others of the plurality of sets. Also, each set of layers includes subsets of one or two, and there are at least two layers from other sets separating each of the subsets in one set. | 07-17-2014 |
Chih-Chang Hsieh, Taipei TW
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20120281481 | THERMALLY ASSISTED DIELECTRIC CHARGE TRAPPING FLASH - A memory device includes an array of dielectric charge trapping structures memory cells including word lines and bit lines. Control circuitry is coupled to the array arranged to control read, program and erase operations. A controller is arranged with supporting circuitry thermally annealing charge trapping structures in the memory cells in the array. Word line drivers and word line termination circuits can be used to induce current flow on the word lines to induce heat for the annealing. The thermal annealing can be applied interleaved with normal operations for recover from cycling damage. Also, the thermally annealing can be applied during mission functions like erase, to improve performance of the function. | 11-08-2012 |
Chih-Chang Hsu, Taipei TW
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20110078995 | YARN MANUFACTURING METHOD AND A MIXING YARN - A yarn manufacturing method is provided. The method includes providing a plurality of raw fibers, modifying at least one of the raw fibers to form at least one modified fiber, and spinning the raw fibers and the at least one modified fiber into a mixed yarn. A mixed yarn spun from the raw fibers and the modified fiber is also provided, wherein the modified fiber is modified from the raw fiber. | 04-07-2011 |
20110081547 | NATURAL QUICK-DRYING YARN AND A MANUFACTURING METHOD THEREOF - A natural quick-drying yarn and a manufacturing method thereof are provided. The natural quick-drying yarn is made of a plurality of natural fibers. Hydrophobic agents are disposed between the natural fibers and on the surface of the natural fibers. Hydrophilic agents are disposed outside the natural fibers. The method includes immersing natural fibers in a solution of hydrophobic agent to dispose the hydrophobic agent between the natural fibers and on the surface of the natural fibers, drying the hydrophobic agent solution immersed natural fibers, immersing the natural fibers in a solution of hydrophilic agent to dispose the hydrophilic agent outside the natural fibers, and drying the hydrophilic agent solution immersed natural fibers. | 04-07-2011 |
20110146832 | PROCESS OF MANUFACTURING ULTRA-SOFT YARN AND FABRIC THEREOF - A process of manufacturing a ultra-soft yarn includes wrapping a roving material with a yarn by a low twist-multiplier of about 1˜4, wherein the roving material is drawn at a draw ratio preferably between 1 and 10, wherein the ultra-soft yarn has a fluffy structure, which can provide better softness, draping property, and hand feel to users. Fabric including the ultra-soft yarn is also provided. | 06-23-2011 |
20110265440 | Manufacturing Methods for Indigo Fleck Fancy Yarn and Indigo Fleck Fancy Fabric - Manufacturing methods for an indigo fleck fancy yarn and for an indigo fleck fancy fabric are provided. The indigo fleck fancy yarn manufacturing method includes providing an original indigo yarn, oxidizing the original indigo yarn, reducing the oxidized indigo yarn, soap washing the reduced indigo yarn, and drying the soap washed indigo yarn to form an indigo fleck fancy yarn. The indigo fleck fancy yarn is an indigo yarn having irregular white area. The indigo fleck fancy fabric manufacturing method includes providing a plurality of indigo fleck fancy yarns made by the above indigo fleck fancy yarn manufacturing method, and using the indigo fleck fancy yarn to make an indigo fleck fancy fabric. | 11-03-2011 |
Chih-Chang Hsu, Osaka JP
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20100158000 | TRANSMITTING APPARATUS AND TRANSMITTING METHOD - To transmit multimedia data in such a manner that is adaptive to the transmission, capability of a receiving apparatus and/or to the congestion state of a network. In a transmitting apparatus ( | 06-24-2010 |
Chih-Chang Hsu, Taipei City TW
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20100275567 | MULTI-LAYER YARN STRUCTURE AND METHOD FOR MAKING THE SAME - A multi-layer yarn structure and a method for making the same are provided. The multi-layer yarn structure includes a core layer, a layer of noncircular fibers, and an outer layer. The core layer has a plurality of hydrophobic fibers. The noncircular fibers surround the core layer to form a middle layer. The outer layer surrounds the middle layer and has a plurality of hydrophilic fibers. The method spins different fibers into multi-layer yarn for making textile with a soft, smooth, and thick feel. By utilizing inherent characteristics of the multi-layer yarn structure, the textile may regulate moisture released from the human body and keep the body dry and comfort. | 11-04-2010 |
20130108795 | Method of Manufacturing Natural, Breathable and Quick Drying Fabric | 05-02-2013 |
Chih-Chang Huang, Anding Shiang TW
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20090122257 | Eyeglasses structure - The present invention relates to an eyeglasses structure having an eyeglass body and temples, wherein tenons are formed on both sides of said eyeglass body, each said tenon is provided with tenon feet on which engaging portions are provided on the end edges; a connection portion is provided on each temple, which is formed by the fitting of two opposite casings; retaining recesses with big arc edge variation corresponding to the shape of the engaging portions on the tenon feet being provided on the casings, a slot being formed after said retaining recesses provided on the casings are oppositely fitted together so as to correspondingly engage with said tenons. According to this structure, the slot having retaining recesses with bigger arc edge variation can be engaged with the tenons of the eyeglass body so as to form a stable combination. | 05-14-2009 |
Chih-Chang Huang, Tainan City TW
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20130335696 | ASSEMBLY OF OPTICAL LENS AND EYEGLASS FRAME - The assembly mainly includes a fastener mounting into and locked between a middle part of the eyeglass frame and a middle part of the optical lens, where the eyeglass frame and the optical lens mounted with each other. Moreover, a stopping plate is mounted into the eyeglass frame at the position corresponding to the fastener. By the stopping plate locked with the fastener, the fastener will not separate from the eyeglass frame. Therefore the connection between the eyeglass frame and the optical lens becomes more firmly and stably by the fastener. | 12-19-2013 |
Chih-Chang Hung, Hsinchu City TW
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20150262827 | SEMICONDUCTOR DEVICE WITH SIDEWALL PASSIVATION AND METHOD OF MAKING - One or more semiconductor devices are provided. The semiconductor device comprises a gate body, a conductive prelayer over the gate body, at least one inhibitor film over the conductive prelayer and a conductive layer over the at least one inhibitor film, where the conductive layer is tapered so as to have a top portion width that is greater than the bottom portion width. One or more methods of forming a semiconductor device are also provided, where an etching process is performed to form a tapered opening such that the tapered conductive layer is formed in the tapered opening. | 09-17-2015 |
20150263132 | BARC-ASSISTED PROCESS FOR PLANAR RECESSING OR REMOVING OF VARIABLE-HEIGHT LAYERS - An IC device manufacturing process effectuates a planar recessing of material that initially varies in height across a substrate. The method includes forming a bottom anti-reflective coating (BARC), baking to induce cross-linking in the BARC, CMP to remove a first portion of the BARC and form a planar surface, then plasma etching to effectuate a planar recessing of the BARC. The plasma etching can have a low selectivity between the BARC and the material being recessed, whereby the BARC and the material are recessed simultaneously. Any of the material above a certain height is removed. Structures that are substantially below that certain height can be protected from contamination and left intact. The method can be particularly effective when an abrasive used during CMP forms ester linkages with the BARC. | 09-17-2015 |
Chih-Chang Kao, New Taipei TW
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20150277522 | ETHERNET POWER SOURCE EQUIPMENT - An Ethernet PSE includes a processor, a plurality of POE ports, a plurality of port modules, a switch module, a detection circuit, and a power supply module. Each of the port modules supplies power to a PD via each of the POE ports. The switch module connects the processor to or disconnects the processor from each of the port modules according to control signals so that the processor can selectively communicate with each of the port modules. The detection circuit determines whether each of the POE ports is connected to the PD or not, outputting a detection signal corresponding to each of the POE ports. The power supply module supplies power to the processor, the plurality of port modules, the switch module, and the detection circuit. The processor controls operation states of the plurality of port modules and the switch module according to the detection signals. | 10-01-2015 |
Chih-Chang Ko, Taipei Hsien TW
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20100073109 | Filtering Device and Related Wireless Communication Receiver - A filtering device includes an isolation substrate including a first plane and a second plane, a micro-strip line deposited on the first plane of the isolation substrate for transmitting signals, and a ground metal layer deposited on the second plane of the isolation substrate for providing grounding. A meander-shaped resonating cavity is formed in an area of the ground metal layer corresponding to an area of the micro-strip line, for generating a rejection band on the micro-strip line. | 03-25-2010 |
Chih-Chang Lai, Tai Chung County TW
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20090213109 | DRIVING METHOD FOR A DISPLAY - The invention discloses a driving method for a display. The method includes the following steps: providing a pixels structure; receiving a plurality of frames; driving the (2n−1)th scan line and the (2n)th scan line by turns while receiving the number of odd frame; driving (2n)th scan line and (2n−1)th scan line by turns while receiving the number of even frame; adjusting the voltage of the Vcom according to pixels voltage value which are the voltage to be written into the pixels by odd data lines and even data lines while the pixels structure receiving the number of odd frame and the number of the even frame. | 08-27-2009 |
20100259700 | LIQUID CRYSTAL DISPLAY DEVICE AND DRIVING METHOD THEREFOR - A liquid crystal display device includes a plurality of pixel units. Each of the pixel units includes a first thin film transistor and a second thin film transistor, a reflective sheet, and a storage capacitor. The channel width/length ratio of the first thin film transistor and the channel width/length ratio of the second thin film transistor are both larger than 12/5. The reflective sheet is disposed adjacent to the first thin film transistor and the second thin film transistor to reflect ambient light. The storage capacitor is formed at a position overlapping the reflective sheet and has a capacitance of lager than 1 pF. | 10-14-2010 |
20110102344 | PORTABLE ELECTRONIC DEVICE AND TABLET PERSONAL COMPUTER - A portable electronic device including a main body and a wireless input unit is provided. The main body has a display surface and an accommodating portion opposite the display surface. The accommodating portion defines an accommodating space substantially parallel to the display surface. The wireless input unit is placed inside the accommodating space and capable of being extracted from the accommodating space. The wireless input unit is separate from the main body. The wireless input unit includes a touch panel, a pattern layer, and a control circuit. The touch panel has an operation surface and a back surface opposite the operation surface. The pattern layer is disposed on the back surface of the touch panel and has a plurality of control area patterns. The control circuit is disposed on the touch panel. | 05-05-2011 |
20110134072 | RESISTIVE TOUCH PANEL AND DRIVING METHOD THEREFOR - A resistive touch panel includes a first substrate, a second substratem and a driving circuit. A first conductive layer is disposed on the first substrate and includes a first, a second, a third, and a fourth corners which are different from each other. A first, a second, a third, and a fourth conducting wires are electrically connected to the first, second, third, and fourth corners, respectively. The second substrate is disposed parallel to the first substrate. A second conductive layer is disposed on the second substrate and faces the first conductive layer. A fifth conducting wire is electrically connected to a first side of the second conductive layer while a sixth conducting wire is electrically connected to a second side of the second conductive layer. The driving circuit is electrically connected to the first, second, third, fourth, fifth, and sixth conducting wires. | 06-09-2011 |
20110157255 | SYSTEM AND METHOD FOR MODULATING BACKLIGHT - A backlight modulation system includes a light source module, an image mapping unit, a histogram analysis unit, a backlight dimming unit, and an image reconstruction unit. An active display area of a panel is divided into multiple illumination areas. The image mapping unit performs an RGB-to-YUV transformation to acquire an original brightness factor for each pixel. The histogram analysis unit sums up the amount of pixels reaching a preset ratio in each illumination area to acquire reference brightness for each illumination area. The backlight dimming unit calculates out a dimming ratio and a reset brightness model according to the reference brightness. The image reconstruction unit resets original brightness factor of each pixel into an output brightness factor according to the reset brightness model, and outputs an image for an illumination area according to the output brightness factor and input image data. | 06-30-2011 |
20110169759 | TOUCH-SENSING DISPLAY DEVICE - A touch-sensing display device includes a display panel, a touch panel, a driver unit, and a flexible printed circuit board. The touch panel is disposed on the display panel, and the driver unit is disposed on the display panel to provide driving signals and drive the display panel and the touch panel. The flexible printed circuit board connects the display panel to a system main board. | 07-14-2011 |
20110199330 | SURFACE CAPACITIVE TOUCH PANEL AND ITS FABRICATION METHOD - A surface capacitive touch panel includes a transparent substrate, a decorative layer, a metal trace pattern layer, and a passivation layer. The decorative layer and the capacitive sensing electrode layer are formed on the transparent substrate. The metal trace pattern layer is formed on the capacitive sensing electrode layer. The decorative layer is disposed at a position substantially overlapping the metal trace pattern layer. | 08-18-2011 |
20110199332 | CAPACITIVE TOUCH PANEL AND ELECTRODE STRUCTURE THEREOF - A transparent capacitive touch panel comprising a transparent substrate, a transparent cover lens and a transparent adhesive layer is provided, wherein a first transparent electrode layer and a second transparent electrode layer are disposed on the transparent cover lens and the transparent substrate respectively. The transparent adhesive layer is used to bind the first transparent electrode layer and second transparent electrode layer in order to combine the transparent cover lens and the transparent substrate disposed in parallel. Thereby, the manufacturing process of the transparent capacitive touch panel is simplified, and the manufacturing cost of the same is lowered. | 08-18-2011 |
Chih-Chang Lai, Zhubei City TW
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20120068947 | TOUCH DETECTION METHOD AND TOUCH DETECTOR USING THE SAME - A method for double click detection includes the following steps. Firstly whether first event is detected is determined, if so, first corresponding position is obtained, a period counting is triggered, and first flag is set. Then whether the period ends is judged; if not and the first flag exists, a counter is incremented and second flag is set when first ending event is detected; if not and the second flag exists, second corresponding position is obtained and third flag is set when second event is detected; if not and the third flag exists, the counter is incremented when second ending event is detected; if so, a double click event is determined when the incremented value is greater than a threshold and a distance between the first and the second positions is smaller a threshold. | 03-22-2012 |
Chih-Chang Lai, Tai Ping City TW
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20130241875 | CAPACITIVE TOUCH PANEL - A transparent capacitive touch panel comprising a transparent substrate, a transparent cover lens and a transparent adhesive layer is provided, wherein a first transparent electrode layer and a second transparent electrode layer are disposed on the transparent cover lens and the transparent substrate respectively. The transparent adhesive layer is used to bind the first transparent electrode layer and second transparent electrode layer in order to combine the transparent cover lens and the transparent substrate disposed in parallel. Thereby, the manufacturing process of the transparent capacitive touch panel is simplified, and the manufacturing cost of the same is lowered. | 09-19-2013 |
20140198078 | CAPACITIVE TOUCH PANEL - A transparent capacitive touch panel comprising a transparent substrate, a transparent cover lens and a transparent adhesive layer is provided, wherein a first transparent electrode layer and a second transparent electrode layer are disposed on the transparent cover lens and the transparent substrate respectively. The transparent adhesive layer is used to bind the first transparent electrode layer and second transparent electrode layer in order to combine the transparent cover lens and the transparent substrate disposed in parallel. Thereby, the manufacturing process of the transparent capacitive touch panel is simplified, and the manufacturing cost of the same is lowered. | 07-17-2014 |
20140354575 | TOUCH-SENSING DISPLAY DEVICE - A touch-sensing display device includes a display panel, a touch panel, a driver unit, and a flexible printed circuit board. The touch panel is disposed on the display panel, and the driver unit is disposed on the display panel to provide driving signals and drive the display panel and the touch panel. The flexible printed circuit board connects the display panel to a system main board. | 12-04-2014 |
Chih-Chang Lai, Tai Ping City, Tai Chung County TW
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20150103044 | CAPACITIVE TOUCH PANEL - A transparent capacitive touch panel comprising a transparent substrate, a transparent cover lens and a transparent adhesive layer is provided, wherein a first transparent electrode layer and a second transparent electrode layer are disposed on the transparent cover lens and the transparent substrate respectively. The transparent adhesive layer is used to bind the first transparent electrode layer and second transparent electrode layer in order to combine the transparent cover lens and the transparent substrate disposed in parallel. Thereby, the manufacturing process of the transparent capacitive touch panel is simplified, and the manufacturing cost of the same is lowered. | 04-16-2015 |
Chih-Chang Lin, Taichung City TW
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20090284217 | SOLAR POWER CHARGING DEVICE WITH SELF-PROTECTION FUNCTION - A solar power charging device with a self-protection function is provided, which includes a solar cell, a rechargeable battery, and a diode. The solar cell defines an open-circuit voltage Voc and an operating voltage Vop, in which the Voc is slightly higher than the Vop. The rechargeable battery defines a battery voltage, an operating voltage of load Vload, and a maximum charging voltage Vf, in which the Vf is substantially equal to the V | 11-19-2009 |
Chih-Chang Lin, Hsinchu TW
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20130190482 | METHOD FOR ONE-STEP PURIFICATION OF RECOMBINANT HELICOBACTER PYLORI NEUTROPHIL-ACTIVATING PROTEIN - is closely associated with chronic gastritis, peptic ulcer disease, and gastric adenocarcinoma. | 07-25-2013 |
Chih-Chang Shih, Hsinchu County TW
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20150332648 | PIXEL STRUCTURE, PIXEL ARRAY, AND DISPLAY PANEL - A pixel structure is provided. The pixel structure includes an active device, a first pixel electrode, a second pixel electrode, and a conductive line. The first pixel electrode is electrically connected to the active device. The second pixel electrode and the first pixel electrode are electrically insulated. The conductive line is located below the first pixel electrode and the second pixel electrode. The active device is electrically connected to the first pixel electrode through the conductive line. The conductive line is coupled to the second pixel electrode to form a coupling capacitance. | 11-19-2015 |
Chih-Chang Wang, Changhua Hsien TW
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20090214321 | SELF-DRILLING SCREW AND METHOD OF MAKING THE SAME - A self-drilling screw includes a head portion, a shank portion having an externally threaded section, and a drilling portion opposite to the head portion. The drilling portion has a main section and a tip section, two flutes extending helically through the main and tip sections, and two lands extending helically between the flutes. Each of the lands has a tapered face extending in the tip section and between the flutes, and a drilling edge formed on one end of the tapered face. | 08-27-2009 |
Chih-Chang Wei, Zhubei City TW
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20140131551 | PROXIMITY SENSOR AND OPERATING METHOD THEREOF - A proximity sensor includes a proximity sensing unit and a signal processing unit. The proximity sensing unit detects whether an object to be detected is close by to obtain a measured value. The signal processing unit compares the measured value with an initial noise cross-talk value to determine whether the initial noise cross-talk value should be updated. If the determined result of the signal processing unit is no, the signal processing unit compares the measured value with a default value to determine whether the object to be detected is located in a detection range of the proximity sensing unit. | 05-15-2014 |
Chih-Chang Wei, New Taipei City TW
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20130285510 | METHOD FOR FABRICATING PIEZOELECTRIC COMPOSITE MATERIAL AND PIEZOELECTRIC POWER GENERATING DEVICE - The invention relates to a method for fabricating piezoelectric composite material comprising steps of mixing a piezoelectric ceramic powder, an adhesive, a cross-linking agent, a lubricant and a plasticizer to form a slurry; extruding the slurry to form a piezoelectric ceramic green fiber; sintering the piezoelectric ceramic green fiber to form the piezoelectric ceramic fiber; arranging the piezoelectric ceramic fiber in a mold according to a predetermined volumetric content; and adding a polymer into the mode to form a polymer matrix of piezoelectric composite material. A piezoelectric power generating device including a piezoelectric power generating element made of the piezoelectric composite material is also provided. | 10-31-2013 |
20140124494 | CAR INTERIOR COMPARTMENT HEATER - A heater used in car interior compartment includes a framework and a heating module. The framework includes a first base and a second base arranged in interval with the first base. The heating module is provided between the first base and the second base. The heating module includes a PTC heating component, a thermal conduction glue, a pair of electrode plate, a insulation thermal conduction glue, and a pair of thermal diffusion body. The electrode plate is stuck to both sides of the PTC heating component by the thermal conduction glue. Each thermal diffusion body connects each electrode plate in an insulation way by the insulation thermal conduction glue, and the heat generating and the anti electricity leakage effect of the heater can be improved. | 05-08-2014 |
20140124499 | ELECTRIC HEATING APPARATUS WITH WATERPROOF MECHANISM - An electric heating apparatus with a waterproof mechanism includes a hollow tube, a positive temperature coefficient (PTC) heating module and a waterproof glue. The hollow tube has a closed end and an open end; the PTC heating module has a pair of electrode plates, a PTC heating unit included between the pair of electrode plates and a conductive terminal coupled to each electrode plate, and the pair of electrode plates and the PTC heating unit are passed into the hollow tube from the open end; the waterproof glue is filled to seal the open end, and each conductive terminal is exposed from the waterproof glue; so that the waterproof glue sealing the open end of the hollow tube can prevent water vapor from entering into the hollow tube. | 05-08-2014 |
20140124500 | INSULATED HEATER - An insulated heater includes a heating unit, two thermal diffusion units and a heat conduction glue. The heating unit includes two electrode plates and at least one PTC heating plate. The PTC heating plate is sandwiched between two electrode plates. The thermal diffusion unit includes a corrugated metal fin and two heat conduction plates, and the corrugated metal fin is sandwiched between two heat conduction plates. Each thermal diffusion unit is attached to one of the electrode plates via the heat conduction plate, and the heat conduction glue is spread between each electrode plate and the thermal diffusion unit attached to the electrode plate. The thermal resistance between the thermal diffusion unit and the electrode plate can decrease by directly binding the thermal diffusion unit and the electrode plate with the heat conduction glue. | 05-08-2014 |
20140126896 | ELECTRICAL HEATING DEVICE AND EQUIPMENT WITH PLUGGABLE HEATING MODULE - An electrical heating device with pluggable heating module includes a box body ( | 05-08-2014 |