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Chien-Ting
Chien-Ting Chen, Taoyuan County TW
| Patent application number | Description | Published |
|---|---|---|
| 20110234467 | PLANAR BI-DIRECTIONAL RADIATION ANTENNA - A planar bi-directional radiation antenna including a substrate, a first reflecting element, an antenna body, a second reflecting element and a third reflecting element is provided. The first reflecting element is concaved inwards to form a first notch in a first surface. The antenna body is located inside the first notch, and is symmetrical to a predetermined direction with the first reflecting element. The second reflecting element is concaved inwards to form a second notch in a second surface. The configuration of the first notch and the second notch is correspondingly disposed along a vertical projection plane with respect to the substrate. The third reflecting element is opposite to the antenna body along the predetermined direction, and covers an opening of the first notch, so that the antenna generates two beams, wherein the two beams have an angle relative to the substrate, so as to achieve a bi-directional radiation effect. | 09-29-2011 |
Chien-Ting Chen, Taichung TW
| Patent application number | Description | Published |
|---|---|---|
| 20100168064 | NOVEL HYDROPHILIC DERIVATIVES OF 2-ARYL-4-QUINOLONES AS ANTICANCER AGENTS - 2-aryl-4-quinolones are converted into phosphates by reacting with tetrabenzyl pyrophosphate to form dibenzyl phosphates thereof, which are then subject to hydrogenation to replace dibenzyl groups with H, followed by reacting with Amberlite IR-120 (Na+ form) to form disodium salts. The results of preliminary screening revealed that these phosphates showed significant anti-cancer activity. A novel intermediate, 2-selenophene 4-quinolone and Λ/, Λ/-dialkylaminoalkyl derivatives of 2-phenyl-4-quinolones are also synthesized. These novel intermediates exhibited significant anticancer activities. | 07-01-2010 |
Chien-Ting Huang, New Taipei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110179306 | Data Read Method for Flash Memory - The invention provides a data read method. In one embodiment, a flash memory comprises a plurality of pages, and predetermined information is written into each of the pages of the flash memory. First, a target address of the flash memory is read according to a source read voltage to obtain source data and a source error correction code. When error bits of the source data cannot be corrected according to the source error correction code, the predetermined information corresponding to the source data is read from the flash memory according to the source read voltage to obtain correction information. The source data and the source error correction code are then amended according to the difference between the predetermined information and the correction information to obtain an amended data and an amended error correction code. Error bits of the amended data are then corrected according to the amended error correction code. | 07-21-2011 |
Chien-Ting Lai, Miao-Li County TW
| Patent application number | Description | Published |
|---|---|---|
| 20100123865 | LIQUID CRYSTAL DISPLAY PANEL AND METHOD FOR MANUFACTURING THE SAME - An exemplary liquid crystal display panel includes a substrate and first conductive wires. The first conductive wires are arranged at a surface of the substrate. Each of the first conductive wires includes a plurality of first connecting portions, a plurality of second connecting portions and a conductive portion with a plurality of conductive particles. The conductive portion is sandwiched between the first connecting portions and the second connecting portions, thus electrically connecting the first connecting portions to the second connecting portions. A method for manufacturing the liquid crystal display panel is also provided. | 05-20-2010 |
| 20110031512 | THIN FILM TRANSISTOR SUBSTRATE - A thin film transistor substrate, capable of being assembled, is attached to a filter substrate to provide a semi-finished liquid crystal display panel. The thin film transistor substrate includes a base substrate with thin film transistors formed thereon, wiring assemblies formed on the substrate and electrically connected to the corresponding thin film transistors selectively, metal sheets formed on the base substrate, a protection layer formed on the thin film transistors, the wiring assemblies, and the metal sheets, and a buffer module formed on the protection layer. The buffer module is positioned above a projection of a cutting line onto the base substrate, and the surplus materials of the filter substrate are removed along the cutting line. | 02-10-2011 |
Chien-Ting Lin, Santa Fe Springs, CA US
| Patent application number | Description | Published |
|---|---|---|
| 20120001038 | TRIPOD STRUCTURE OF STAND - Provided is a tripod structure of a stand, which is combined on a central post of the stand and allows the leg units of the stand to be folded, and includes: an upper tripod unit having a central post orifice and at least three leg unit connection parts evenly arranged at the outer periphery of the central post and formed with at least an accessory part, wherein the upper tripod unit is fastened at a preset location of the central post of the stand via the central post orifice, and each leg unit of the stand is respectively hinged with each leg unit connection part; and a lower tripod unit having a post plug and at least three moveable support rod connection parts evenly arranged at the outer periphery of the post plug, and each moveable support rod connection part is correspondingly formed with a leg unit buckling part and formed with at least an accessory part, wherein the post plug is installed at the distal end of the central post of the stand, and hinged to the leg unit and the moveable support rod connection part through a support rod, such that the leg units can be folded and respectively buckled with each corresponding leg unit buckling part. | 01-05-2012 |
Chien-Ting Lin, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20080237809 | METHOD OF FABRICATING HYBRID ORIENTATION SUBSTRATE AND STRUCTURE OF THE SAME - A method of fabricating a hybrid orientation substrate is described. A silicon substrate with a first orientation having a silicon layer with a second orientation directly thereon is provided, and then a stress layer is formed on the silicon layer. A trench is formed between a first portion and a second portion of the silicon layer through the stress layer and into the substrate. The first portion of the silicon layer is amorphized. A SPE process is performed to recrystallize the amorphized first portion of the silicon layer to be a recrystallized layer with the first orientation. An annealing process is performed at a temperature lower than 1200° C. to convert a surface layer of the second portion of the silicon layer to a strained layer. The trench is filled with an insulating material after the SPE process or the annealing process, and the stress layer is removed. | 10-02-2008 |
| 20090242997 | METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE AND STRUCTURE OF STATIC RANDOM ACCESS MEMORY - A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening. | 10-01-2009 |
| 20110031558 | GATE STRUCTURE OF SEMICONDUCTOR DEVICE - A gate structure of a semiconductor device includes a first low resistance conductive layer, a second low resistance conductive layer, and a first type conductive layer disposed between and directly contacting sidewalls of the first low resistance conductive layer and the second low resistance conductive layer. | 02-10-2011 |
| 20110034019 | METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE - A method for fabricating a semiconductor structure is disclosed. A substrate with a first transistor having a first dummy gate and a second transistor having a second dummy gate is provided. The conductive types of the first transistor and the second transistor are different. The first and second dummy gates are simultaneously removed to form respective first and second openings. A high-k dielectric layer, a second type conductive layer and a first low resistance conductive layer are formed on the substrate and fill in the first and second openings, with the first low resistance conductive layer filling up the second opening. The first low resistance conductive layer and the second type conductive layer in the first opening are removed. A first type conductive layer and a second low resistance conductive layer are then formed in the first opening, with the second low resistance conductive layer filling up the first opening. | 02-10-2011 |
Chien-Ting Lin, Taipei TW
| Patent application number | Description | Published |
|---|---|---|
| 20100155047 | SYSTEMS AND METHODS TO DISSIPATE HEAT IN AN INFORMATION HANDLING SYSTEM - In a particular embodiment, a system to dissipate heat in an information handling system includes a first heat-generating component adapted to process first data and a second heat-generating component adapted to process second data. The system also includes a cooling fluid guide including an electroactive material. The cooling fluid guide is adapted to change from a first shape to a second shape, in response to receiving a trigger voltage or in response to no longer receiving the trigger voltage. The system also includes a controller adapted to detect a data load processed at the second heat-generating component and, in response to detecting the data load, to cause the trigger voltage to be received at, or no longer received at, the cooling fluid guide. The cooling fluid guide is adapted to direct an increased portion of cooling fluid toward the first heat-generating component when the cooling fluid guide is in a form of the second shape, as compared to the first shape. | 06-24-2010 |
Chien-Ting Yeh, Linkou Shiang TW
| Patent application number | Description | Published |
|---|---|---|
| 20090172205 | METHOD AND SYSTEM FOR ENABLING A SIDESHOW DEVICE TO RETRIEVE SYSTEM INFORMATION FROM A COMPUTING DEVICE - A method and system for enabling an auxiliary system to retrieve the system information from a computing device are disclosed. Specifically, one embodiment of the present invention sets forth a method, which includes the steps of requesting for the system information from an embedded controller of the computing device through a first bi-directional data bus if the computing device is shut down, requesting for the system information from the computing device through the first bidirectional bus during the boot-up sequence of the computing device, and requesting for the system information from the computing device through a general purpose input/output (GPIO) after the computing device completes the boot-up sequence. | 07-02-2009 |