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Chien-Min

Chien-Min Chang, Taipei City TW

Patent application numberDescriptionPublished
20090110947APPARATUS AND METHOD OF DECORATING A SURFACE OF A WORKPIECE AND DECORATED PART - A method of decorating a surface of a workpiece includes the step of positioning a decorating film over the surface, wherein the decorating film has a first side and an opposite second side with a decorating pattern facing the surface. The decorating film is then fitted tightly on the surface by applying negative pressure therebetween. Next, the decorating pattern is transferred onto the surface by providing a heated gas current to heat the decorating film.04-30-2009
20090236772PATTERN TRANSFER MOLD AND PATTERN TRANSFER METHOD - A pattern transfer mold is suitable for transferring at least one decorative pattern of a film to at least one workpiece. The pattern transfer mold includes a mold base and a mold core. The mold base has a mold cavity and an air vent associated with the mold cavity. The mold core is inserted in the mold cavity of the mold base and has an upper surface and a plurality of upper air grooves on the upper surface. The mold cavity and the mold core have a plurality of mold air channels located between the mold cavity and the mold core. The upper air grooves are associated with the air vent via the mold air channels.09-24-2009
20110061798PRODUCTION METHOD OF THREE-DIMENSIONAL PATTERN - A production method of a three-dimensional pattern is disclosed. First, an adhesive layer is applied on a three-dimensional workpiece. Next, a film is vacuum adsorbed on the adhesive layer so that the film is impressed onto the adhesive layer to form the three-dimensional pattern on the adhesive layer. Finally, the adhesive layer is cured.03-17-2011
20110064915METAL WORKPIECE WITH THREE-DIMENSIONAL PATTERN AND PRODUCTION METHOD THEREOF - A production method of metal workpiece is provided. First, an adhesive layer is applied on a metal workpiece. The adhesive layer is impressed by a mold, so that the adhesive layer forms a three-dimensional pattern. The adhesive layer is then cured by implementing a plurality of heat treatments thereon. A metal workpiece with three-dimensional pattern is also provided.03-17-2011
20110064924PRODUCTION METHOD, WORKPIECE AND PRODUCTION DEVICE OF THREE-DIMENSIONAL PATTERN - A production method of three-dimensional pattern is disclosed. First, an adhesive layer is applied on a three-dimensional workpiece. Next, a film is vacuum adsorbed on the adhesive layer so that the film is impressed onto the adhesive layer to form the three-dimensional pattern on the adhesive layer. Finally, the adhesive layer is cured by implementing a plurality of heat treatments thereon. A workpiece of three-dimensional pattern and a production device of three-dimensional pattern are also disclosed.03-17-2011
20110183270METHOD FOR FORMING THREE-DIMENSIONAL PATTERN - A method for forming a three-dimensional pattern includes following steps. A shaped workpiece having an inner surface and an outer surface is provided, and a first photoresist layer and a second photoresist layer are respectively formed on the outer surface and the inner surface. The shaped workpiece is placed on a transparent fixture. The first photoresist layer and the second photoresist layer are exposed and developed, such that the first photoresist layer forms a patterned photoresist layer, and the second photoresist layer forms an etching protection layer. The shaped workpiece is etched to form the three-dimensional pattern on the outer surface of the shaped workpiece. The patterned photoresist layer and the etching protection layer are removed.07-28-2011

Chien-Min Chen, Hukou TW

Patent application numberDescriptionPublished
20110095316LED PACKAGE STRUCTURE - An LED package structure includes an LED die, a lead frame and a housing connecting to the lead frame. The LED die is located on a surface of the lead frame. The housing includes an inner face surrounding the LED die. The inner face has a bottom edge connected to the surface of the lead frame, a top edge and a waist line between the bottom edge and top edge. The bottom edge surrounds an area less than an area surrounded by the waist line. The area surrounded by the waist line is less than an area surrounded by the top edge. The inner face has a curved surface between the waist line and the bottom edge.04-28-2011
20110156085SEMICONDUCTOR PACKAGE - A semiconductor package includes at least four lead frames each having an extending portion and a connecting portion, a heat dissipation plate having a top surface and a bottom surface, at least one semiconductor chip positioned on the top surface of the heat dissipation plate. At least one conductive wire electrically connects the chip to the lead frames. An encapsulation covers the lead frames, the heat dissipation plate, the semiconductor chip, and the conductive wires, while the bottom surface of the heat dissipation plate and the extending portions of the lead frames are exposed.06-30-2011

Chien-Min Chen, Tu-Cheng TW

Patent application numberDescriptionPublished
20090236405METHOD FOR MAKING BACKLIGHT MODULE FRAME - An exemplary method for making backlight module frame includes: providing a plurality of metallic sheets cooperatively defining a frame shape, and a positioning device comprising a worktable and a plurality of positioning portions defined at corners of the worktable, wherein each metallic sheet comprises a first positioning protrusion corresponding to the positioning portions, positioning the metallic sheets on the worktable of the positioning device with the first positioning protrusions of the metallic sheets engaging with the positioning portions of the positioning device, welding the metallic sheets together to form a semi-manufactured frame, and pressing the semi-manufactured frame to form a backlight module frame.09-24-2009
20090239438METHOD FOR MAKING BACKLIGHT MODULE FRAME - An exemplary method for making backlight module frames includes: method includes: providing a first metallic sheet and a second metallic sheet, each of the first and second metallic sheets having at least two L-shaped portions connected side by side and oriented in the same direction; welding the two metallic sheets to form a plurality of connected semi-manufactured frames corresponding to s subsequent backlight module frame; and pressing the connected semi-manufactured frames to form a plurality of backlight module frames. The method costs less welding time and it is convenient for the backlight module frames to be mass-produced.09-24-2009

Patent applications by Chien-Min Chen, Tu-Cheng TW

Chien-Min Chen, Taipei TW

Patent application numberDescriptionPublished
20090116342Movable clock - A movable clock includes a control system (05-07-2009

Chien-Min Chen, Hsinchu TW

Patent application numberDescriptionPublished
20120025215SEMICONDUCTOR PACKAGE WITH HEAT DISSIPATING STRUCTURE - A semiconductor package includes a substrate, a number of electrodes formed in the substrate, a heat dissipating member fixed on the substrate, and at least one semiconductor chip mounted on the heat dissipating member and electrically connected to the electrodes. The heat dissipating member defines a receiving through hole and includes a conducting portion formed at the bottom of the receiving through hole. The at least one semiconductor chip is mounted on the conducting portion. The conducting portion efficiently conducts the heat generated by the semiconductor chip to the heat dissipating member and improves the heat dissipating efficiency of the semiconductor package.02-02-2012

Chien-Min Fang, Tu-Cheng TW

Patent application numberDescriptionPublished
20090049337SYSTEM AND METHOD FOR TESTING REDUNDANCY AND HOT-SWAPPING CAPABILITY OF A REDUNDANT POWER SUPPLY - A system for testing redundancy and hot-swapping capability of a redundant power supply includes a power switch fixture, a system under test (SUT), and a computing device. The power switch fixture includes a processor, an alternating current (AC) source, a first relay, a second, and two AC outputs. The processor is configured for controlling the AC source to output voltage to the two AC outputs by switching one of the first and the second relay on and the first and the second relay off, so as to ensure that one of the first power supply and the second power supply is operable to provide power to the SUT. The SUT includes a redundant power supply that includes a first power supply and a second power supply. The computing device includes a test control unit for testing redundancy and hot-swapping capability of the redundant power supply.02-19-2009

Chien-Min Hsu, Hsinchu TW

Patent application numberDescriptionPublished
20090219668CAPACITOR DEVICES HAVING MULTI-SECTIONAL CONDUCTORS - A capacitive device is provided. The capacitive device includes a first electrode and a second electrode below the first electrode and spaced apart from the first electrode, wherein at least one of the first electrode and the second electrode includes a plurality of conductive step sections, the plurality of conductive step sections having different heights. The capacitive device also includes an insulating region between the first electrode and the second electrode; and at least one slot formed on one of the first electrode and the second electrode.09-03-2009
20100321858MULTILAYER CAPACITORS AND METHODS FOR MAKING THE SAME - A capacitor device may include a first electrode, a second electrode, a third electrode, a first dielectric layer, and a second dielectric layer. The first electrode may be coupled with a first terminal of the capacitor device. The second electrode is under the first electrode and may be coupled with a second terminal of the capacitor device. The second electrode may be electrically isolated from the first electrode. The third electrode is under the first electrode and the second electrode and may be electrically isolated from the second electrode and electrically coupled with the first electrode. The first dielectric layer has a first dielectric constant and may be sandwiched between the first electrode and the second electrode. The second dielectric layer may have a second dielectric constant and may be sandwiched between the second electrode and the third electrode. In one embodiment, the second dielectric constant is at least five times larger than the first dielectric constant.12-23-2010

Chien-Min Hsu, Wugu Shiang TW

Patent application numberDescriptionPublished
20080239622WIRING STRUCTURE OF LAMINATED CAPACITORS - The present invention relates to a wiring structure for reducing the equivalent series inductance (ESL) of a laminated capacitor. The laminated capacitor comprises a number of conductive layers, a power via extending along a thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer, and a ground via extending along the thickness direction of the laminated capacitor and arranged to extend from the top conductive layer to the bottom conductive layer. The conductive layers include a set of first conductive layers and a set of second conductive layers. The power via is electrically coupled to the first conductive layers and the ground via is electrically coupled to the second conductive layers. The laminated capacitor further comprises a supplemental via between the power via and the ground via. The supplemental via is shorter in length than the power via and the ground via. The supplemental via is electrically coupled to one of the first conductive layers and the second conductive layer.10-02-2008

Chien-Min Huang, Clovis, CA US

Patent application numberDescriptionPublished
20100214425METHOD OF IMPROVING THE VIDEO IMAGES FROM A VIDEO CAMERA - A method of improving a video image by removing the effects of camera vibration comprising the steps of, obtaining a reference frame, receiving an incoming frame, determining the frame translation vector for the incoming frame, translating the incoming frame to generate a realigned frame, performing low pass filtering in the spatial domain on pixels in the realigned frame, performing low pass filtering in the spatial domain on pixels in the reference frame, determining the absolute difference between the filtered pixels in the reference frame and the filtered pixels in the realigned frame, performing low pass filtering in the temporal domain on the pixels in the realigned frame to generate the output frame if the absolute difference is less than a predetermined threshold, and providing the realigned frame as the output frame if the absolute difference is greater than the predetermined threshold.08-26-2010

Chien-Min Lin, Taipei TW

Patent application numberDescriptionPublished
20090026608Crosstalk-Free WLCSP Structure for High Frequency Application - A structure, a system, and a method for manufacture of crosstalk-free wafer level chip scale packaging (WLCSP) structure for high frequency applications is provided. An illustrative embodiment comprises a substrate on which various layers and structures form circuitry, a signal pin formed on the substrate and coupled with the circuitry, a ground ring encircling the signal pin, and a grounded solder bump coupled to the ground ring.01-29-2009
20090050356Capacitors with Insulating Layer Having Embedded Dielectric Rods - A circuit structure is provided. The circuit structure includes a capacitor including a top capacitor electrode; a bottom capacitor electrode parallel to the top capacitor electrode; and an insulating layer between the top and the bottom capacitor electrodes. The insulating layer includes a dielectric rod enclosed by a dielectric material. The dielectric rod has a higher dielectric constant than that of the dielectric material. The circuit structure may be a printed circuit board or packaging substrate, wherein the capacitor is formed between the two layers of the capacitor. Additional dielectric rods may be formed in the insulating layer of the capacitor and spaced apart from the dielectric rods.02-26-2009

Chien-Min Liu, Taichung County 434 TW

Patent application numberDescriptionPublished
20110042782ON-CHIP INDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME - The present invention relates to a an on-chip inductor structure and a method for manufacturing the same. The an on-chip inductor structure according to the present invention comprises a substrate, a porous layer, a plurality of conductors, and an inductor. The porous layer is disposed on the substrate and has a plurality of voids; each of the plurality of conductors is disposed in the plurality of voids, respectively; and the inductor is disposed on the porous layer. Because the plurality of conductors is used as the core of the inductor, the inductance is increased effectively and the area of the an on-chip inductor is reduced. Besides the manufacturing method according to the present invention is simple and compatible with the current CMOS process, the manufacturing cost can be lowered.02-24-2011

Chien-Min Weng, Industrial Park TW

Patent application numberDescriptionPublished
20100215931ITO layer structure - A ITO layer structure, which is composed of the ITO as the outermost layer and the first anti-reflected layer on the specific side of the transparent substrate, furthermore, the second anti-reflected layer is formed on the opposite side of substrate, can improve the total transmittance.08-26-2010

Chien-Min Weng, Tao-Yuan TW

Patent application numberDescriptionPublished
20100101937METHOD OF FABRICATING TRANSPARENT CONDUCTIVE FILM - A method of fabricating transparent conductive film including the following steps is provided. First, a reactive chamber having at least a target and at least a heating device is provided. Subsequentially, a plasma is generated in the reactive chamber, wherein the plasma is located above the target. Next, the plasma is heated by the heating device from a standby temperature to a working temperature. Simultaneously, a hard plastic substrate is passed above the plasma at a specific speed, wherein the particles of the target are bombarded by the plasma so as to form transparent conductive film on the hard plastic substrate.04-29-2010
20110056244METHOD OF STRENGTHENING GLASS PLATE - A method of strengthening glass plate is provided. A plasma treating process is performed on a glass plate so that a surface pore variation of the glass plate after the plasma treating process is reduced relative to the surface pore variation of the glass plate before the plasma treating process, wherein the surface pore variation is a variation degree of surface pores in different unit areas of the glass plate. In the mean time, a melted network crosslinking structure is formed on the surface of the glass plate. Based on the above-mentioned mechanisms, the glass plate is strengthened. The plasma treating process is conducive to strengthen the glass plate whether the plasma treating process is performed before or after the conventional chemical strengthening process.03-10-2011
20110234507INTEGRATED TOUCH PANEL AND MANUFACTURING METHOD THEREOF - The present invention provides an integrated touch panel comprising a transparent substrate, one of an icon or artwork layer, a first layer of optical film, and a first sensing layer. The icon layer or artwork layer is coated on the periphery of one side face of the transparent substrate, and the inner periphery of the icon layer or artwork layer is not perpendicular to the adjacent line of the transparent substrate. The first layer of optical film is stacked on icon layer or artwork layer and the areas on the transparent substrate uncovered with icon layer. The first sensing layer is stacked on the first layer of optical film by sputtering. The interchangeability is included in the patent claim of the present invention. As icon layer or artwork layer is not perpendicular to the transparent substrate, the subsequent cladding of the structures may be completed by sputtering or other methods.09-29-2011
20120009354Method for treating surface of glass substrate and apparatus for performing same - A method for treating a surface of a glass substrate according to the invention has the steps of placing the glass substrate into a vacuum treatment chamber, introducing a gas into the vacuum treatment chamber, providing electric power to generate an ion source and using the ion source to treat the surface of the glass substrate. By this way, the invention can achieve an effect of surface cleaning and further render the conductive film to be coated on the glass substrate in the subsequent stage to have a reduced surface resistance, thereby improving the conductivity of the glass substrate. The film coated on the glass substrate in the subsequent stage will have higher crystalline level as well.01-12-2012
20120009392Strengthened substrate structure - The substrate according to the invention includes at least one surface coated with an organic buffer layer and the organic buffer layer is provided with a coating layer on a surface thereof opposite to its surface attached to the substrate. The provision of the organic buffer layer diminishes the effect of the coating layer on the strength of the substrate, thereby maintaining the strength of the substrate.01-12-2012

Patent applications by Chien-Min Weng, Tao-Yuan TW

Chien-Min Wu, Taipei TW

Patent application numberDescriptionPublished
20100040821Molding glass lens and mold thereof - A molding glass lens and a mold thereof are disclosed. The molding glass lens consists of an upper optical surface, a lower optical surface, two outers surrounding the optical surfaces and at least three grooves arranged in the form of a circle disposed on the lower outer and/or the upper outer. The disposition of the grooves has no affecting in original size of the outers as well as assembling with other mechanical parts in les group. The mold of the lens includes an upper molding unit and a lower molding unit. Cavity of each molding unit is composed of a central part for forming an optical surface of the lens and an outer circular part for forming outer of the lens. At least three protrudent parts with the same height are disposed in the form of a circle on the outer circular of the lower molding unit and/or the upper molding unit. Thus the air in the mold cavity is easy to exhaust through the gap formed by protrudent parts and glass preform. Therefore, air bubbles generated during the molding processes are prevented and precision of the glass lens is provided.02-18-2010
20100157428GLASS LENS ARRAY MODULE WITH ALIGNMENT MEMBER AND MANUFACTURING METHOD THEREOF - A glass lens array module with alignment fixture and a manufacturing method thereof are revealed. A glass lens array is produced by multi-cavity glass molding and alignment members are arranged on a peripheral of non-optical area of the glass lens array. Optical axis of each of two adjacent glass lens arrays is aligned by corresponding alignment members and the glass lens arrays are assembled by glue. A spacer is disposed between the two adjacent glass lens arrays to form a preset interval if needed. Thus a glass lens array module is formed after curing of the glue. Thereby the alignment of the optical axis of the glass lens is achieved easily and optical precision is also attained. Moreover, the manufacturing processes are simplified and the cost is reduced.06-24-2010
20100284089STACKED OPTICAL GLASS LENS ARRAY, STACKED LENS MODULE AND MANUFACTURING METHOD THEREOF - A stacked optical glass lens array, a stacked lens module and a manufacturing method thereof are disclosed. The stacked optical glass lens array includes at least two optical glass lens arrays whose optical axis are aligned and then stacked with each other by cement glue in glue grooves. A stacked optical glass lens element can be singularized by cutting along with the alignment notches of stacked optical glass lens array. The stacked lens module is formed by a single stacked optical glass lens element and related optical element mounted in a lens holder. Thereby the optical axis of the lenses of the stacked lens module are aligned precisely, the manufacturing processes are simplified and the production cost is reduced.11-11-2010

Chien-Min Wu, Hsinchu City TW

Patent application numberDescriptionPublished
20100015534METHOD FOR MONITORING PHOTOLITHOGRAPHY PROCESS AND MONITOR MARK - A method for monitoring a photolithography process includes providing a monitor mark having high sensitivity of the focus of the photolithography process, transferring the monitor mark together with the product patterns through the photolithography process onto a substrate, and measuring the deviation dimension of the monitor mark formed on the substrate to real-time monitor the focus of the photolithography process.01-21-2010
20100149535METHOD OF MEASURING NUMERICAL APERTURE OF EXPOSURE MACHINE, CONTROL WAFER, PHOTOMASK, AND METHOD OF MONITORING NUMERICAL APERTURE OF EXPOSURE MACHINE - A method of measuring a numerical aperture of an exposure machine is described. A control wafer having vernier marks thereon and an aberration mask having pinholes therein are provided, wherein each pinhole corresponds to a vernier mark in position. A lithography process using the exposure machine and the aberration mask is performed to the control wafer, so as to form over each vernier mark a photoresist pattern having the same shape of the illumination pattern of the light source of the exposure machine. The numerical aperture of the exposure machine is then derived from a graduation of the vernier mark corresponding to an outer edge of the photoresist pattern.06-17-2010
20100265774METHOD FOR DETERMINING NATIVE THRESHOLD VOLTAGE OF NONVOLATILE MEMORY - A method for determining native threshold voltage of nonvolatile memory includes following steps. A memory cell including a control gate, a charge storage layer, a source region, and a drain region is provided. A programming operation is performed on the memory cell by using F-N tunneling effect to obtain a programming curve of time versus threshold voltage. In the programming operation, a positive voltage is applied to the control gate. An erase operation is performed on the memory cell by using F-N tunneling effect to obtain an erasure curve of time versus threshold voltage. In the erase operation, a negative voltage is applied to the control gate. The absolute values of the positive voltage and the negative voltage are the same. The native threshold voltage of memory cell is determined from the cross point of the programming curve and the erasure curve.10-21-2010

Patent applications by Chien-Min Wu, Hsinchu City TW