| Patent application number | Description | Published |
|---|
| 20090267210 | INTEGRATED CIRCUIT PACKAGE AND MANUFACTURING METHOD THEREOF - An integrated circuit package and a manufacturing method thereof are provided. The package includes a die pad, a plurality of first and second contact pads, a first die, a second die and a molding compound. The contact pads adjacent to at least one side of the die pad are arranged along an inner row and an outer row with respect to the die pad. The first die is fixed on the first die and electrically connected to the first contact pads by wire-bonding. The second die is fixed on the first die and electrically connected to the second contact pads by wire-bonding. The molding compound covers the second die, the first die, the die pad, the first contact pads and the second contact pads. The bottoms of the die pad, the first contact pads and the second contact pads are exposed at the bottom surface of the molding compound. | 10-29-2009 |
| 20090278242 | STACKED TYPE CHIP PACKAGE STRUCTURE - A stacked type chip package structure including a lead frame, a chip package, a second chip, and a second molding compound is provided. The lead frame includes a plurality of first leads and second leads insulated from one another. The first leads have a first upper surface, and the second leads have a second upper surface which is not co-planar with the first upper surface. The chip package is disposed on the first leads and includes a substrate, a first chip, and a first molding compound. The second chip is stacked on the chip package and electrically connected to the second leads. The second molding compound is disposed on the lead frame and filled among the first leads and the second leads for encapsulating the chip package and the second chip. | 11-12-2009 |
| 20090278243 | STACKED TYPE CHIP PACKAGE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A stacked type chip package structure including a chip carrier, a first chip, a second chip, a third chip, and an insulating material is provided. The chip carrier includes two die pads and a plurality of leads surrounding the die pads. The first chip and the second chip are disposed on the die pads respectively, and are electrically connected to the leads by wire bonding. The third chip traverses the first chip and the second chip, and is electrically connected to the first chip and the second chip respectively. The insulating material is disposed on the chip carrier for encapsulating the first chip, the second chip and the third chip, and fills among the die pads and the leads. | 11-12-2009 |
| 20100184255 | MANUFACTURING METHOD FOR PACKAGE STRUCTURE - A manufacturing method for package structure is provided. The manufacturing method includes the follow steps. Firstly, a substrate is provided. Next, a number of chips are provided. Then, the chips are electrically connected with the substrate. After that, the chips are encapsulated with a sealant, so that the chips and the substrate form a package. Then, the package is adhered by a vacuum force. Afterwards, the adhered package is singulated to form many package structures along the portion between adjacent two of airways. | 07-22-2010 |
| 20100213598 | CIRCUIT CARRIER AND SEMICONDUCTOR PACKAGE USING THE SAME - A circuit carrier suitable for being connected with a bump is provided. The circuit carrier includes a substrate and at least one bonding pad. The substrate has a bonding pad disposed on a surface thereof for being connected with the bump. A brown-oxide layer is disposed on a surface of the bonding pad. | 08-26-2010 |
