| Patent application number | Description | Published |
|---|
| 20110062580 | PROTECTION LAYER FOR PREVENTING UBM LAYER FROM CHEMICAL ATTACK AND OXIDATION - A protection layer formed of a CuGe | 03-17-2011 |
| 20110101521 | POST PASSIVATION INTERCONNECT WITH OXIDATION PREVENTION LAYER - A copper interconnect line formed on a passivation layer is protected by a copper-containing material layer including a group III element, a group IV element, a group V element or combinations thereof. | 05-05-2011 |
| 20110101523 | PILLAR BUMP WITH BARRIER LAYER - A copper pillar bump has a surface covered with by a barrier layer formed of a copper-containing material layer including a group III element, a group IV element, a group V element or combinations thereof. The barrier layer depresses the copper diffusion and reaction with solder to reduce the thickness of intermetallic compound between the pillar pump and solder. | 05-05-2011 |
| 20110233761 | CU PILLAR BUMP WITH NON-METAL SIDEWALL PROTECTION STRUCTURE - Sidewall protection processes are provided for Cu pillar bump technology, in which a protection structure on the sidewalls of the Cu pillar bump is formed of at least one of non-metal material layers, for example a dielectric material layer, a polymer material layer, or combinations thereof. | 09-29-2011 |
| 20110241040 | NOVEL SEMICONDUCTOR PACKAGE WITH THROUGH SILICON VIAS - The substrate with through silicon plugs (or vias) described above removes the need for conductive bumps. The process flow is very simple and cost efficient. The structures described combines the separate TSV, redistribution layer, and conductive bump structures into a single structure. By combining the separate structures, a low resistance electrical connection with high heat dissipation capability is created. In addition, the substrate with through silicon plugs (or vias, or trenches) also allows multiple chips to be packaged together. A through silicon trench can surround the one or more chips to provide protection against copper diffusing to neighboring devices during manufacturing. In addition, multiple chips with similar or different functions can be integrated on the TSV substrate. Through silicon plugs with different patterns can be used under a semiconductor chip(s) to improve heat dissipation and to resolve manufacturing concerns. | 10-06-2011 |
| 20110241061 | HEAT DISSIPATION BY THROUGH SILICON PLUGS - The package substrates with through silicon plugs (or vias) described above provide lateral and vertical heat dissipation pathways for semiconductor chips that require thermal management. Designs of through silicon plugs (TSPs) with high duty ratios can most effectively provide heat dissipation. TSP designs with patterns of double-sided combs can provide high duty ratios, such as equal to or greater than 50%. Package substrates with high duty ratios are useful for semiconductor chips that generate large amount of heat. An example of such semiconductor chip is a light-emitting diode (LED) chip. | 10-06-2011 |
| 20110254159 | CONDUCTIVE FEATURE FOR SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURE - An embodiment of the disclosure includes a conductive feature on a semiconductor die. A substrate is provided. A bond pad is formed over the substrate. The bond pad has a first width. A polyimide layer is formed over the substrate and the bond pad. The polyimide layer has a first opening over the bond pad with a second width. A silicon-based protection layer overlies the polyimide layer. The silicon-based protection layer has a second opening over the bond pad with a third width. The first opening and the second opening form a combined opening having sidewalls to expose a portion of the bond pad. A UBM layer is formed over the sidewalls of combined opening to contact the exposed portion of the bond pad. A conductive feature overlies the UBM layer. | 10-20-2011 |
| 20110266667 | CU PILLAR BUMP WITH NON-METAL SIDEWALL PROTECTION STRUCTURE - A sidewall protection structure is provided for covering at least a portion of a sidewall surface of a bump structure, in which a protection structure on the sidewalls of a Cu pillar and a surface region of an under-bump-metallurgy (UBM) layer is formed of at least one non-metal material layers, for example a dielectric material layer, a polymer material layer, or combinations thereof. | 11-03-2011 |
