Patent application number | Description | Published |
20110062580 | PROTECTION LAYER FOR PREVENTING UBM LAYER FROM CHEMICAL ATTACK AND OXIDATION - A protection layer formed of a CuGe | 03-17-2011 |
20110101521 | POST PASSIVATION INTERCONNECT WITH OXIDATION PREVENTION LAYER - A copper interconnect line formed on a passivation layer is protected by a copper-containing material layer including a group III element, a group IV element, a group V element or combinations thereof. | 05-05-2011 |
20110101523 | PILLAR BUMP WITH BARRIER LAYER - A copper pillar bump has a surface covered with by a barrier layer formed of a copper-containing material layer including a group III element, a group IV element, a group V element or combinations thereof. The barrier layer depresses the copper diffusion and reaction with solder to reduce the thickness of intermetallic compound between the pillar pump and solder. | 05-05-2011 |
20110233761 | CU PILLAR BUMP WITH NON-METAL SIDEWALL PROTECTION STRUCTURE - Sidewall protection processes are provided for Cu pillar bump technology, in which a protection structure on the sidewalls of the Cu pillar bump is formed of at least one of non-metal material layers, for example a dielectric material layer, a polymer material layer, or combinations thereof. | 09-29-2011 |
20110241040 | NOVEL SEMICONDUCTOR PACKAGE WITH THROUGH SILICON VIAS - The substrate with through silicon plugs (or vias) described above removes the need for conductive bumps. The process flow is very simple and cost efficient. The structures described combines the separate TSV, redistribution layer, and conductive bump structures into a single structure. By combining the separate structures, a low resistance electrical connection with high heat dissipation capability is created. In addition, the substrate with through silicon plugs (or vias, or trenches) also allows multiple chips to be packaged together. A through silicon trench can surround the one or more chips to provide protection against copper diffusing to neighboring devices during manufacturing. In addition, multiple chips with similar or different functions can be integrated on the TSV substrate. Through silicon plugs with different patterns can be used under a semiconductor chip(s) to improve heat dissipation and to resolve manufacturing concerns. | 10-06-2011 |
20110241061 | HEAT DISSIPATION BY THROUGH SILICON PLUGS - The package substrates with through silicon plugs (or vias) described above provide lateral and vertical heat dissipation pathways for semiconductor chips that require thermal management. Designs of through silicon plugs (TSPs) with high duty ratios can most effectively provide heat dissipation. TSP designs with patterns of double-sided combs can provide high duty ratios, such as equal to or greater than 50%. Package substrates with high duty ratios are useful for semiconductor chips that generate large amount of heat. An example of such semiconductor chip is a light-emitting diode (LED) chip. | 10-06-2011 |
20110254159 | CONDUCTIVE FEATURE FOR SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURE - An embodiment of the disclosure includes a conductive feature on a semiconductor die. A substrate is provided. A bond pad is formed over the substrate. The bond pad has a first width. A polyimide layer is formed over the substrate and the bond pad. The polyimide layer has a first opening over the bond pad with a second width. A silicon-based protection layer overlies the polyimide layer. The silicon-based protection layer has a second opening over the bond pad with a third width. The first opening and the second opening form a combined opening having sidewalls to expose a portion of the bond pad. A UBM layer is formed over the sidewalls of combined opening to contact the exposed portion of the bond pad. A conductive feature overlies the UBM layer. | 10-20-2011 |
20110266667 | CU PILLAR BUMP WITH NON-METAL SIDEWALL PROTECTION STRUCTURE - A sidewall protection structure is provided for covering at least a portion of a sidewall surface of a bump structure, in which a protection structure on the sidewalls of a Cu pillar and a surface region of an under-bump-metallurgy (UBM) layer is formed of at least one non-metal material layers, for example a dielectric material layer, a polymer material layer, or combinations thereof. | 11-03-2011 |
20110285011 | CU PILLAR BUMP WITH L-SHAPED NON-METAL SIDEWALL PROTECTION STRUCTURE - An L-shaped sidewall protection process is used for Cu pillar bump technology. The L-shaped sidewall protection structure is formed of at least one of non-metal material layers, for example a dielectric material layer, a polymer material layer or combinations thereof. | 11-24-2011 |
20110298123 | CU PILLAR BUMP WITH NON-METAL SIDEWALL SPACER AND METAL TOP CAP - A bump has a non-metal sidewall spacer on a lower sidewall portion of Cu pillar, and a metal top cap on a top surface and an upper sidewall portion of the Cu pillar. The metal top cap is formed by an electroless or immersion plating technique after the non-metal sidewall spacer formation. | 12-08-2011 |
20120007230 | CONDUCTIVE BUMP FOR SEMICONDUCTOR SUBSTRATE AND METHOD OF MANUFACTURE - An embodiment of the disclosure includes a conductive bump on a semiconductor die. A substrate is provided. A bond pad is over the substrate. An under bump metallurgy (UBM) layer is over the bond pad. A copper pillar is over the UBM layer. The copper pillar has a top surface with a first width and sidewalls with a concave shape. A nickel layer having a top surface and a bottom surface is over the top surface of the copper pillar. The bottom surface of the nickel layer has a second width. A ratio of the second width to the first width is between about 0.93 to about 1.07. A solder material is over the top surface of the cap layer. | 01-12-2012 |
20120091577 | COPPER PILLAR BUMP WITH COBALT-CONTAINING SIDEWALL PROTECTION - An integrated circuit device includes a Cu pillar and a solder layer overlying the Cu pillar. A Co-containing metallization layer is formed to cover the Cu pillar and the solder layer, and then a thermally reflow process is performed to form a solder bump and drive the Co element into the solder bump. Next, an oxidation process is performed to form a cobalt oxide layer on the sidewall surface of the Cu pillar. | 04-19-2012 |
20120098124 | SEMICONDUCTOR DEVICE HAVING UNDER-BUMP METALLIZATION (UBM) STRUCTURE AND METHOD OF FORMING THE SAME - A semiconductor device has a UBM (under-bump metallization) structure underlying and electrically connected to a solder bump. The UBM structure has a first metallization layer with a first cross-sectional dimension d | 04-26-2012 |
20120280388 | COPPER PILLAR BUMP WITH NON-METAL SIDEWALL PROTECTION STRUCTURE AND METHOD OF MAKING THE SAME - This description relates to an integrated circuit device including a conductive pillar formed over a substrate. The conductive pillar has a sidewall surface and a top surface. The integrated circuit device further includes an under-bump-metallurgy (UBM) layer between the substrate and the conductive pillar. The UBM layer has a surface region. The integrated circuit device further includes a protection structure on the sidewall surface of the conductive pillar and the surface region of the UBM layer. The protection structure is formed of a non-metal material. | 11-08-2012 |
20130302979 | METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THROUGH SILICON PLUGS - A method of making a semiconductor device, the method includes forming a first opening and a second opening in a substrate. The method further includes forming a conductive material in the first opening and in the second opening, the conductive material comprising a joined portion where the conductive material in the first opening and the conductive material in the second opening are electrically and thermally connected together at a first surface of the substrate. The method further includes reducing a thickness of the substrate from a second surface of the substrate, opposite the first surface, to expose the conductive material in the first opening and the conductive material in the second opening. The method further includes connecting a device to the second surface of the substrate. | 11-14-2013 |
20140154871 | METHOD AND SYSTEM FOR MANUFACTURING SEMICONDUCTOR DEVICE - A method for manufacturing a semiconductor device is provided. The method contains steps of providing the semiconductor device including a working area; directing a medium flow onto the working area; configuring a lens in contact with the medium flow; and directing a laser beam to the working area through the lens and the medium flow. A laser processing for manufacturing a semiconductor device is also provided. | 06-05-2014 |
20140335687 | METHOD OF MAKING A CONDUCTIVE PILLAR BUMP WITH NON-METAL SIDEWALL PROTECTION STRUCTURE - A method of making a semiconductor device includes forming an under bump metallurgy (UBM) layer over a substrate, the UBM layer comprising sidewalls and a surface region. The method further includes forming a conductive pillar over the UBM layer, the conductive pillar includes sidewalls, wherein the conductive pillar exposes the surface region of the UBM layer. The method further includes forming a non-metal protective structure over the sidewalls of the conductive pillar, wherein the non-metal protective structure contacts the surface region of the UBM layer, and the non-metal protective structure exposes the sidewalls of the UBM layer. | 11-13-2014 |
20140342546 | COPPER PILLAR BUMP WITH COBALT-CONTAINING SIDEWALL PROTECTION LAYER - A method of forming an integrated circuit device comprises forming a metal pillar over a semiconductor substrate. The method also comprises forming a solder layer over the metal pillar. The method further comprises forming a metallization layer comprising a cobalt (Co) element, the metallization layer covering the metal pillar and the solder layer. The method additionally comprises thermally reflowing the solder layer to form a solder bump, driving the Co element of the metallization layer into the solder bump. The method also comprises oxidizing the metallization layer to form a metal oxide layer on a sidewall surface of the metal pillar. | 11-20-2014 |
20140363970 | METHOD OF MAKING A PILLAR STRUCTURE HAVING A NON-METAL SIDEWALL PROTECTION STRUCTURE - A method of making a pillar structure includes forming a first under-bump-metallurgy (UBM) layer formed on a pad region of a substrate, wherein the first UBM layer includes sidewalls. The method further includes forming a second UBM layer on the first UBM layer, wherein the second UBM layer includes a sidewall surface, an area of the first UBM layer is greater than an area of the second UBM layer. The method further includes forming a copper-containing pillar on the second UBM layer, wherein the copper-containing pillar includes a sidewall surface and a top surface. The method further includes forming a protection structure on the sidewall surface of the copper-containing pillar and on an entirety of the sidewall surface of the second UBM layer, wherein the protection structure does not cover the sidewalls of the first UBM layer, and the protection structure is a non-metal material. | 12-11-2014 |
Patent application number | Description | Published |
20080268553 | Electroless plating apparatus with non-liquid heating source - An electroless plating apparatus is provided. The electroless plating apparatus includes a wafer holder; a chemical dispensing nozzle over the wafer holder; a conduit connected to the chemical dispensing nozzle; and a radiation source over the wafer holder. | 10-30-2008 |
20090317214 | NOVEL WAFER'S AMBIANCE CONTROL - A semiconductor manufacturing system, an interface system, a carrier, and a method for providing an ambient controlled environment is disclosed. The semiconductor manufacturing system comprises a plurality of process chambers; at least one interface system, wherein the interface system includes a first ambient control element; at least one carrier, wherein the carrier comprises a second ambient control element; and a control module coupled to the plurality of process chambers, the at least one interface system, and the at least one carrier. | 12-24-2009 |
20100018463 | Plural Gas Distribution System - A plural gas distribution system is presented. The system includes a chamber and a showerhead. The chamber is configured to contain and to exhaust a plurality of gases. The showerhead includes at least one multi-channel gas delivery tube with at least two sub-tubes within the multi-channel gas delivery tube, wherein the at least two sub-tubes are configured to simultaneously expel gases unmixed into the chamber. | 01-28-2010 |
20100032096 | Apparatus for Holding Semiconductor Wafers - Apparatus for holding semiconductor wafers during semiconductor manufacturing processes are disclosed. In one embodiment, the apparatus comprises a heat-conductive layer disposed on a supporting base. The apparatus also comprises a plurality of holes formed through the heat-conductive layer and the supporting base. The apparatus further comprises a plurality of heat-conductive lift pins that extend through the holes over the heat-conductive layer at the top end, and make a direct contact with a wafer substrate. The heat-conductive layer and the lift pins are connected to a heating circuit. | 02-11-2010 |
20100285723 | POLISHING APPARATUS - A chemical mechanical polishing (CMP) device for processing a wafer is provided which includes a plate for supporting the wafer to be processed in a face-up orientation, a polishing head opposing the plate, wherein the polishing head includes a rotatable polishing pad operable to contact the wafer while the polishing pad is rotating, and a slurry coating system providing a slurry to the polishing pad for polishing the wafer. | 11-11-2010 |
20110115077 | Method for Reducing Voids in a Copper-Tin Interface and Structure Formed Thereby - An embodiment is a method for forming a semiconductor assembly comprising cleaning a connector comprising copper formed on a substrate, applying cold tin to the connector, applying hot tin to the connector, and spin rinsing and drying the connector. | 05-19-2011 |
20120018878 | Doping Minor Elements into Metal Bumps - A method of forming a device includes providing a substrate, and forming a solder bump over the substrate. A minor element is introduced to a region adjacent a top surface of the solder bump. A re-flow process is then performed to the solder bump to drive the minor element into the solder bump. | 01-26-2012 |
20120068218 | THERMALLY EFFICIENT PACKAGING FOR A PHOTONIC DEVICE - The present disclosure provides a method of packaging for a photonic device, such as a light-emitting diode device. The packaging includes an insulating structure. The packaging includes first and second conductive structures that each extend through the insulating structure. A substantial area of a bottom surface of the light-emitting diode device is in direct contact with a top surface of the first conductive structure. A top surface of the light-emitting diode device is bonded to the second conductive structure through a bonding wire. | 03-22-2012 |
20120088362 | Thermal Compressive Bond Head - A method includes allowing a work piece having a solder bump to contact a bond head; heating the bond head until the solder bump is melted; and conducting a cooling media into the bond head to cool the solder bump and to solidify the solder bump. | 04-12-2012 |
20120111922 | Thermal Compressive Bonding with Separate Die-Attach and Reflow Processes - A method of bonding includes providing a first work piece, and attaching a second work piece on the first work piece, with a solder bump disposed between the first and the second work pieces. The second work piece is heated using a heating head of a heating tool to melt the solder bump. After the step of heating the second work piece, one of the first and the second work pieces is allowed to move freely in a horizontal direction to self-align the first and the second work pieces. After the step of allowing one of the first and the second work pieces to move, a temperature of the heating head is lowed until the first solder bump solidifies to form a second solder bump. | 05-10-2012 |
20120211547 | In-Situ Accuracy Control in Flux Dipping - A flux dipping apparatus includes a flux plate having a top surface; and a dipping cavity in the flux plate and recessed from the top surface. A flux leveler is disposed over the flux plate and configured to move parallel to the top surface. A piezoelectric actuator is configured to adjust a distance between the flux leveler and the top surface in response to a controlling voltage applied to electrodes of the first piezoelectric actuator. | 08-23-2012 |
20120227886 | Substrate Assembly Carrier Using Electrostatic Force - A portable electrostatic chuck carrier includes a holder having a dielectric top surface, and bipolar electrodes under the dielectric top surface. The bipolar electrodes includes positive electrodes and negative electrodes electrically insulated from the positive electrodes. The positive electrodes and the negative electrodes are allocated in an alternating pattern in a plane substantially parallel to the dielectric top surface. | 09-13-2012 |
20120286423 | Doping Minor Elements into Metal Bumps - A method of forming a device includes providing a substrate, and forming a solder bump over the substrate. A minor element is introduced to a region adjacent a top surface of the solder bump. A re-flow process is then performed to the solder bump to drive the minor element into the solder bump. | 11-15-2012 |
20130048027 | Package Assembly Cleaning Process Using Vaporized Solvent - A method includes generating a solvent-containing vapor that contains a solvent. The solvent-containing vapor is conducted to a package assembly to clean the package assembly. The solvent-containing vapor condenses to form a liquid on a surface of the package assembly, and flows off from the surface of the package assembly. | 02-28-2013 |
20130115752 | Pick-and-Place Tool for Packaging Process - An apparatus includes a guide ring, and a bond head installed on the guide ring. The bond head is configured to move in loops along the guide ring. The bond head is configured to pick up dies and place the dies during the loops | 05-09-2013 |
20130146647 | Integrated Reflow and Cleaning Process and Apparatus for Performing the Same - A method includes reflowing a solder region of a package structure, and performing a cleaning on the package structure at a cleaning temperature higher than a room temperature. Between the step of reflowing and the step of cleaning, the package structure is not cooled to temperatures close to the room temperature. | 06-13-2013 |
20130167373 | Methods for Stud Bump Formation and Apparatus for Performing the Same - An apparatus includes a spool configured to supply a wire, a cutting device configured to form a notch in the wire, and a capillary configured to bond the wire and to form a stud bump. The apparatus is further configured to pull the wire to break at the notch, with a tail region attached to the stud bump. | 07-04-2013 |
20130228951 | Wafer-Level Underfill and Over-Molding - A mold includes a top portion, and an edge ring having a ring-shape. The edge ring is underlying and connected to edges of the top portion. The edge ring includes air vents. The edge ring further encircles the inner space under the top portion of the mold. A plurality of injection ports is connected to the inner space of the mold. The plurality of injection ports is substantially aligned to a straight line crossing a center of the top portion of the mold. The plurality of injection ports has different sizes. | 09-05-2013 |
20140030849 | Pick-and-Place Tool for Packaging Process - An apparatus includes a guide ring, and a bond head installed on the guide ring. The bond head is configured to move in loops along the guide ring. The bond head is configured to pick up dies and place the dies during the loops | 01-30-2014 |
20140061153 | Methods for Forming Apparatus for Stud Bump Formation - An apparatus used for forming stud bumps may be formed by providing a first clamp plate comprising a clamping surface, forming a notcher on the clamping surface, and forming a contact stopper on the clamping surface. The apparatus may include a clamp that includes at least two opposing plates, and at least one of the opposing plates includes a protruding feature that intersects the wire when the wire is clamped forming a first notch in the wire. The method for forming stud bumps includes bonding wire to a bonding surface, releasing the wire from the clamp, passing the wire a notch pitch distance through the clamp, clamping the wire with the clamp forming a second notch in the wire, and breaking the wire leaving a bonded portion of the wire on the bonding surface. | 03-06-2014 |
20140097175 | Apparatus for Holding Semiconductor Wafers - Apparatus for holding semiconductor wafers during semiconductor manufacturing processes are disclosed. In one embodiment, the apparatus comprises a heat-conductive layer disposed on a supporting base. The apparatus also comprises a plurality of holes formed through the heat-conductive layer and the supporting base. The apparatus further comprises a plurality of heat-conductive lift pins that extend through the holes over the heat-conductive layer at the top end, and make a direct contact with a wafer substrate. The heat-conductive layer and the lift pins are connected to a heating circuit. | 04-10-2014 |
20140131863 | Semiconductor Device with Copper-Tin Compound on Copper Connector - An embodiment is a method for forming a semiconductor assembly including cleaning a connector including copper formed on a substrate, applying cold tin to the connector, applying hot tin to the connector, and spin rinsing and drying the connector. | 05-15-2014 |
20140291881 | WAFER LEVEL TRANSFER MOLDING AND APPARATUS FOR PERFORMING THE SAME - A method includes placing a package structure into a mold chase, with top surfaces of device dies in the package structure contacting a release film in the mold chase. A molding compound is injected into an inner space of the mold chase through an injection port, with the injection port on a side of the mold chase. During the injection of the molding compound, a venting step is performed through a first venting port and a second venting port of the mold chase. The first venting port has a first flow rate, and the second port has a second flow rate different from the first flow rate. | 10-02-2014 |
20140363966 | Pillar Bumps and Process for Making Same - Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular, or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art. | 12-11-2014 |