Patent application number | Description | Published |
20080254642 | METHOD OF FABRICATING GATE DIELECTRIC LAYER - A method for fabricating gate dielectric layer is provided. First, a sacrificial layer is formed on a substrate. Next, fluorine ions are implanted into the substrate. Then, the sacrificial layer is then removed. Finally, a dielectric layer is formed on the substrate. | 10-16-2008 |
20090063845 | SYSTEM AND ELECTRONIC DEVICE HAVING MULTIPLE OPERATING SYSTEMS AND OPERATING METHOD THEREOF - A system and an electronic device having multiple operating systems and an operating method thereof are provided. The electronic device includes a display and a system having a first operating system, a second operating system, and an embedded controller. The first operating system consumes less power than the second operating system. The embedded controller receives an input signal to switch between the first operating system and the second operating system and display an interface of the switched operating system on a screen of the display. The first operating system and the embedded controller remain in an alive state after the electronic device is turned on, and the second operating system enters a non-working state after a preset idle time. | 03-05-2009 |
20090064195 | METHOD FOR SYNCHRONIZING INFORMATION OF DUAL OPERATING SYSTEMS - A method for synchronizing information of dual operating systems is provided. The method is used for synchronizing information of a first operating system and a second operating system when an electronic device is switching from a first operating system to a second operating system. First, the second operating system sends an information requesting message to a controller of the electronic device when the first operating system is switched to the second operating system. The controller checks if the first operating system operates in a work mode. If the first operating system operates in the work mode, the controller forwards the information requesting message to the first operating system, so as to obtain the information of the first operating system. Finally, the second system synchronizes the information recorded therein according to the obtained information. | 03-05-2009 |
20100148271 | Method for gate leakage reduction and Vt shift control and complementary metal-oxide-semiconductor device - The present invention relates to a method for gate leakage reduction and Vt shift control, in which a first ion implantation is performed on PMOS region and NMOS region of a substrate to implant fluorine ions, carbon ions, or both in the gate dielectric or the semiconductor substrate, and a second ion implantation is performed only on the NMOS region of the substrate to implant fluorine ions, carbon ions, or both in the gate dielectric or the semiconductor substrate in the NMOS region, with the PMOS region being covered by a mask layer. Thus, the doping concentrations obtained by the PMOS region and the NMOS region are different to compensate the side effect caused by the different equivalent oxide thickness and to avoid the Vt shift. | 06-17-2010 |
20120193796 | POLYSILICON LAYER AND METHOD OF FORMING THE SAME - The method of forming a polysilicon layer is provided. A first polysilicon layer with a first grain size is formed on a substrate. A second polysilicon layer with a second grain size is formed on the first polysilicon layer. The first grain size is smaller than the second grain size. The first polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the second polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved. | 08-02-2012 |
20120204022 | METHOD AND ELECTRONIC DEVICE FOR SYNCHRONIZING INFORMATION OF DUAL OPERATING SYSTEMS AND RECORDING MEDIUM - A method and an electronic device for synchronizing information of dual operating systems and a recording medium are provided. The method is used for synchronizing information of a first operating system and a second operating system when an electronic device is switching from a first operating system to a second operating system. First, the second operating system sends an information requesting message to a controller of the electronic device when the first operating system is switched to the second operating system. The controller checks if the first operating system operates in a work mode. If the first operating system operates in the work mode, the controller forwards the information requesting message to the first operating system, so as to obtain the information of the first operating system. Finally, the second system synchronizes the information recorded therein according to the obtained information. | 08-09-2012 |
20120228723 | GATE STRUCTURE AND METHOD FOR FABRICATING THE SAME - A gate structure and a method for fabricating the same are described. A substrate is provided, and a gate dielectric layer is formed on the substrate. The formation of the gate dielectric layer includes depositing a silicon nitride layer on the substrate by simultaneously introducing a nitrogen-containing gas and a silicon-containing gas. A gate is formed on the gate dielectric layer, so as to form the gate structure. | 09-13-2012 |
20120264284 | MANUFACTURING METHOD FOR METAL GATE STRUCTURE - A manufacturing method for a metal gate structure includes providing a substrate having a gate trench formed thereon, forming a work function metal layer in the gate trench, and performing an annealing process to the work function metal layer. The annealing process is performed at a temperature between 400° C. and 500° C., and in a bout 20 seconds to about 180 seconds. | 10-18-2012 |
20120270382 | METHOD OF FABRICATING AN EPITAXIAL LAYER - A method of fabricating an epitaxial layer includes providing a substrate. The substrate is etched to form at least a recess within the substrate. A surface treatment is performed on the recess to form a Si—OH containing surface. An in-situ epitaxial process is performed to form an epitaxial layer within the recess, wherein the epitaxial process is performed in a hydrogen-free atmosphere and at a temperature lower than 800° C. | 10-25-2012 |
20120306028 | SEMICONDUCTOR PROCESS AND STRUCTURE THEREOF - A semiconductor process is provided, including: a substrate is provided, a buffer layer is formed, and a dielectric layer having a high dielectric constant is formed, wherein the methods of forming the buffer layer include: (1) an oxidation process is performed; and a baking process is performed; Alternatively, (2) an oxidation process is performed; a thermal nitridation process is performed; and a plasma nitridation process is performed; Or, (3) a decoupled plasma oxidation process is performed. Furthermore, a semiconductor structure fabricated by the last process is also provided. | 12-06-2012 |
20120309171 | METHOD FOR FABRICATING SEMICONDUCTOR DEVICE - A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a gate structure thereon; forming a film stack on the substrate and covering the gate structure, wherein the film stack comprises at least an oxide layer and a nitride layer; removing a portion of the film stack for forming recesses adjacent to two sides of the gate structure and a disposable spacer on the sidewall of the gate structure; and filling the recesses with a material comprising silicon atoms for forming a faceted material layer. | 12-06-2012 |
20120329261 | MANUFACTURING METHOD FOR METAL GATE - A manufacturing method for a metal gate includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function. | 12-27-2012 |
20130001707 | FABRICATING METHOD OF MOS TRANSISTOR, FIN FIELD-EFFECT TRANSISTOR AND FABRICATION METHOD THEREOF - A fabricating method of a MOS transistor includes the following steps. A substrate is provided. A gate dielectric layer is formed on the substrate. A nitridation process containing nitrogen plasma and helium gas is performed to nitride the gate dielectric layer. A fin field-effect transistor and fabrication method thereof are also provided. | 01-03-2013 |
20130012012 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A substrate having an oxide layer thereon is provided. A high temperature process higher than 1000° C. is performed to form a melting layer between the substrate and the oxide layer. A removing process is performed to remove the oxide layer and the melting layer. | 01-10-2013 |
20130072028 | PROCESS FOR FABRICATING SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING METAL OXIDE SEMICONDUCTOR DEVICE - A process for fabricating a semiconductor device is described. A silicon oxide layer is formed. A nitridation process including at least two steps is performed to nitridate the silicon oxide layer into a silicon oxynitride (SiON) layer. The nitridation process comprises a first nitridation step and a second nitridation step in sequence, wherein the first nitridation step and the second nitridation step are different in the setting of at least one parameter. | 03-21-2013 |
20130072030 | METHOD FOR PROCESSING HIGH-K DIELECTRIC LAYER - A method for processing a high-k dielectric layer includes the following steps. A semiconductor substrate is provided, and a high-k dielectric layer is formed thereon. The high-k dielectric layer has a crystalline temperature. Subsequently, a first annealing process is performed, and a process temperature of the first annealing process is substantially smaller than the crystalline temperature. A second annealing process is performed, and a process temperature of the second annealing process is substantially larger than the crystalline temperature. | 03-21-2013 |
20130078818 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A substrate is provided. At least a fin-shaped structure is formed on the substrate and an oxide layer is formed on the substrate without the fin-shaped structure forming thereon. A thermal treatment process is performed to form a melting layer on at least a part of the sidewall of the fin-shaped structure. | 03-28-2013 |
20130093064 | SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF - A semiconductor process includes the following steps. A substrate is provided. A dielectric layer having a high dielectric constant is formed on the substrate, wherein the steps of forming the dielectric layer include: (a) a metallic oxide layer is formed; (b) an annealing process is performed to the metallic oxide layer; and the steps (a) and (b) are performed repeatedly. Otherwise, the present invention further provides a semiconductor structure formed by said semiconductor process. | 04-18-2013 |
20130095616 | METHOD FOR MANUFACTURING MULTI-GATE TRANSISTOR DEVICE - A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer, a gate dielectric layer and a gate layer sequentially formed thereon, forming a multiple insulating layer sequentially having a first insulating layer and a second insulating layer and covering the patterned semiconductor layer and the gate layer, removing a portion of the multiple insulating layer to simultaneously form a first spacer around the gate layer and a second spacer around the patterned semiconductor layer, removing the second spacer to expose a portion of the first insulating layer covering the patterned semiconductor layer and simultaneously removing a portion of the first spacer to form a third spacer around the gate layer, and removing the exposed first insulating layer to expose the patterned semiconductor layer. | 04-18-2013 |
20130171837 | SEMICONDUCTOR PROCESS - A semiconductor process includes the following steps. A substrate having a recess is provided. A decoupled plasma nitridation process is performed to nitride the surface of the recess for forming a nitrogen containing liner on the surface of the recess. A nitrogen containing annealing process is then performed on the nitrogen containing liner. | 07-04-2013 |
20140073111 | Method of Forming Isolation Structure - The present invention provides a method of forming an isolation structure. A substrate is provided, and a trench is formed in the substrate. Next, a semiconductor layer is formed on a surface of the trench. A nitridation is carried out to form a nitridation layer in the semiconductor layer. Lastly, an insulation layer is filled into the trench. | 03-13-2014 |
20140159211 | SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF - A semiconductor structure includes a dielectric layer located on a substrate, wherein the dielectric layer includes nitrogen atoms, and the concentration of the nitrogen atoms in the dielectric layer is lower than 5% at a location wherein the distance between this location in the dielectric layer to the substrate is less than 20% of the thickness of the dielectric layer. Moreover, the present invention provides a semiconductor process including the following steps: a dielectric layer is formed on a substrate. Two annealing processes are performed in-situly on the dielectric layer, wherein the two annealing processes have different imported gases and different annealing temperatures. | 06-12-2014 |
20140199817 | METHOD FOR MANUFACTURING MULTI-GATE TRANSISTOR DEVICE - A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer, a gate dielectric layer and a gate layer sequentially formed thereon, forming a multiple insulating layer sequentially having a first insulating layer and a second insulating layer and covering the patterned semiconductor layer and the gate layer, removing a portion of the multiple insulating layer to simultaneously form a first spacer around the gate layer and a second spacer around the patterned semiconductor layer, removing the second spacer to expose a portion of the first insulating layer covering the patterned semiconductor layer and simultaneously removing a portion of the first spacer to form a third spacer around the gate layer, and removing the exposed first insulating layer to expose the patterned semiconductor layer. | 07-17-2014 |
20150021776 | POLYSILICON LAYER - A polysilicon layer including an amorphous polysilicon layer and a crystallized polysilicon layer is provided. The crystallized polysilicon layer is disposed on the amorphous polysilicon layer. Besides, the amorphous polysilicon layer has a first grain size, the crystallized polysilicon layer has a second grain size, and the first grain size is smaller than the second grain size. The amorphous polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the crystallized polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved. | 01-22-2015 |
Patent application number | Description | Published |
20090064186 | MOBILE DEVICE WITH TWO OPERATING SYSTEMS AND METHOD FOR SHARING HARDWARE DEVICE BETWEEN TWO OPERATING SYSTEMS THEREOF - A mobile device and a method for sharing a hardware device thereof are provided. Two operation systems are executed on the present mobile device simultaneously, and an embedded controller is configured to communicate among the two operation systems and a shared hardware device of the mobile device. When one of the operation systems encodes an operating command into a uniform message and transmits the uniform message to the embedded controller, the uniform message is decoded into the operating command by the embedded controller such that the hardware device operates according to the decoded operating command. On the other hand, when the embedded controller receives input data from the hardware device, the embedded controller encodes the input data into the uniform message and transmits the uniform message to one of the operation systems. The operation system receiving the uniform message decodes the uniform message into the input data. | 03-05-2009 |
20120156891 | SILICON DIOXIDE FILM FABRICATING PROCESS - A silicon dioxide film fabricating process includes the following steps. Firstly, a substrate is provided. A rapid thermal oxidation-in situ steam generation process is performed to form a silicon dioxide film on the substrate. An annealing process is performed to anneal the substrate in a first gas mixture at a temperature in the range of 1000° C. to 1100° C. | 06-21-2012 |
20120299124 | GATE STRUCTURE AND A METHOD FOR FORMING THE SAME - A method for forming a gate structure includes the following steps. A substrate is provided. A silicon oxide layer is formed on the substrate. A decoupled plasma-nitridation process is applied to the silicon oxide layer so as to form a silicon oxynitride layer. A first polysilicon layer is formed on the silicon oxynitride layer. A thermal process is applied to the silicon oxynitride layer having the first polysilicon layer. After the thermal process, a second polysilicon layer is formed on the first polysilicon layer. The first polysilicon layer can protect the gate dielectric layer during the thermal process. The nitrogen atoms inside the gate dielectric layer do not lose out of the gate dielectric layer. Thus, the out-gassing phenomenon can be avoided, and a dielectric constant of the gate dielectric layer can not be changed, thereby increasing the reliability of the gate structure. | 11-29-2012 |
20120326162 | PROCESS FOR FORMING REPAIR LAYER AND MOS TRANSISTOR HAVING REPAIR LAYER - A repair layer forming process includes the following steps. Firstly, a substrate is provided, and a gate structure is formed on the substrate, wherein the gate structure at least includes a gate dielectric layer and a gate conductor layer. Then, a nitridation process is performed to form a nitrogen-containing superficial layer on a sidewall of the gate structure. Then, a thermal oxidation process is performed to convert the nitrogen-containing superficial layer into a repair layer. Moreover, a metal-oxide-semiconductor transistor includes a substrate, a gate dielectric layer, a gate conductor layer and a repair layer. The gate dielectric layer is formed on the substrate. The gate conductor layer is formed on the gate dielectric layer. The repair layer is at least partially formed on a sidewall of the gate conductor layer. | 12-27-2012 |
20120329285 | GATE DIELECTRIC LAYER FORMING METHOD - A gate dielectric layer forming method is applied to a fabrication process of a metal-oxide-semiconductor field-effect transistor. The gate dielectric layer forming method includes the following steps. Firstly, a substrate is provided. Then, an interlayer is formed on the substrate. Then, a high-k dielectric layer is formed on the interlayer. A nitridation process is performed to convert the high-k dielectric layer into a nitridated high-k dielectric layer. A first low temperature post-nitridation annealing process is performed to treat the nitridated high-k dielectric layer with a first gas. Afterwards, a second low temperature post-nitridation annealing process is performed to treat the nitridated high-k dielectric layer with a second gas. | 12-27-2012 |
Patent application number | Description | Published |
20110291590 | SWITCHING MODE POWER SUPPLIES AND CONTROL METHODS USED THEREIN TO PROVIDE POWER FACTOR CORRECTION AND CONSTANT OUTPUT CURRENT - Switching mode power supplies (SMPS) and control methods used thereof are disclosed. An exemplifying SMPS is coupled to control an inductive device. The SMPS comprises a voltage divider and a peak controller. The voltage divider comprises a resistor and a controllable resistor connected in series through a connection node. The resistance of the controllable resistor is variable, controlled by a control signal. The voltage divider generates a limiting signal at the connection node based on a line voltage at a line voltage power node. The peak controller controls a peak current flowing through the inductive device according to the limiting signal. | 12-01-2011 |
20120169315 | POWER SUPPLIES AND CONTROL METHODS FOR OPERATING IN QUADRATURE-RESONANCE-SIMILAR MODE - Control method and power controller suitable for a switched mode power supply with a power switch are provided. An ON time of the power switch is recorded. An estimated OFF time is provided based on the ON time. The estimated OFF time is in positive correlation with the ON time. The power switch is turned ON after the elapse of the estimated OFF time. | 07-05-2012 |
20120320632 | POWER SWITCH CONTROLLERS AND METHODS USED THEREIN FOR IMPROVING CONVERSION EFFECIENCY OF POWER CONVERTERS - Power switch controllers and methods used therein are disclosed. An exemplifying power switch controller includes a window provider, a sensor and a logic controller. The window provider provides minimum and maximum time signals to indicate the elapses of a minimum time and a maximum time, respectively. The sensor detects a terminal of an inductive device, to generate a trigger signal. The logic controller prevents a power switch connected to the inductive device from being turned on before the elapse of the minimum time, forces the power switch to be turned on after the elapse of the maximum time, and turns on the power switch if the trigger signal is asserted. | 12-20-2012 |
20130033211 | SWITCHING-MODE POWER SUPPLIES AND CONTROL METHODS THEREOF - Disclosed include switching-mode power supplies and control methods thereof. A disclosed switching-mode power supply is coupled to an input power node and a ground node, comprising a controller, a first inductor, and a bootstrap circuit. The controller is for controlling a power switch coupled to the input power node and a connection node. The controller is powered by the connection node and an operation power node. The first inductor is coupled between the connection node and a discharge node. The bootstrap circuit is coupled between the discharge node, the operation power node and the connection node, to make an operation voltage at the operation power node substantially not less than a discharge voltage at the discharge node. The discharge node is coupled to power an output load. | 02-07-2013 |
20130334975 | Controllers and Light Modules with Light Emitting Diodes - Disclosed are a controller and a relevant LED lighting module. A disclosed controller comprises a high-voltage power terminal and a low-voltage power terminal, a major switch circuit, an upward-connection terminal and a downward-connection terminal, and a management circuit. The major switch circuit is coupled between the high-voltage and low-voltage power terminals, and has a driving terminal for coupling to at least one LED. The management circuit is coupled to control the major switch circuit, and configured to communicate with an upstream controller via the upward-connection terminal and to communicate with a downstream controller via the downward-connection terminal. The upward-connection terminal is coupled to the downward-connection terminal of an upstream controller. The downward-connection terminal is coupled to the upward-connection terminal of a downstream controller. The management circuit is capable of operating in one of operation conditions. | 12-19-2013 |