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Chien-Liang Chen
Chien-Liang Chen, Changhua County TW
| Patent application number | Description | Published |
|---|---|---|
| 20100134234 | SHIFT REGISTER APPARATUS - A shift register apparatus is provided. The pull-down unit of each of the shift registers in the shift register apparatus is controlled by itself, previous, and next two shift registers to enhance the ability of pull-down and voltage regulating. Therefore, the circuit structure of each of the shift registers does not need to be designed a large compensation capacitor therein to substantially restrain the coupling noise effect caused by the clock signal, and thus permitting that each of the shift registers can be collocated with a small compensation capacitor to enhance the output capability thereof. | 06-03-2010 |
| 20100302178 | TOUCH PANEL DISPLAY - A touch panel display including a first substrate, a second substrate, a display medium and a touch device is provided. The first substrate has a display area and a peripheral area. The first substrate has a pixel array in the display area and at least one integrated driving circuit in the peripheral area. The integrated driving circuit is electrically connected to the pixel array. The second substrate is disposed above the first substrate to cover the integrated driving circuit and the pixel array. The display medium is disposed on the pixel array and located between the first substrate and the second substrate. The touch device is disposed on the second substrate, and has a sensor element and a wiring element connected to the sensor element. The sensor element is located above the pixel array and the wiring element is located above at least a portion of the integrated driving circuit. | 12-02-2010 |
| 20110102310 | SHIFT REGISTER WITH IMAGE RETENTION RELEASE AND METHOD FOR IMAGE RETENTION RELEASE - A flat panel display, a shift register with image retention release and method for releasing image retention are provided. An output end of the shift register couples to a gate line of a display panel. A first end of a first transistor couples to the output end of the shift register. A second end of the first transistor couples to a system voltage VDD or a reference voltage VSS. A first end of a capacitor couples to a control end of the first transistor. A second end of the capacitor couples to the reference voltage VSS. During a power-off period, the reference voltage VSS is pulled high for turning on the first transistor, therefore the voltage of the gate line is pulled high. | 05-05-2011 |
Chien-Liang Chen, Hsin-Chu TW
| Patent application number | Description | Published |
|---|---|---|
| 20080308873 | Semiconductor device with discontinuous CESL structure - A semiconductor device using a CESL (contact etch stop layer) to induce strain in, for example, a CMOS transistor channel, and a method for fabricating such a device. A stress-producing CESL, tensile in an n-channel device and compressive in a p-channel device, is formed over the device gate structure as a discontinuous layer. This may be done, for example, by depositing an appropriate CESL, then forming an ILD layer, and simultaneously reducing the ILD layer and the CESL to a desired level. The discontinuity preferably exposes the gate electrode, or the metal contact region formed on it, if present. The upper boundary of the CESL may be further reduced, however, to position it below the upper boundary of the gate electrode. | 12-18-2008 |
| 20100038692 | Integrating the Formation of I/O and Core MOS Devices with MOS Capacitors and Resistors - An integrated circuit structure includes a semiconductor substrate, and a first and a second MOS device. The first MOS device includes a first gate dielectric over the semiconductor substrate, wherein the first gate dielectric is planar; and a first gate electrode over the first gate dielectric. The second MOS device includes a second gate dielectric over the semiconductor substrate; and a second gate electrode over the second gate dielectric. The second gate electrode has a height greater than a height of the first gate electrode. The second gate dielectric includes a planar portion underlying the second gate electrode, and sidewall portions extending on sidewalls of the second gate electrode. | 02-18-2010 |
| 20100231497 | DISPLAY DEVICE PROVIDING BI-DIRECTIONAL VOLTAGE STABILIZATION - An LCD device includes a plurality of gate lines and a plurality of shift register units for driving corresponding gate lines. Each shift register unit includes a first circuit and a second circuit. The first circuit, disposed on a first side of a corresponding gate line, includes a pulse generator and a first transistor having a first W/L ratio. The pulse generator provides a driving signal according to the voltage obtained at a node, while the first transistor maintains the voltage level of the node. The second circuit, disposed on a second side of the corresponding gate line, includes a second transistor having a second W/L ratio. The second transistor maintains the voltage level of the driving signal from the second side of the corresponding gate line. The first W/L ratio is smaller than the second W/L ratio, and the first circuit occupies larger space than the second circuit. | 09-16-2010 |
| 20110085098 | ARRAY SUBSTRATE AND FLAT DISPLAY DEVICE - A flat display device includes an array substrate. The array substrate includes a plurality of gate lines, data lines and pixels. The pixels include a plurality of first pixel units and second pixel units, and each of the first pixel units and each of the second pixel units include more than three pixels. The first pixel units and the second pixel units disposed in between two adjacent data lines are arranged alternately, wherein the first pixel units are electrically connected with one of the two adjacent data lines, and the second pixel units are electrically connected with the other data line. | 04-14-2011 |
Chien-Liang Chen, Kaohsiung City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110080661 | LENS DISPLACEMENT DEVICE, FLEXIBLE PIECE AND THE MANUFACTURING PROCESS THEREOF - A lens displacement device includes a flexible piece, a fixed element and a mobile element. The flexible piece has a support, a flexible part and an oscillation absorber. The flexible part connects to the support and at least one gap exists between the flexible part and the support. The oscillation absorber is installed in the gap between the flexible part and the support. Moreover, the fixed element couples to the support of the flexible piece, and the mobile element couples to the flexible part of the flexible piece. Furthermore, the flexible part of the flexible piece is deformed in shape for providing a restoration force with the mobile element. A manufacturing process of the flexible piece is also disclosed. | 04-07-2011 |
Chien-Liang Chen, Hsinchu TW
| Patent application number | Description | Published |
|---|---|---|
| 20110044014 | Flexible Printed Circuit and Display Module Comprising the Same - A flexible printed circuit and a display module comprising the flexible printed circuit are disclosed. The display module comprises a display panel, a printed circuit board, and a flexible printed circuit. The flexible printed circuit electrically connects the display panel and the printed circuit board, and further comprises a flexible substrate and a cover lay. The flexible substrate has an upper surface and two opposite end portions. The cover lay is disposed on the upper surface of the flexible substrate and extends along a lengthwise direction of the flexible substrate. The cover lay further has two opposite sides each also extending along the lengthwise direction of the flexible substrate. Each of the sides has at least a partially continuous contour which is formed with a discontinuous status on at least one of the end portions. | 02-24-2011 |
Chien-Liang Chen, Taipei Hsien TW
| Patent application number | Description | Published |
|---|---|---|
| 20100191985 | Power signal detecting system, method and a portable electronic device thereof - A power signal detecting system and method thereof are disclosed. The power signal detecting system comprises a power supply and a portable electronic device. The portable electronic device is electrically connected with the power supply to receive a power signal. The portable electronic device comprises a sensing element, a detecting module and a power management module. The sensing element is used to connect the power signal. The detecting module is electrically connected to the sensing element and is used for detecting the power signal. The power management module electrically connects to the detecting module and is used for executing a power management for the portable electronic device by identifying the power signal. | 07-29-2010 |
| 20110006735 | Portable Computer System and Related Power Supply Device and Charging Method - A portable computer system includes a host, a power storage device and a dock. The power storage device is installed in the host, for sensing current from a first power socket to a first power terminal to generate a first sensing result, and charging a first rechargeable battery according to a first control signal. The dock is capable of connecting to the host by means of insertion, for sensing current from a second power socket to a second power terminal to generate a second sensing result, and charging a second rechargeable battery according to a second control signal. The dock includes a control device for outputting the first control signal and the second control signal according to the first sensing result and the second sensing result, to control charging operations on the first rechargeable battery and the second rechargeable battery. | 01-13-2011 |
Chien-Liang Chen, Yunlin County TW
| Patent application number | Description | Published |
|---|---|---|
| 20100134124 | MISALIGNMENT DETECTION DEVICES - A misalignment detection device comprising a substrate, at least one integrated circuit (IC), and at least one detection unit is disclosed. The substrate comprises a first positioning pad and a second positioning pad adjacent to the first positioning pad. The integrated circuit is disposed on the substrate and comprises a first positioning bump and a second positioning bump adjacent to the first positioning bump. The first and second positioning bumps substantially correspond to the first and second positioning pads, respectively. The at least one detection unit is electrically coupled to the substrate, wherein the detection unit outputs a fault signal in response to a positioning shift occurring between the first and second positioning pads and the first and second positioning bumps. | 06-03-2010 |
Chien-Liang Chen, Hsinchu City TW
| Patent application number | Description | Published |
|---|---|---|
| 20090039433 | SEMICONDUCTOR DEVICE WITH HIGH-K/DUAL METAL GATE - An apparatus, and method of manufacture thereof, comprising a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first gate electrode having a first metal layer forming a first trench and a second metal layer filling the first trench, wherein the first and second metal layers have substantially different metallic compositions. The second semiconductor device includes a second gate electrode having a third metal layer forming a second trench and a fourth metal layer filling the second trench, wherein the third and fourth metal layers have substantially different metallic compositions, and wherein the first and third metal layers have substantially different metallic compositions. | 02-12-2009 |
| 20100044803 | SEALING STRUCTURE FOR HIGH-K METAL GATE AND METHOD OF MAKING - The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer. | 02-25-2010 |
| 20100052072 | DUAL GATE STRUCTURE ON A SAME CHIP FOR HIGH-K METAL GATE TECHNOLOGY - A semiconductor device and method for fabricating a semiconductor device is disclosed. The method includes providing semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a metal layer over the capping layer, removing the metal layer and capping layer in the second region, forming a polysilicon layer over the metal layer in the first region and over the high-k dielectric layer in the second region, and forming an active device with the metal layer in the first region and forming a passive device without the metal layer in the second region. | 03-04-2010 |
| 20100109088 | BALANCE STEP-HEIGHT SELECTIVE BI-CHANNEL STRUCTURE ON HKMG DEVICES - The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region. | 05-06-2010 |
| 20110278646 | Balance Step-Height Selective Bi-Channel Structure on HKMG Devices - The present disclosure provides a method including forming STI features in a silicon substrate, defining a first and a second active regions for a PFET and an NFET, respectively; forming a hard mask having an opening to expose the silicon substrate within the first active region; etching the silicon substrate through the opening to form a recess within the first active region; growing a SiGe layer in the recess such that a top surface of the SiGe layer within the first active region and a top surface of the silicon substrate within the second active region are substantially coplanar; forming metal gate material layers; patterning the metal gate material layers to form a metal gate stack on the SiGe layer within the first active region; and forming an eSiGe S/D stressor distributed in both the SiGe layer and the silicon substrate within the first active region. | 11-17-2011 |
Chien-Liang Chen, Hsinchu Hsien TW
| Patent application number | Description | Published |
|---|---|---|
| 20090217069 | Power Management Method for a Multi-Microprocessor System - A power management method for a multi-microprocessor system is provided. The multi-microprocessor system comprises a first microprocessor and a second microprocessor. The power management method comprises steps of receiving a power down instruction; transmitting a power down notice signal to the first microprocessor from the second microprocessor, transmitting a reply signal from the first microprocessor to the second microprocessor in response to the power down notice signal, and turning off power of the first microprocessor by the second microprocessor. | 08-27-2009 |
| 20120023342 | Power Management Method for a Multi-Microprocessor System - A power management method for a multi-microprocessor system is provided. The multi-microprocessor system comprises a first microprocessor and a second microprocessor. The power management method comprises steps of receiving a power down instruction; transmitting a power down notice signal to the first microprocessor from the second microprocessor, transmitting a reply signal from the first microprocessor to the second microprocessor in response to the power down notice signal, and turning off power of the first microprocessor by the second microprocessor. | 01-26-2012 |
Chien-Liang Chen, Taipei TW
| Patent application number | Description | Published |
|---|---|---|
| 20090116266 | PARALLELED POWER CONDITIONING SYSTEM WITH CIRCULATING CURRENT FILTER - This present invention relates to a paralleled power conditioning system with circulating current filter, comprising: an input terminal for receiving a input power; a plurality of power conditioning units; and a load. Each power conditioning unit includes: a DC/DC converter coupled to the input for receiving the input power so as to convert the input power to a DC voltage; a DC/AC inverter coupled to the DC/DC converter for converting the DC voltage to a AC voltage; and a filter coupled to the DC/AC inverter for eliminating the noise generated by the AC voltage and the circulating current among the plurality of power conditioning units so as to generate a filter voltage. The load is connected to the plurality of power conditioning units. The plurality of power conditioning units are connected in parallel to the load. | 05-07-2009 |
| 20110245626 | System for human physical parameters examination - A system for detecting and recording a user's physical parameters, an interactive TV receiver connected to an information network system for receiving physical parameters data detected by the physical parameter scanner and transmitting the data to a rear end server and database through the information network system for enabling a remote user, remote hospital or remote pharmacy to trace patient's physical conditions and to provide the necessary medication services. | 10-06-2011 |
Chien-Liang Chen, Hsinchu County TW
| Patent application number | Description | Published |
|---|---|---|
| 20090096802 | APPARATUS AND METHOD FOR PROGRAMMING FUNCTIONS OF DISPLAY - The present invention provides an apparatus for programming functions of a display. The apparatus comprises a memory, a programming device, and a program code checking unit. The memory is for storing a program code. The programming device coupled to the memory is for reading the program code with a predetermined length from the memory. The program code with the predetermined length is part of the program code. The program code checking unit coupled to the programming device is for checking whether the program code with the predetermined length is consistent with a predetermined state, and for selectively generating a control signal. Under control of the control signal, the programming device determines whether to write the program code with the predetermined length into a memory of the display. | 04-16-2009 |
Chien-Liang Chen, Blacksburg, VA US
| Patent application number | Description | Published |
|---|---|---|
| 20080205096 | CONTROL SYSTEM AND METHOD FOR A UNIVERSAL POWER CONDITIONING SYSTEM - A new current loop control system method is proposed for a single-phase grid-tie power conditioning system that can be used under a standalone or a grid-tie mode. This type of inverter utilizes an inductor-capacitor-inductor (LCL) filter as the interface in between inverter and the utility grid. The first set of inductor-capacitor (LC) can be used in the standalone mode, and the complete LCL can be used for the grid-tie mode. A new admittance compensation technique is proposed for the controller design to avoid low stability margin while maintaining sufficient gain at the fundamental frequency. The proposed current loop controller system and admittance compensation technique have been simulated and tested. Simulation results indicate that without the admittance path compensation, the current loop controller output duty cycle is largely offset by an undesired admittance path. At the initial simulation cycle, the power flow may be erratically fed back to the inverter causing catastrophic failure. With admittance path compensation, the output power shows a steady-state offset that matches the design value. Experimental results show that the inverter is capable of both a standalone and a grid-tie connection mode using the LCL filter configuration. | 08-28-2008 |
Chien-Liang Chen, Banqiao City TW
| Patent application number | Description | Published |
|---|---|---|
| 20110158108 | ETHERENT PHYSICAL LAYER TEST SYSTEM AND METHOD - An Ethernet physical layer test system and method, wherein a signal pattern generator is utilized to generate repeatedly a signal pattern frame required by the test items of the Ethernet physical layer according to a transmission procedure of a medium access controller; meanwhile, the signal pattern generator generates a control signal for switching a multiplexer, so as to control the transmission of a signal pattern frame. The Ethernet physical layer receives the signal pattern frame and outputs a test packet to a measurement instrument via a twisted-pair, for testing and analyzing quality of signals output by the Ethernet physical layer. Through the application of this Ethernet physical layer test system and method, the time required for testing the Ethernet physical layer can be effectively reduced, thus simplifying the complexity of an algorithm in testing the Ethernet physical layer. | 06-30-2011 |
Chien-Liang Chen, New Taipei City TW
| Patent application number | Description | Published |
|---|---|---|
| 20120043926 | Power Management Device, Power Management Method and Portable Electronic Device - A power management device for a portable electronic device includes a sensing unit, coupled between a power supply and a system circuit of the portable electronic device, for sensing current outputted from the power supply to the system circuit, to generate a sensing signal, and a control unit, coupled between the sensing unit and a charger module of the portable electronic device, for indicating the charger module to stop charging when the sensing signal indicates that current outputted from the power supply to the system circuit is greater than a predetermined value. | 02-23-2012 |