Patent application number | Description | Published |
20080220341 | MASK PATTERN AND METHOD FOR FORMING THE SAME - The invention provides a mask pattern. The mask pattern comprises at least a continuous pattern. Each of the continuous patterns has a first pattern, a second pattern and a set of assistance patterns. The assistant patterns are located between the first pattern to the second pattern. The first pattern, the assistant patterns and the second pattern together form a closed opening. | 09-11-2008 |
20090014717 | TEST IC STRUCTURE - A test IC structure is described, which is disposed in a scribe line region of a wafer and includes first and second test keys, first and second conductive plugs, first and second test pads, and a passivation layer over the scribe line region. The first/second test key includes a first/second active device and a first/second interconnect structure electrically connected thereto, wherein the second test key is arranged substantially parallel with the first one. The first/second plug is disposed over the first/second interconnect structure and contacts with the upmost metal layer thereof. The first/second test pad is disposed over the first and the second test keys and contacts with the first/second conductive plug. The passivation layer has therein a first opening exposing a portion of the first test pad and a second opening exposing a portion of the second test pad. | 01-15-2009 |
20090079439 | EFUSE SYSTEM AND TESTING METHOD THEREOF - An eFuse system and a method for testing the eFuse system are provided. The eFuse system includes an eFuse, a sensing circuit, and an offset resistor. The sensing circuit has a trigger point resistance and is coupled to a first end of the eFuse for sensing the resistance of the eFuse, wherein the resistance depends on whether the eFuse is blown or not. Accordingly, the sensing circuit outputs a first signal if the sensed resistance is greater than the trigger point resistance and outputs a second signal if the sensed resistance is less than the trigger point resistance. The offset resistor is coupled to a second end of the eFuse for compensating a shift on the trigger point resistance of the sensing circuit due to temperature change. | 03-26-2009 |
20090236583 | Method of fabricating a phase change memory and phase change memory - The present invention relates to a phase change memory and a method of fabricating a phase change memory. The phase change memory includes a heater structure disposed on a phase change material pattern, wherein the heater structure is in a tapered shape with a bottom portion contacting the phase change material pattern. The fabrication of the phase change memory is compatible with the fabrication of logic devices, and accordingly an embedded phase change memory can be fabricated. | 09-24-2009 |
20100012916 | PHASE CHANGE MEMORY - A phase change memory and the method for manufacturing the same are disclosed. The phase change memory includes a word line, a phase change element, a plurality of heating parts, and a plurality of bit lines. The phase change material layer is electrically connected to the word line and the heating parts. Each heating part is electrically connected to a respective bit line. | 01-21-2010 |
20100135093 | OPERATING VOLTAGE TUNING METHOD FOR STATIC RANDOM ACCESS MEMORY - An operating voltage tuning method for a static random access memory is disclosed. The static random access memory receives a periphery voltage and a memory cell voltage. The steps of the method mentioned above are shown as follows. First, perform a shmoo test on the static random access memory to obtain a shmoo test plot and a minimum operating voltage. Compare the minimum operating voltage with a preset specification. Position a specification position point on the line which the periphery voltage is equal to the memory cell voltage in the shmoo test plot corresponding to the preset specification. Fix one of the memory cell voltage and the periphery voltage and gradually decrease the other to test the static random access memory and obtain a failure bits distribution. Finally, tune process parameters of the static random access memory according to the specification position point and the failure bits distribution. | 06-03-2010 |
20120112782 | METHOD FOR PREDICTING TOLERABLE SPACING BETWEEN CONDUCTORS IN SEMICONDUCTOR PROCESS - A method for predicting tolerable contact-to-gate spacing is provided. At first, a wafer with a plurality of source/drain contacts are provided. Then, a plurality of testing gate lines are formed on the wafer by using a photomask. In one die, there are different contact-to-gate distances ranging from d+Δd to d−Δd wherein d is the standard spacing and Δd05-10-2012 | |
20140061855 | CAPACITOR STRUCTURE AND FABRICATING METHOD THEREOF - A capacitor structure includes a first conductive structure, a dielectric structure, a first capacitor electrode, a capacitor dielectric layer, and a second capacitor electrode. The first conductive structure is disposed over a substrate. The dielectric structure is disposed over the substrate and partially enclosing the first conductive structure. The dielectric structure has a trench. A first surface of the first conductive structure is exposed through the trench of the dielectric structure. The first capacitor electrode is disposed on a bottom and a sidewall of the trench. The first capacitor electrode is electrically contacted with the first surface of the first conductive structure. The capacitor dielectric layer is disposed on a surface of the first capacitor electrode. The second capacitor electrode is disposed on a surface of the capacitor dielectric layer and filled in the trench. | 03-06-2014 |