Patent application number | Description | Published |
20090295439 | Phase Lock Loop (PLL) with Gain Control - A Phase Lock Loop (PLL) with gain control is provided. The PLL has a dual-path configuration, where a first and a second VCO control voltage are generated in response to a phase or frequency difference between a PLL input signal and an output signal. The PLL comprises a dynamic voltage gain control (DVGC) unit and a voltage-to-current (V2I) unit, where the DVGC creates a baseline reference current in response to the first VCO control voltage and the V2I provides a substantially linear current in response to the second VCO control voltage. The currents from the DVGC and V2I are combined and fed into a current-controlled oscillator, which generates a PLL output frequency signal. Frequency gain of the VCO is substantially reduced, thus providing a PLL with improved tuning precision. | 12-03-2009 |
20100077192 | COMPUTER, BOOTING SOFTWARE PRODUCT AND COMPUTER BOOTING METHOD - A computer includes an application system, a storage device and a basic input output system (BIOS). The application system can be respectively coupled to the storage device and the BIOS, set at least a multimedia file as a preset playing file according to an input instruction and store the preset playing file into the storage device. The application system can further generate a log file according to the input instruction and the storage position of the preset playing file, wherein the log file is sent to the BIOS. The BIOS has a file access module, so that the BIOS can acquire the preset playing file from the storage device according to the log file for playing during booting the computer. | 03-25-2010 |
20100141346 | Phase-Locked Loop with Start-Up Circuit - A circuit includes a voltage-controlled oscillator (VCO), which includes a voltage input node having an input voltage; and a start-up circuit. The start-up circuit includes a first current path and a second current path. The first current path has a first current and is configured so that the first current increases in response to a decrease in the input voltage and decreases in response to an increase in the input voltage. The second current path has a second current and is configured so that the second current decreases in response to the decrease in the input voltage and decreases in response to the increase in the input voltage. The VCO further includes a third current path combining a first proportion of the first current and a second proportion of the second current into a combined current; and a current-controlled oscillator (CCO) including an input receiving the combined current and outputting an AC signal. | 06-10-2010 |
20100176777 | Constant Gm Circuit and Methods - Structures and methods for providing a temperature independent constant current reference are provided. A constant Gm circuit is disclosed with embodiments including a voltage controlled resistor providing a current into a current mirror, the current mirror sinking a reference current at its output. By providing a feedback loop that controls the voltage controlled resistor, a temperature compensated circuit may be obtained. The temperature dependence of the voltage controlled resistor is positive and the feedback circuitry maintains this resistor at a value that compensates for the negative temperature dependence of the current mirror circuit. The reference current is thus obtained at a predetermined level independent of temperature. A method for providing a reference current is disclosed wherein a voltage dependent resistor is provided supply current to a current mirror, the voltage dependent resistor receiving a feedback voltage from the current mirror and the feedback controlling the resistor so that a temperature independent reference current is obtained. | 07-15-2010 |
20110080220 | TEMPERATURE COMPENSATED INTEGRATOR - A representative integrator includes an amplifier having an input and an output; a feedback loop coupled between the input and the output of the amplifier, the feedback loop comprising a compensated resistor circuit having a resistance value selected for reducing a loss factor of the integrator; and a control circuit coupled to an input of the compensated resistor circuit, the control circuit producing a control signal for controlling the compensated resistor circuit to substantially maintain the resistance value selected for reducing the loss factor of the integrator across a range of integrator temperatures. | 04-07-2011 |
20110099493 | IMAGE AUXILIARY DATA SEARCHING AND DISPLAYING METHOD AND DOCUMENT CAMERA USING SUCH METHOD - An image auxiliary data searching and displaying method is used in a document camera. The document camera includes a processor and a user interface. The processor is accessible to a database. The image auxiliary data searching and displaying method includes steps of performing an image-selecting operation on an image of the to-be-displayed object via the user interface to generate a target image, processing the target image by the processor to generate a target characteristic property, searching the database by the processor according to the target characteristic property so as to generate a search result, and simultaneously displaying at least one image auxiliary data from the search result and the image of the to-be-displayed object for comparison. | 04-28-2011 |
20110221494 | PHASE-LOCKED LOOP START UP CIRCUIT - A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator (VCO) having a VCO input for receiving a control voltage and a VCO output, a feedback loop between the VCO input and the VCO output, and a start-up circuit having a start-up circuit input and a start-up circuit output. The start-up circuit output is coupled to the VCO input and the start-up circuit input is coupled to the VCO output. The start-up circuit provides a voltage at its start-up circuit output during a start-up phase, which terminates after a predetermined number of feedback pulses are detected by the start-up circuit. | 09-15-2011 |
20110281829 | NOVEL COMPOSITION - This disclosure relates to a pharmaceutical composition that includes a first agent selected from the group consisting of an oxidative phosphorylation inhibitor, an ionophore, and an adenosine 5′-monophosphate-activated protein kinase (AMPK) activator; a second agent that possesses anti-inflammatory activity; and a third agent that is a serotonin metabolite. | 11-17-2011 |
20130185689 | METHOD OF AND SYSTEM FOR GENERATING OPTIMIZED SEMICONDUCTOR COMPONENT LAYOUT - A method of generating an optimized layout of semiconductor components in conformance with a set of design rules includes generating, for a unit cell including one or more semiconductor components, a plurality of configurations each of which satisfies some, but not all, of the design rules. For each configuration, it is checked whether a layout, which is a repeating pattern of the unit cell, satisfies the remaining design rules. Among the configurations which satisfy all of the design rules, the configuration providing an optimal value of a property is selected for generating the optimized layout of the semiconductor components. | 07-18-2013 |
20130187686 | FLIP-FLOP CIRCUIT, FREQUENCY DIVIDER AND FREQUENCY DIVIDING METHOD - In response to a first level of the clock signal, an inverting output of a flip-flop circuit is connected, via a non-inverting input thereof, to a first intermediate node of the flip-flop circuit and a non-inverting output of the flip-flop circuit is connected, via an inverting input thereof, to a second intermediate node of the flip-flop circuit. In response to a second level of the clock signal, the first intermediate node is connected, via a third intermediate node of the flip-flop circuit, to the non-inverting output and the second intermediate node is connected, via a fourth intermediate node of the flip-flop circuit, to the inverting output. A first cross-coupled gates arrangement of the flip-flop circuit is coupled between the first and second intermediate nodes. A second cross-coupled gates arrangement of the flip-flop circuit is coupled between the third and fourth intermediate nodes. | 07-25-2013 |
20130198710 | SEMICONDUCTOR DEVICE FEATURE DENSITY GRADIENT VERIFICATION - A method for verifying that acceptable device feature gradients and device feature disparities are present in a semiconductor device layout, is provided. The method provides for dividing a device layout into a plurality of windows and measuring or otherwise determining the device feature density within each window. The device layout includes various device regions and the method provides for comparing an average device feature density within one region to surrounding areas or other regions and also for determining gradients of device feature densities. The gradients may be monitored from within a particular device region to surrounding regions. Instructions for carrying out the method may be stored on a computer readable storage medium and executed by a processor. | 08-01-2013 |
20130292754 | CAPACITOR AND METHOD OF FORMING SAME - A device comprises a substrate having at least one active region, an insulating layer above the substrate, and an electrode in a gate electrode layer above the insulating layer, forming a metal-oxide-semiconductor (MOS) capacitor. A first contact layer is provided on the electrode, having an elongated first pattern extending in a first direction parallel to the electrode. A contact structure contacts the substrate. The contact structure has an elongated second pattern extending parallel to the first pattern. A dielectric material is provided between the first and second patterns, so that the first and second patterns and dielectric material form a side-wall capacitor connected in parallel to the MOS capacitor. | 11-07-2013 |
20130346935 | SEMICONDUCTOR DEVICE FEATURE DENSITY GRADIENT VERIFICATION - A method for verifying that acceptable device feature gradients and device feature disparities are present in a semiconductor device layout, is provided. The method provides for dividing a device layout into a plurality of windows and measuring or otherwise determining the device feature density within each window. The device layout includes various device regions and the method provides for comparing an average device feature density within one region to surrounding areas or other regions and also for determining gradients of device feature densities. The gradients may be monitored from within a particular device region to surrounding regions. Instructions for carrying out the method may be stored on a computer readable storage medium and executed by a processor. | 12-26-2013 |
20140084771 | ELECTRONIC DEVICE AND MOVABLE FIXING STRUCUTRE THEREOF - A movable fixing structure is used for causing the first casing to be combined with or detached from the second casing along a first axial direction. The movable fixing structure includes a blocking component, a locating element and a limiting element. The blocking component is movably disposed on the first casing along a second axial direction. The blocking component is used for moving between a first position and a second position. The locating element has a first locating portion and a second locating portion. The locating element is disposed on the first casing and is used for moving between a third and a fourth position along a third axial direction. The limiting element is disposed on the second casing and is used for interfering with the second locating portion on the first axial direction. | 03-27-2014 |
20140087579 | CONNECTOR COMPONENT AND PORTABLE ELECTRONIC DEVICE HAVING THEREOF - A connector component that is used for connecting a first electronic device and a second electronic device via the connector component is provided. The connector component includes a first connection component, a second connection component and fixing element. The first connection component electronically extends from the first electronic device and has a fastening portion. The second connection component is disposed in the second electronic device. The fixing element is disposed in the second electronic device and is located next to the second connection component. When the first connection component is coupled to the second connection component, the fixing element is fastened with the fixing portion, so as to fix the first connection component to the second connection component. | 03-27-2014 |
20140356052 | HOT MELT ASSEMBLY STRUCTURE AND ASSEMBLY METHOD THEREOF - A hot melt assembly structure includes a support member and an assembly member. The support member has a hot melt hole and at least one rib adjacent to the hot melt hole. The assembly member includes a main body and a hot melt body connected to the main body. The hot melt body includes a neck part and a cap part. The neck part connects the main body with the cap part. The neck part is disposed through the hot melt hole and the cap part leans against the rib. | 12-04-2014 |