| Patent application number | Description | Published |
| 20090295439 | Phase Lock Loop (PLL) with Gain Control - A Phase Lock Loop (PLL) with gain control is provided. The PLL has a dual-path configuration, where a first and a second VCO control voltage are generated in response to a phase or frequency difference between a PLL input signal and an output signal. The PLL comprises a dynamic voltage gain control (DVGC) unit and a voltage-to-current (V2I) unit, where the DVGC creates a baseline reference current in response to the first VCO control voltage and the V2I provides a substantially linear current in response to the second VCO control voltage. The currents from the DVGC and V2I are combined and fed into a current-controlled oscillator, which generates a PLL output frequency signal. Frequency gain of the VCO is substantially reduced, thus providing a PLL with improved tuning precision. | 12-03-2009 |
| 20100077192 | COMPUTER, BOOTING SOFTWARE PRODUCT AND COMPUTER BOOTING METHOD - A computer includes an application system, a storage device and a basic input output system (BIOS). The application system can be respectively coupled to the storage device and the BIOS, set at least a multimedia file as a preset playing file according to an input instruction and store the preset playing file into the storage device. The application system can further generate a log file according to the input instruction and the storage position of the preset playing file, wherein the log file is sent to the BIOS. The BIOS has a file access module, so that the BIOS can acquire the preset playing file from the storage device according to the log file for playing during booting the computer. | 03-25-2010 |
| 20100141346 | Phase-Locked Loop with Start-Up Circuit - A circuit includes a voltage-controlled oscillator (VCO), which includes a voltage input node having an input voltage; and a start-up circuit. The start-up circuit includes a first current path and a second current path. The first current path has a first current and is configured so that the first current increases in response to a decrease in the input voltage and decreases in response to an increase in the input voltage. The second current path has a second current and is configured so that the second current decreases in response to the decrease in the input voltage and decreases in response to the increase in the input voltage. The VCO further includes a third current path combining a first proportion of the first current and a second proportion of the second current into a combined current; and a current-controlled oscillator (CCO) including an input receiving the combined current and outputting an AC signal. | 06-10-2010 |
| 20100176777 | Constant Gm Circuit and Methods - Structures and methods for providing a temperature independent constant current reference are provided. A constant Gm circuit is disclosed with embodiments including a voltage controlled resistor providing a current into a current mirror, the current mirror sinking a reference current at its output. By providing a feedback loop that controls the voltage controlled resistor, a temperature compensated circuit may be obtained. The temperature dependence of the voltage controlled resistor is positive and the feedback circuitry maintains this resistor at a value that compensates for the negative temperature dependence of the current mirror circuit. The reference current is thus obtained at a predetermined level independent of temperature. A method for providing a reference current is disclosed wherein a voltage dependent resistor is provided supply current to a current mirror, the voltage dependent resistor receiving a feedback voltage from the current mirror and the feedback controlling the resistor so that a temperature independent reference current is obtained. | 07-15-2010 |
| 20110080220 | TEMPERATURE COMPENSATED INTEGRATOR - A representative integrator includes an amplifier having an input and an output; a feedback loop coupled between the input and the output of the amplifier, the feedback loop comprising a compensated resistor circuit having a resistance value selected for reducing a loss factor of the integrator; and a control circuit coupled to an input of the compensated resistor circuit, the control circuit producing a control signal for controlling the compensated resistor circuit to substantially maintain the resistance value selected for reducing the loss factor of the integrator across a range of integrator temperatures. | 04-07-2011 |
| 20110099493 | IMAGE AUXILIARY DATA SEARCHING AND DISPLAYING METHOD AND DOCUMENT CAMERA USING SUCH METHOD - An image auxiliary data searching and displaying method is used in a document camera. The document camera includes a processor and a user interface. The processor is accessible to a database. The image auxiliary data searching and displaying method includes steps of performing an image-selecting operation on an image of the to-be-displayed object via the user interface to generate a target image, processing the target image by the processor to generate a target characteristic property, searching the database by the processor according to the target characteristic property so as to generate a search result, and simultaneously displaying at least one image auxiliary data from the search result and the image of the to-be-displayed object for comparison. | 04-28-2011 |
| 20110221494 | PHASE-LOCKED LOOP START UP CIRCUIT - A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator (VCO) having a VCO input for receiving a control voltage and a VCO output, a feedback loop between the VCO input and the VCO output, and a start-up circuit having a start-up circuit input and a start-up circuit output. The start-up circuit output is coupled to the VCO input and the start-up circuit input is coupled to the VCO output. The start-up circuit provides a voltage at its start-up circuit output during a start-up phase, which terminates after a predetermined number of feedback pulses are detected by the start-up circuit. | 09-15-2011 |
| 20110281829 | NOVEL COMPOSITION - This disclosure relates to a pharmaceutical composition that includes a first agent selected from the group consisting of an oxidative phosphorylation inhibitor, an ionophore, and an adenosine 5′-monophosphate-activated protein kinase (AMPK) activator; a second agent that possesses anti-inflammatory activity; and a third agent that is a serotonin metabolite. | 11-17-2011 |
| Patent application number | Description | Published |
| 20100061646 | IMAGE PROCESSING METHOD - An image processing method is provided. The image processing method includes obtaining a least significant bit (LSB) associated with a pixel block. Further, two bits are reduced from a bit number of each of the pixels of the pixel block. Thereafter whether to carry the pixel or not is determined according to the LSB. When the LSB is 01 or 11, the carry manners of each pixel of the pixel block in two consecutive frames are asymmetric one to another. Further, under the conditions of when the LSB is 01 and 11, respectively, the carry manners of the pixels of the pixel block mutually compensate. Therefore, the display performance of a display is improved. | 03-11-2010 |
| 20100245340 | DRIVING DEVICE AND DRIVING METHOD FOR LIQUID CRYSTAL DISPLAY - A driving device and a driving method for an Liquid crystal display are provided. The driving device includes a memory unit, a comparator, a compensation unit, and a selector. The memory unit provides a previous image and a previous comparison result. The comparator compares a present image with the previous image and outputs a present comparison result. The compensation unit processes the present image according to the previous image to generate a plurality of processed present images. The selector selects and outputs one of the present image and the processed present images according to the previous comparison result and the present comparison result. Thereby, the space required in the memory unit is reduced and the image display quality is improved. | 09-30-2010 |
| 20100271277 | Slot Antenna - A slot antenna includes a dielectric substrate, and an antenna body that is formed on the dielectric substrate. The antenna body defines an open loop antenna slot that has first and second ends, and an open loop perturbation slot that extends inwardly from the open loop antenna slot, and that has first and second ends, each of which is connected to a respective one of the first and second ends of the open loop antenna slot. | 10-28-2010 |
| 20100302234 | METHOD OF ESTABLISHING DOF DATA OF 3D IMAGE AND SYSTEM THEREOF - A method and a system of establishing depth of field data of a 3D image, applicable to a 3D image including a first and a second visual image. The system includes a storage module, an offset calculator, and a comparator. An offset vector matrix includes data fields in the same number as that of pixels of a first visual image. An offset calculator divides a reference frame by taking an a | 12-02-2010 |
| 20100322535 | IMAGE TRANSFORMATION METHOD ADAPTED TO COMPUTER PROGRAM PRODUCT AND IMAGE DISPLAY DEVICE - An image transformation method for use in a computer program product and an image display device is provided. In the image transformation method, a two dimensional image and a corresponding depth image are acquired first. A motion process is performed on the two dimensional image to obtain a plurality of motion images according to the depth image and a plurality of gain values. Then, a plurality of view images are provided and an interpolation process is performed on each motion image to obtain the corresponding view image. Finally, a synthesis process is performed on the view images to obtain a three dimensional image. | 12-23-2010 |
| 20110090318 | Method for generating 3D image - A method for generating a 3D image utilizes a background image and an object image. A camera is used for capturing a 2D image including the background image and the object image. The object image is obtained from the 2D image according the background image. Then, an image from a first angle of view and an image from a second angle of view are generated by rendering the background image and the object image. So, the 3D image is generated by interweaving the image from the first angle of view and the image from the second angle of view. | 04-21-2011 |
| 20110149027 | Image processing method - An image processing method including the following steps is provided. First, a two-dimensional original image is received. Next, a plurality of depth values corresponding to the two-dimensional original image are received. Afterwards, a two-dimensional shifting image is obtained according to the depth values and a standard value. A plurality of shifting values exist between the two-dimensional shifting image and the two-dimensional original image, and the shifting values are determined by a plurality of differences between the depth values and the standard value. Thereafter, a three-dimensional image is produced according to the two-dimensional original image and the two-dimensional shifting image. | 06-23-2011 |
| 20110169851 | OVERDRIVING APPARATUS AND METHOD THEREOF - An overdriving apparatus including a memory unit, a position unit and an overdriving unit is provided. The memory unit stores a present frame received and outputs a previous frame stored in the memory unit. The position unit generates pixel position information according to a display control signal of the present frame. The overdriving unit determines a corresponding relationship between several pixel grey values of the present frame and several display areas of a display panel according to the pixel position information, so as to select a corresponding specific table group of each of the pixel grey values from a plurality of overdriving tables. The overdriving unit further generates an overdriving frame by looking up the corresponding specific table group of each of the pixel grey values. | 07-14-2011 |
| 20110187840 | THREE DIMENSIONAL DISPLAY AND METHOD THEREOF - A three dimensional display and a method thereof are provided. The display includes an image display device and a shutter glasses. The image display device receives a video signal to display a left eye frame or a right eye frame, and outputs a shutter synchronization signal according to whether the left eye frame or the right eye frame is displayed. The shutter glasses is coupled to the image display device to open a left eye glass or a right eye glass according to the shutter synchronization signal. Therefore, the display and the method prevents the left eye and the right eye from receiving an incomplete frame. | 08-04-2011 |
| 20120019514 | THREE DIMENSIONAL DISPLAY - A three-dimensional (3D) display including a memory unit, a signal processing unit, a display panel, a pair of shutter glasses and a timing controller is provided. In a first display period of a left eye frame period, the signal processing unit reading and outputting the first display data from the memory unit. In a third display period of a right eye frame period, the signal processing unit reading and outputting the third display data from the memory unit. In a second display period of the left eye frame period and a fourth display period of the right eye frame period, the signal processing unit outputting second display data. The timing controller controlling the shutter glass and driving the display panel according the first display data, the second display data and the third display data. As such, writing-in time and display time of frames can be increased. | 01-26-2012 |
| 20120019515 | DISPLAY METHOD - A display method thereof is provided. The display method includes following steps. In a first display period of a left eye frame period, first display data are read from a memory unit, and the left eye frame is displayed accordingly. In a second display period of the left eye frame period, second display data is provided and a black frame is displayed accordingly. In a third display period of a right eye frame period, third display data are read from the memory unit, and the right eye frame is displayed accordingly. In a fourth display period of the right eye frame period, the second display data is provided and the black frame is displayed accordingly. As such, writing-in time and display time of frames can be increased. | 01-26-2012 |
| Patent application number | Description | Published |
| 20100002431 | BACKLIGHT MODULE - A backlight module including a back cover, a reflector, a lamp supporter, and a number of lamps is provided. The back cover includes a number of holes, an inner face, and an outer face. The reflector is disposed on the inner face and has a number of openings. The openings expose parts of the holes. The lamp supporter has a base substrate and a number of carriers that are connected to the base substrate. The base substrate is assembled to the outer face of the back cover, and the carriers penetrate the holes of the back cover and the openings of the reflector. The lamps are disposed in the carriers, such that the lamps and the base substrate are located at two opposite sides of the back cover. | 01-07-2010 |
| 20100089829 | MEMBRANE CLEANING METHOD AND APPARATUS - A membrane cleaning apparatus comprising two electrode plates and a filtration unit is provided, wherein the filtration unit is disposed between the electrode plates. The filtration unit comprises a supporting plate and a membrane, and the membrane is disposed on the support plate. This invention can effectively clean the fouling on the membrane by applying an electric field in the membrane region and performing a back flushing process on the membrane. Moreover, a membrane cleaning method is also provided. | 04-15-2010 |
| 20100121491 | METHOD FOR TRACKING POLLUTION SOURCE IN PROCESS WATER - A method for tracking a pollution source in process water is presented. Firstly, variation curves of drain water drained from different rinsing tanks are respectively obtained, and a water quality concentration of the drain water drained to a buffer tank is detected, so as to output a water quality variation curve. Then, an analytical comparison is performed on each drain water amount variation curve and the water quality variation curve within a same time interval, so as to output an analytical result of each flow of drain water in a range exceeding a predetermined water quality standard. In this manner, the drain water that exceeds the predetermined water quality standard can be tracked in real-time according to the analytical result, thereby quickly improving the process for discharging the drain water. | 05-13-2010 |
| 20110051328 | ELECTRONIC DEVICE AND SLIDING HINGE THEREOF - A sliding hinge is provide, including a first member, a cover, a bottom cover movable relative to the first member, a sling plate fixed to the bottom cover, and an elastic module. The first member has a main body and a connection portion protruding therefrom, wherein the connection portion has a recess. The cover is fixed to the connection portion, wherein the cover and the first member form a space therebetween to receive the sling plate and the elastic module. The elastic module has an end received in the recess. | 03-03-2011 |
| 20110160042 | METHOD FOR CONSTRUCTING FRACTAL NETWORK STRUCTURE IN HYDROGEN STORAGE MATERIAL - The present invention provides a method for constructing a fractal network structure in hydrogen storage material to improve the hydrogen uptake at room temperature, the method including the following steps: providing a hydrogen storage material comprising a source and a receptor of hydrogen atoms, wherein the source is disposed above the receptor, and a chemical bridge is disposed between the source and the receptor, wherein the chemical bridge is composed of precursor material; and treating the hydrogen storage material to construct a fractal network structure of mesopores and micropores in the receptor, so as to enhance the hydrogen storage capacity of the hydrogen storage material at room temperature. | 06-30-2011 |
| Patent application number | Description | Published |
| 20090190055 | Liquid crystal display device and method for making the same - A method for manufacturing a substrate of a TFT LCD device is disclosed with following steps: providing a transparent substrate having a thin film transistors area and a storing capacitor area; forming an aluminum metal layer and a metal protecting layer on the substrate; patterning a first pattern on the aluminum metal layer of the TFT area, and a second pattern on the metal protecting layer of the storing capacitor area through a halftone mask; forming an aluminum nitride layer on the patterned metal protecting layer; removing the aluminum nitride layer form a rugged surface; forming patterned gates, patterned sources, and patterned drains over the patterned metal protecting layer of the TFT area, and forming a second metal layer over the rugged surface of the aluminum layer on the storing capacitor area, wherein the second metal layer is electrically connected with the drains; and forming patterned pixel electrodes. | 07-30-2009 |
| 20110001916 | LIQUID CRYSTAL DISPLAY DEVICE - A liquid crystal display device is disclosed, which comprises an upper substrate, a lower substrate, and a liquid crystal layer. The lower substrate has several pixel electrodes, metal lines, and switch elements thereon. Each switch element comprises a source electrode, a drain electrode, a gate electrode, and an opening between the source electrode and the drain electrode. A passivation layer covering the surface of the source electrode and the drain electrode forms two inclined planes separately on two sides. The two inclined planes face each other and are locating on a kink or step of the source electrode and drain electrode. The inclined planes also contact each other at the upper side of the opening. The inclinations of the inclined planes to the lower substrate are in a range from 5 to 50 degrees. | 01-06-2011 |
| Patent application number | Description | Published |
| 20080265479 | CLAMPING APPARATUS WITH POSITION VALIDATION FUNCTION AND CLAMPING PROCESS USING SAME - An exemplary clamping apparatus includes a supporting body, a plurality of clamping units installed on the supporting body, a PWM controller, and a detection unit. Each clamping unit includes a magnet, a clamping pin, an electrical coil, and a coil core mechanically engaged with the clamping pin. The magnet is configured for holding the clamping pin at a target position. The PWM controller is configured for supplying a pulse signal to the respective electrical coil of each clamping unit and for thereby creating a magnetic force causing a corresponding coil core and a corresponding clamping pin to, synchronously, move. The detection unit is configured for detecting a back electromotive force representative of the arrival to the target position of a clamping pin and signaling the PWM controller to stop supplying the pulse signal. A clamping process utilizing the clamping apparatus is also provided. | 10-30-2008 |
| 20090011142 | METHOD FOR MANUFACTURING PATTERNED THIN-FILM LAYER - A method for manufacturing a patterned thin-film layer includes the steps of: providing a substrate with a plurality of banks thereon, the plurality of banks defining a plurality of spaces therein for receiving ink therein, each of the banks having a top surface; providing a UV light source for emitting UV light toward the substrate; disposing a photo mask between the UV light source and the substrate; applying UV light on the substrate through the photo mask so as to reduce surface wettability of the ink on the top surfaces of the substrate, wherein the UV light is applied in a manner that the top surfaces of the banks are blocked by the photo mask and thus free of radiation from the UV light emitted from the UV light source; applying the ink into the spaces; and curing the ink so as to form a patterned thin-film layer on the substrate. | 01-08-2009 |
| 20090142864 | METHOD FOR MANUFACTURING THIN FILM TRANSISTOR ARRAY SUBSTRATE - A method for manufacturing a thin film transistor (TFT) array substrate needs only or even less than six mask processes for manufacturing the TFT array substrate integrated with a color filter pattern. Therefore, the manufacturing method is simpler and the manufacturing cost is reduced. In addition, the manufacturing method needs not to form a contact window in a relative thick film layer such as a planarization layer or a color filter layer, so as to connect the pixel electrode to the source/drain. Thus, the difficulty of the manufacturing process is effectively reduced. | 06-04-2009 |
| 20090191691 | Method for singulating semiconductor devices - Disclosed is a method for singulating semiconductor devices. The substrate has a plurality of scribe lines between the substrate units. A protecting film is provided having a patterned adhesive layer formed thereon corresponding to the scribe lines. The protecting film is attached and aligned to the substrate in a manner that the patterned adhesive layer adheres to the scribe lines without covering the substrate units. The substrate is cut by a laser beam aimed at the protecting film firstly and cut through the substrate along the peripheries of the scribe lines to singulate the substrate units. Therefore, the residue films of the protecting film on the substrate units can easily be removed. The contaminations of the substrate units by the sputtered particles and the melted protecting film during laser cutting can be eliminated. The shapes of the substrate units can be diverse. | 07-30-2009 |
| 20090244104 | METHOD FOR DRIVING LCD PANEL AND LCD USING THE SAME - A method for driving an LCD panel and an LCD using the same are provided. The method includes following steps. Firstly, a number of scan signals are provided sequentially, and an enabling time of the scan signals excluding the last scan signal is adjusted according to a compensation time, so as to unfix the enabling time of these scan signals. Next, the scan signals having the unfixed enabling time are sequentially provided to an LCD panel, so as to turn on a number of row pixels of the LCD panel one by one. Thereby, the entire brightness of the LCD can be uniformed by applying the method disclosed in the present invention. | 10-01-2009 |
| Patent application number | Description | Published |
| 20090017590 | METHOD FOR FABRICATING SONOS A MEMORY - A method for fabricating a SONOS memory is disclosed. First, a semiconductor substrate is provided and a SONOS memory cell is formed on said semiconductor substrate. A passivation layer is deposited on the SONOS memory cell and a contact pad is formed on the passivation layer. Subsequently, an ultraviolet treatment is performed and an annealing process is conducted thereafter. | 01-15-2009 |
| 20110250727 | METHOD OF MANUFACTURING FLASH MEMORY DEVICE - A method of manufacturing flash memory device is provided and includes the following steps. First, a substrate is provided. Then, a stacked gate structure is formed on the substrate. Subsequently, a first oxide layer is formed on the stacked gate structure. Following that, a nitride spacer is formed on the first oxide layer, wherein a nitrogen atom-introducing treatment is performed after the forming of the first oxide layer and before the forming of the nitride spacer. Accordingly, the nitrogen atom-introducing treatment of the presentation invention can improve the data retention reliability of the flash memory device. | 10-13-2011 |
| 20110309434 | NONVOLATILE MEMORY DEVICE AND MANUFACTURING METHOD THEREOF - A nonvolatile memory device and a manufacturing method thereof are provided. The manufacturing method includes the following steps. First, a substrate is provided. Then, a tunneling dielectric layer is formed on the substrate, and a dummy gate is form on the tunneling dielectric layer. Subsequently, an interlayer dielectric layer is formed around the dummy gate, and the dummy gate is removed to form an opening. Following that, a charge storage layer is formed on the inner side wall of the opening, and the charge storage layer covers the tunneling dielectric layer. Moreover, an inter-gate dielectric layer is formed on the charge storage layer, and a metal gate is formed on the inter-gate dielectric layer. Accordingly, a stacked gate structure of the nonvolatile memory device includes the tunneling dielectric layer, the charge storage layer, the inter-gate dielectric layer, and the metal gate. | 12-22-2011 |