Patent application number | Description | Published |
20090015111 | MOTOR ASSEMBLY FOR CEILING FAN - A motor assembly for ceiling fans includes a top cover having a plurality of protrusions extending from a top thereof, a bottom cover and a ring-shaped member connected between the top cover and the bottom cover so as to form a case. A shaft rotatably extends through the top cover and the bottom cover. A stator is fixed to the shaft and located in the case, and a permanent magnet is fixed to an inner periphery of the ring-shaped member. A light detection device is connected to the frame and includes a light detection member. A circuit board is located in the light detection device. The protrusions pass through the light detection member to block a light beam emitted from the light detection member to activate the light detection member to send a signal to the circuit board to count the revolution of the shaft. | 01-15-2009 |
20090066197 | WIRELESS SIGNAL TRANSMISSION DEVICE FOR A DC BRUSHLESS CEILING FAN MOTOR - A wireless signal transmission device for a DC brushless ceiling fan motor that includes a wireless signal transmission device to receive and transmit a signal to a controlling unit, and the controlling unit transmits the control signal to the motor via an electric wire. A wireless signal-transmitting device is installed above the motor. The signal-transmitting device detects the position of the motor and transmits a wireless signal to a signal receiving device, which then transmits the signal to the controlling unit, which further transmits the controlling signal to the motor via of the electric wire, for the purpose of controlling the rotation of the motor. Due to the fact that the signal is transmitted wirelessly, it is not necessary to use any destructive process such as drilling a hole on the body of the ceiling fan, and thus the rigidity and the strength of the components are preserved. | 03-12-2009 |
20100013423 | CONTROL CIRCUITRY OF CEILING FAN FOR CONTROLLING ROTATION DIRECTION AND SPEED - A control circuitry of a ceiling fan for controlling speed and direction of rotation of the ceiling fan includes a power switch, an electromagnetic interference reduction circuit connected to the power switch, a power frequency detecting circuit connected to the electromagnetic interference reduction circuit, a central processor connected to the power frequency detecting circuit, a motor driving circuit connected to the central processor and a brushless motor, a rectification and filter circuit connected to the electromagnetic interference reduction circuit and the motor driving circuit, and a power supply circuit connected to the power frequency detecting circuit and the central processor. When the power switch is operated, it will generate interruptions, and the central processor will sense these interruptions and determine which are commands for speed change and which are commands for direction change according to the time of the interruptions to control the brushless motor through the motor driving circuit. | 01-21-2010 |
20100060224 | METHOD OF CONTROLLING SPEED OF BRUSHLESS MOTOR OF CEILING FAN AND THE CIRCUIT THEREOF - The present invention relates to a method and a circuit of controlling a speed of a brushless motor of a ceiling fan. The circuit includes a motor PWM duty consumption sampling unit and a motor speed sampling to sense a PWM duty and a speed of the brushless motor. A central processing unit is provided to compare the PWM duty and the speed of the brushless motor to a preset maximum PWM duty and a preset maximum speed. When the PWM duty reaches to the preset maximum PWM duty first, the central processing unit sets the current speed to be a maximum speed, and speeds of each level are calculated according to the maximum speed. If the speed reaches to the preset maximum speed first, a constant-speed control will take over to control the brushless motor, and speeds of each level are according to the preset speeds. | 03-11-2010 |
Patent application number | Description | Published |
20090101202 | METHOD OF FAST HYDROGEN PASSIVATION TO SOLAR CELLS MADE OF CRYSTALLINE SILICON - A method of improving efficiency of solar cells made of crystalline silicon, including monocrystalline silicon, multicrystalline silicon and polycrystalline silicon is provided. In the method, a negative bias pulse is applied to solar cells at a predetermined voltage, a predetermined frequency, and a predetermined pulse width while immersing the solar cells in a hydrogen plasma. Hydrogen ions are attracted and quickly implanted into the solar cells. Thus, the passivation of crystal defects in the solar cells can be realized in a short period. Meanwhile, the properties of an antireflection layer cannot be damaged as proper operating parameters are used. Consequently, the serious resistance of the solar cells can be significantly reduced and the filling factor increases as a result. Further, the short-circuit current and the open-circuit voltage can be increased. Therefore, the efficiency can be enhanced. | 04-23-2009 |
20090165855 | PASSIVATION LAYER STRUCTURE OF SOLAR CELL AND FABRICATING METHOD THEREOF - A passivation layer structure of a solar cell, disposed on a substrate, is provided. The passivation layer structure has a first passivation layer and a second passivation layer. The first passivation layer is disposed on the substrate. The second passivation layer is disposed between the substrate and the first passivation layer, and the material of the second passivation layer is an oxide of the material of the substrate. Since the second passivation layer is disposed between the substrate and the first passivation layer, the surface passivation effect and carrier lifetime of a photoelectric device are enhanced, and a photoelectric conversion efficiency of the solar cell is increased as well. | 07-02-2009 |
20120132264 | SOLAR CELL AND METHOD FOR FABRICATING THE SAME - A solar cell and a method for fabricating the same are described. A pyramid structure is formed on a silicon substrate. A laser treatment is performed on the pyramid structure, so that a top portion of the pyramid structure has an arc shape, and a round is formed at a crest line of the pyramid structure. Films formed during subsequent processes hence have a uniform thickness and conversion efficiency of the solar cell is improved. | 05-31-2012 |
20120138128 | Solar Cell - A solar cell is disclosed, including the following elements. A through hole passes through a substrate, wherein the substrate includes a third surface in the through hole. A first thin film semiconductor layer is disposed on the third surface in the through hole and extended to be over the second surface of the substrate, wherein the first thin film semiconductor layer is second type. A second thin film semiconductor layer is disposed on the first surface of the substrate. A through hole connection layer is disposed in the through hole and extended to be over the first surface and the second surface of the substrate, wherein a junction is formed between the first thin film semiconductor layer and the substrate to prevent shorts from occurring between the through hole connection layer and the substrate. | 06-07-2012 |
20130133728 | BACK-CONTACT HETEROJUNCTION SOLAR CELL - A back-contact heterojunction solar cell, having a first conductive type silicon substrate, a first amorphous semiconductor layer, a second amorphous semiconductor layer, a first conductive type semiconductor layer, a second conductive type semiconductor layer and a second conductive type doped region is introduced. The first amorphous semiconductor layer disposed on the illuminated surface of the silicon substrate is an intrinsic semiconductor layer or is of the first conductive type. The second amorphous semiconductor layer disposed on the non-illuminated surface of the silicon substrate is an intrinsic semiconductor layer. The first and the second conductive type semiconductor layers are disposed on the second amorphous semiconductor layer. The second conductive type doped region is located in the silicon substrate under the second conductive type semiconductor layer and is in contact with the second amorphous semiconductor layer. | 05-30-2013 |
20130174903 | SOLAR CELL - A solar cell is disclosed. A substrate includes a first surface and a second surface, wherein the substrate is of a first type. A through hole passes through the substrate, wherein the substrate includes a third surface in the through hole. An insulating layer is on the third surface in the through hole and extends to be over the second surface of the substrate. A first thin film semiconductor layer is disposed on the first surface of the substrate, wherein the first thin film semiconductor layer is of a first type. A transparent conductive layer is on the first thin film semiconductor layer. A through hole connection layer is disposed in the through hole and extends to be over the first surface and the second surface of the substrate. | 07-11-2013 |
20130217171 | METHOD FOR FABRICATING SEMICONDUCTOR LAYER HAVING TEXTURED SURFACE AND METHOD FOR FABRICATING SOLAR CELL - The disclosure provides a method for fabricating a semiconductor layer having a textured surface, including: (a) providing a textured substrate; (b) forming at least one semiconductor layer on the textured substrate; (c) forming a metal layer on the semiconductor layer; and (d) conducting a thermal process to the textured substrate, the semiconductor layer and the metal layer, wherein the semiconductor layer is separated from the textured substrate by the thermal process to obtain the semiconductor layer having the metal layer and a textured surface. | 08-22-2013 |
20130237005 | METHOD FOR FABRICATING SEMICONDUCTOR LAYER HAVING TEXTURED SURFACE AND METHOD FOR FABRICATING SOLAR CELL - The disclosure provides a method for fabricating a semiconductor layer having a textured surface, including: (a) providing a textured substrate; (b) forming at least one semiconductor layer on the textured substrate; (c) forming a metal layer on the semiconductor layer; and (d) conducting a thermal process or a low temperature process to the textured substrate, the semiconductor layer and the metal layer, wherein the semiconductor layer is separated from the textured substrate by the thermal process to obtain the semiconductor layer having the metal layer and a textured surface. | 09-12-2013 |
Patent application number | Description | Published |
20130342290 | EQUALIZER FOR LOSS-COMPENSATION OF HIGH-FREQUENCY SIGNALS GENERATED IN TRANSMISSION CHANNELS - An equalizer for compensating transmission losses of electronic communication signals includes a circuit board and a compensation module. The compensation module includes a pair of input pins, a pair of output pins, first and second resistors, first and second vias, and a pair of micro-strips. When a signal transmitted by the circuit board is received by the input pins, a first part of the signal is directly outputted from the output pins, a second part of the signal is reflected by the first resistor and transmitted back to the output pins to be outputted, and a third part of the signal is reflected by the second resistor and transmitted back to the output pins to be outputted, such that the output of the equalizer applies two stages of compensation. | 12-26-2013 |
20140167887 | EQUALIZER FOR LOSS-COMPENSATION OF HIGH-FREQUENCY SIGNALS GENERATED IN TRANSMISSION CHANNELS - An equalizer includes a circuit board and a compensation module. The compensation module includes first and second transmission lines, first to fourth resistors, and first to fourth micro-strips. Four vias extend through the circuit board and are grounded. First terminals of the four resistors are grounded through the vias. A second terminal of a first resistor is connected to a second terminal of the second resistor through the first micro-strip, and is connected to the first transmission line through the second micro-strip. A second terminal of the third resistor is connected to the second transmission line through the third micro-strip, and is connected to a second terminal of the fourth resistor through the fourth micro-strip. A length of the first micro-strip is equal to a length of the fourth micro-strip. A length of the second micro-strip is equal to a length of the third micro-strip. | 06-19-2014 |
20140167888 | EQUALIZER FOR LOSS-COMPENSATION OF HIGH-FREQUENCY SIGNALS GENERATED IN TRANSMISSION CHANNELS - An equalizer includes a circuit board and a compensation module. The compensation module includes first and second transmission lines, first to fourth resistors, and first to fourth micro-strips. Two vias extend through the circuit board and are grounded. First terminals of the first and second resistors are electrically connected to the ground layer through the first via. First terminals of the third and fourth resistors are electrically connected to the ground layer through the second via. A second terminal of the first resistor is electrically connected to the first transmission line through the first micro-strip, and is further electrically connected to a second terminal of the second resistor through the second micro-strip. A second terminal of the third resistor is electrically connected to the second transmission line through the third micro-strip, and is further electrically connected to a second terminal of the fourth resistor through the fourth micro-strip. | 06-19-2014 |