| Patent application number | Description | Published |
|---|
| 20080274589 | Wafer-level flip-chip assembly methods - A method of packaging integrated circuit structures is provided. The method includes providing a wafer having bonding conductors on a surface of the wafer, and applying a compound underfill onto the surface of the wafer. The compound underfill includes an underfill material and a flux material. A die is then bonded on the wafer after the step of applying the compound underfill, wherein solder bumps on the die are joined with the bonding conductors. | 11-06-2008 |
| 20080274592 | Process and apparatus for wafer-level flip-chip assembly - A method of forming an integrated circuit structure is provided. The method includes providing an interposer wafer; mounting the interposer wafer onto a handling wafer; thinning a backside of the interposer wafer; removing the handling wafer from the interposer wafer after the step of thinning; securing the interposer wafer on a fixture; and bonding a die on the interposer wafer. | 11-06-2008 |
| 20090011543 | Enhanced Reliability of Wafer-Level Chip-Scale Packaging (WLCSP) Die Separation Using Dry Etching - An improved Wafer-Level Chip-Scale Packaging (WLCSP) process is described that includes forming a plurality of conductive pillars on a first surface of a semiconductor wafer. One or more grooves are dry etched into the first surface of the semiconductor wafer, where the grooves define at least one boundary between each of a plurality of die within the semiconductor wafer. A layer of encapsulating material is deposited over the first surface. A recess is then cut in each of the grooves through the encapsulating material, where the cutting leaves a piece of semiconductor material on the second surface of the semiconductor wafer. The second surface is then ground to remove the piece of semiconductor material, where the removal of this material separates the plurality of die. | 01-08-2009 |
| 20090096085 | Thermally Enhanced Wafer Level Package - A method of forming a package structure includes providing a plurality of dies; attaching the plurality of dies onto a heat-dissipating plate; and sawing the heat-dissipating plate into a plurality of packages, each including one of the plurality of dies and a piece of the heat-dissipating plate. | 04-16-2009 |
| 20090130840 | Protected Solder Ball Joints in Wafer Level Chip-Scale Packaging - Protection of a solder ball joint is disclosed in which the solder ball joint is located below the surface level of the encapsulating buffer layer. The buffering layer is etched to expose one or more electrode posts, each of which may be made up of a single column or multiple columns. A top layer resulting either from a top conductive cap or a plating layer around the electrode posts also lies below the buffer layer. When the solder ball is placed onto the posts, the solder/ball joint is protected in a position below the surface of the buffer layer, while still maintaining an electrical connection between the various solder balls and their associated or capping/plating material, electrode posts, wiring layers, and circuit layers. Therefore, the entire ball joint is protected from direct stress. | 05-21-2009 |
| 20090263214 | FIXTURE FOR P-THROUGH SILICON VIA ASSEMBLY - A silicon-based wafer such as a TSV interposer wafer having a first and second surfaces wherein a glass carrier is mounted on the second surface by a UV tape is held by a vacuum holder applied on the first surface and the glass carrier is removed from the silicon-based wafer by irradiating the UV tape with a UV light through the glass carrier. The silicon-based wafer is then flipped and placed onto a vacuum plate and secured to the vacuum plate by applying vacuum to the vacuum plate. The vacuum holder is then released from the silicon-based wafer leaving the silicon-based wafer secured to the vacuum plate for subsequent processing steps. | 10-22-2009 |
| 20100047963 | Through Silicon Via Bonding Structure - System and method for bonding semiconductor substrates is presented. A preferred embodiment comprises forming a buffer layer over a surface of a semiconductor substrate while retaining TSVs that protrude from the buffer layer in order to prevent potential voids that might form. A protective layer is formed on another semiconductor substrate that will be bonded to the first semiconductor substrate. The two substrates are aligned and bonded together, with the buffer layer preventing any short circuit contacts to the surface of the original semiconductor substrate. | 02-25-2010 |
| 20100093135 | STRATIFIED UNDERFILL METHOD FOR AN IC PACKAGE - A method includes joining an integrated circuit die having at least one low-k dielectric layer to a package substrate or printed circuit board using a plurality of solder bumps located between the die and the package substrate or printed circuit board. The low-k dielectric layer has a dielectric constant of about 3.0 or less. The solder bumps have a lead concentration of about 5% or less. A stratified underfill is formed between the die and the package substrate or printed circuit board. | 04-15-2010 |
| 20100273296 | Thermally Enhanced Wafer Level Package - A method of forming a package structure includes providing a plurality of dies; attaching the plurality of dies onto a heat-dissipating plate; and sawing the heat-dissipating plate into a plurality of packages, each including one of the plurality of dies and a piece of the heat-dissipating plate. | 10-28-2010 |
| 20100314756 | Interconnect Structures Having Lead-Free Solder Bumps - An integrated circuit structure includes a semiconductor substrate, and a polyimide layer over the semiconductor substrate. An under-bump-metallurgy (UBM) has a first portion over the polyimide layer, and a second portion level with the polyimide layer. A first solder bump and a second solder bump are formed over the polyimide layer, with a pitch between the first solder bump and the second solder bump being no more than 150 μm. A width of the UBM equals one-half of the pitch plus a value greater than 5 μm. | 12-16-2010 |
| 20110051378 | Wafer-Level Molded Structure for Package Assembly - An integrated circuit structure includes a bottom die; a top die bonded to the bottom die with the top die having a size smaller than the bottom die; and a molding compound over the bottom die and the top die. The molding compound contacts edges of the top die. The edges of the bottom die are vertically aligned to respective edges of the molding compound. | 03-03-2011 |
