Patent application number | Description | Published |
20120267767 | SEMICONDUCTOR OVERLAPPED PN STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention discloses a semiconductor overlapped PN structure and manufacturing method thereof. The method includes: providing a substrate; providing a first mask to define a P (or N) type well and at least one overlapped region in the substrate; implanting P (or N) type impurities into the P (or N) type well and the at least one overlapped region; providing a second mask having at least one opening to define an N (or P) type well in the substrate, and to define at least one dual-implanted region in the at least one overlapped region; implanting N (or P) type impurities into the N (or P) type well and the at least one dual-implanted region such that the at least one dual-implanted region has P type and N type impurities. | 10-25-2012 |
20120280320 | High voltage device and manufacturing method thereof - The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate includes isolation regions defining a device region. The high voltage device includes: a drift region, located in the device region, doped with second conductive type impurities; a gate in the device region and on the surface of the substrate; and a second conductive type source and drain in the device region, at different sides of the gate respectively. From top view, the concentration of the second conductive type impurities of the drift region is distributed substantially periodically along horizontal and vertical directions. | 11-08-2012 |
20130069153 | High Voltage Device and Manufacturing Method Thereof - The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device includes: a substrate, having an isolation structure for defining a device region; a drift region located in the device region, wherein from top view, the drift region includes multiple sub-regions separated from one another but are electrically connected with one another; a source and a drain in the device region; and a gate on the surface of the substrate and between the source and drain in the device region. | 03-21-2013 |
20130181253 | SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF - The present invention discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure is formed in a first conductive type substrate, which has an upper surface. The semiconductor structure includes: a protected device, at least a buried trench, and at least a doped region. The protected device is formed in the substrate. The buried trench is formed below the upper surface with a first depth, and the buried trench surrounds the protected device from top view. The doped region is formed below the upper surface with a second depth, and the doped region surrounds the buried trench from top view. The second depth is not less than the first depth. | 07-18-2013 |
20130181319 | Trench Schottky Barrier Diode and Manufacturing Method Thereof - The present invention discloses a trench Schottky barrier diode (SBD) and a manufacturing method thereof. The trench SBD includes: an epitaxial layer, formed on a substrate; multiple mesas, defined by multiple trenches; a field plate, formed on the epitaxial layer and filled in the multiple trenches, wherein a Schottky contact is formed between the field plate and top surfaces of the mesas; a termination region, formed outside the multiple mesas and electrically connected to the field plate; a field isolation layer, formed on the upper surface and located outside the termination region; and at least one mitigation electrode, formed below the upper surface outside the termination region, and is electrically connected to the field plate through the field isolation layer, wherein the mitigation electrode and the termination region are separated by part of a dielectric layer and part of the epitaxial layer. | 07-18-2013 |
20130313641 | DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE - The present invention discloses a double diffused metal oxide semiconductor (DMOS) device. The DMOS device is formed in a substrate, and includes a high voltage well, a first field oxide region, a first gate, a first source, a drain, a body region, a body electrode, a second field oxide region, a second gate, and a second source. The second field oxide region and the first field oxide region are separated by the high voltage well and the body region. A part of the second gate is on the second field oxide region, and another part of the second gate is on the body region. The second gate is electrically connected to the first gate, and the second source is electrically connected to the first source, such that when the DMOS device is ON, a surface channel and a buried channel are formed. | 11-28-2013 |
20130341719 | Hybrid High Voltage Device and Manufacturing Method Thereof - The present invention discloses a hybrid high voltage device and a manufacturing method thereof. The hybrid high voltage device is formed in a first conductive type substrate, and includes at least one lateral double diffused metal oxide semiconductor (LDMOS) device region and at least one vent device region, wherein the LDMOS device region and the vent device region are connected in a width direction and arranged in an alternating order. Besides, corresponding high voltage wells, sources, drains, body regions, and gates of the LDMOS device region and the vent device region are connected to each other respectively. | 12-26-2013 |
20140021544 | Double Diffused Drain Metal Oxide Semiconductor Device and Manufacturing Method Thereof - The present invention discloses a double diffused drain metal oxide semiconductor (DDDMOS) device and a manufacturing method thereof. The DDDMOS device is formed in a substrate, and includes a first well, a gate, a diffusion region, a source, and a drain. A low voltage device is also formed in the substrate, which includes a second well and a lightly doped drain (LDD) region, wherein the first well and the diffusion region are formed by process steps which also form the second well and the LDD region in the low voltage device, respectively. | 01-23-2014 |
20140151796 | HYBRID HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF - The present invention discloses a hybrid high voltage device and a manufacturing method thereof. The hybrid high voltage device is formed in a first conductive type substrate, and includes at least one lateral double diffused metal oxide semiconductor (LDMOS) device region and at least one vent device region, wherein the LDMOS device region and the vent device region are connected in a width direction and arranged in an alternating order. Besides, corresponding high voltage wells, sources, drains, body regions, and gates of the LDMOS device region and the vent device region are connected to each other respectively. | 06-05-2014 |
20140151799 | Double Diffused Drain Metal Oxide Semiconductor Device and Manufacturing Method Thereof - The present invention discloses a double diffused drain metal oxide semiconductor (DDDMOS) device and a manufacturing method thereof. The DDDMOS device is formed in a substrate, and includes a first well, a gate, a diffusion region, a source, and a drain. A low voltage device is also formed in the substrate, which includes a second well and a lightly doped drain (LDD) region, wherein the first well and the diffusion region are formed by process steps which also form the second well and the LDD region in the low voltage device, respectively. | 06-05-2014 |
20140315358 | MANUFACTURING METHOD OF JUNCTION FIELD EFFECT TRANSISTOR - The present invention discloses a manufacturing method of a junction field effect transistor (JFET). The manufacturing method includes: providing a substrate with a first conductive type, forming a channel region with a second conductive type, forming a field region with the first conductive type, forming a gate with the first conductive type, forming a source with the second conductive type, forming a drain with the second conductive type, and forming a lightly doped region with the second conductive type. The channel region is formed by an ion implantation process step, wherein the lightly doped region is formed by masking a predetermined region from accelerated ions of the ion implantation process step, and diffusing impurities with the second conductive type nearby the predetermined region into it with a thermal process step. | 10-23-2014 |
20150028417 | HIGH VOLTAGE DEVICE AND MANUFACTURING METHOD THEREOF - The present invention discloses a high voltage device and a manufacturing method thereof. The high voltage device is formed in a first conductive type substrate, wherein the substrate includes isolation regions defining a device region. The high voltage device includes: a drift region, located in the device region, doped with second conductive type impurities; a gate in the device region and on the surface of the substrate; and a second conductive type source and drain in the device region, at different sides of the gate respectively. From top view, the concentration of the second conductive type impurities of the drift region is distributed substantially periodically along horizontal and vertical directions. | 01-29-2015 |